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authorJoe McGill <jmcgill@us.ibm.com>2016-12-15 00:12:48 -0600
committerDaniel M. Crowell <dcrowell@us.ibm.com>2018-05-09 00:28:01 -0400
commit37931b3b0f8f291696059c8b42dc558cfe3c3719 (patch)
tree0f76e32e66a08d60cb2935f3a448842510e9cb06
parent496e3d430783bf3e1309a69b19f3ddb183d6df97 (diff)
downloadtalos-hostboot-37931b3b0f8f291696059c8b42dc558cfe3c3719.tar.gz
talos-hostboot-37931b3b0f8f291696059c8b42dc558cfe3c3719.zip
Add MSS customization support from CRP0 Lx MVPD
Keyword V0 offsets are the same as V1 Move bad-bits error processing to 1.03 Change-Id: I233b3142ea8e8b08621b88a4b3af5417bbde5745 Original-Change-Id: I01e44c83f775b77e4ecc7afd7a5d92db524dfc98 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34073 Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58313
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/tests/p9_mss_ut.mk1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/tests/p9_mss_ut.mk b/src/import/chips/p9/procedures/hwp/memory/tests/p9_mss_ut.mk
index 48e9a21e1..c58ce4318 100644
--- a/src/import/chips/p9/procedures/hwp/memory/tests/p9_mss_ut.mk
+++ b/src/import/chips/p9/procedures/hwp/memory/tests/p9_mss_ut.mk
@@ -50,6 +50,7 @@ $(WRAPPER)_DEPLIBS+=p9_mss_freq_drift
$(WRAPPER)_DEPLIBS+=p9_mss_scominit
$(WRAPPER)_DEPLIBS+=p9_mss_thermal_init
$(WRAPPER)_DEPLIBS+=p9_mss_throttle_mem
+$(WRAPPER)_DEPLIBS+=p9_mss_attr_update
# USELIBS to get the header, DEPLIBS to get the so
$(WRAPPER)_USELIBS+=p9_getecid
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