diff options
| author | Zane Shelley <zshelle@us.ibm.com> | 2018-04-25 21:50:14 -0500 |
|---|---|---|
| committer | Zane C. Shelley <zshelle@us.ibm.com> | 2018-04-27 21:30:50 -0400 |
| commit | f848b1fc2c753141bad799d075045e41c28dc0cb (patch) | |
| tree | f8adc5efe7c9c2fda08f6d73286a8c4e79ffb6ce | |
| parent | 096bf926ad629fae603499bd5fbdeba19cf818b5 (diff) | |
| download | talos-hostboot-f848b1fc2c753141bad799d075045e41c28dc0cb.tar.gz talos-hostboot-f848b1fc2c753141bad799d075045e41c28dc0cb.zip | |
PRD: register capture groups for Centaur
Change-Id: I6c17a4724fc42a54f9ca3f2ddecade8f82954b30
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57860
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com>
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57933
CI-Ready: Zane C. Shelley <zshelle@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
16 files changed, 510 insertions, 3842 deletions
diff --git a/src/usr/diag/prdf/common/plat/cen/cen_centaur.rule b/src/usr/diag/prdf/common/plat/cen/cen_centaur.rule index da358c8b7..6c74be378 100644 --- a/src/usr/diag/prdf/common/plat/cen/cen_centaur.rule +++ b/src/usr/diag/prdf/common/plat/cen/cen_centaur.rule @@ -327,6 +327,7 @@ chip cen_centaur reset (&, 0x02011441); mask (|, 0x02011445); capture group default; + capture group MaintCmdRegs_mba0; }; register MBSECCFIR_0_MASK @@ -334,6 +335,7 @@ chip cen_centaur name "Centaur chip MBSECCFIR 0 MASK"; scomaddr 0x02011443; capture group default; + capture group MaintCmdRegs_mba0; }; register MBSECCFIR_0_ACT0 @@ -341,6 +343,7 @@ chip cen_centaur name "Centaur chip MBSECCFIR 0 ACT0"; scomaddr 0x02011446; capture group default; + capture group MaintCmdRegs_mba0; capture req nonzero("MBSECCFIR_0"); }; @@ -349,6 +352,7 @@ chip cen_centaur name "Centaur chip MBSECCFIR 0 ACT1"; scomaddr 0x02011447; capture group default; + capture group MaintCmdRegs_mba0; capture req nonzero("MBSECCFIR_0"); }; @@ -363,6 +367,7 @@ chip cen_centaur reset (&, 0x02011481); mask (|, 0x02011485); capture group default; + capture group MaintCmdRegs_mba1; }; register MBSECCFIR_1_MASK @@ -370,6 +375,7 @@ chip cen_centaur name "Centaur chip MBSECCFIR 1 MASK"; scomaddr 0x02011483; capture group default; + capture group MaintCmdRegs_mba1; }; register MBSECCFIR_1_ACT0 @@ -377,6 +383,7 @@ chip cen_centaur name "Centaur chip MBSECCFIR 1 ACT0"; scomaddr 0x02011486; capture group default; + capture group MaintCmdRegs_mba1; capture req nonzero("MBSECCFIR_1"); }; @@ -385,6 +392,7 @@ chip cen_centaur name "Centaur chip MBSECCFIR 1 ACT1"; scomaddr 0x02011487; capture group default; + capture group MaintCmdRegs_mba1; capture req nonzero("MBSECCFIR_1"); }; @@ -504,21 +512,21 @@ chip cen_centaur { name "MEM Chiplet Checkstop FIR"; scomaddr 0x03040000; - capture group default; + capture group MemChipletRegs; }; register MEM_CHIPLET_RE_FIR { name "MEM Chiplet Recoverable FIR"; scomaddr 0x03040001; - capture group default; + capture group MemChipletRegs; }; register MEM_CHIPLET_FIR_MASK { name "MEM Chiplet FIR MASK"; scomaddr 0x03040002; - capture group default; + capture group MemChipletRegs; }; ############################################################################ @@ -529,14 +537,14 @@ chip cen_centaur { name "MEM Chiplet Special Attention FIR"; scomaddr 0x03040004; - capture group default; + capture group MemChipletRegs; }; register MEM_CHIPLET_SPA_FIR_MASK { name "MEM Chiplet Special Attention FIR MASK"; scomaddr 0x03040007; - capture group default; + capture group MemChipletRegs; }; ############################################################################ @@ -549,21 +557,21 @@ chip cen_centaur scomaddr 0x0304000A; reset (&, 0x0304000B); mask (|, 0x0304000F); - capture group default; + capture group MemChipletRegs; }; register MEM_LFIR_MASK { name "Centaur chip MEM_LFIR MASK"; scomaddr 0x0304000D; - capture group default; + capture group MemChipletRegs; }; register MEM_LFIR_ACT0 { name "Centaur chip MEM_LFIR ACT0"; scomaddr 0x03040010; - capture group default; + capture group MemChipletRegs; capture req nonzero("MEM_LFIR"); }; @@ -571,7 +579,7 @@ chip cen_centaur { name "Centaur chip MEM_LFIR ACT1"; scomaddr 0x03040011; - capture group default; + capture group MemChipletRegs; capture req nonzero("MEM_LFIR"); }; @@ -618,7 +626,7 @@ group gGLOBAL_FIR attntype UNIT_CS, RECOVERABLE filter singlebit /** GLOBAL_FIR[3] * Attention from MEM chiplet */ - (rGLOBAL_FIR, bit(3)) ? analyze(gMEM_CHIPLET_FIR); + (rGLOBAL_FIR, bit(3)) ? analyzeMemChipletFir; }; @@ -637,7 +645,7 @@ group gGLOBAL_SPA_FIR attntype HOST_ATTN filter singlebit /** GLOBAL_SPA_FIR[3] * Attention from MEM chiplet */ - (rGLOBAL_SPA_FIR, bit(3)) ? analyze(gMEM_CHIPLET_SPA_FIR); + (rGLOBAL_SPA_FIR, bit(3)) ? analyzeMemChipletSpa; }; diff --git a/src/usr/diag/prdf/common/plat/cen/cen_centaur_actions.rule b/src/usr/diag/prdf/common/plat/cen/cen_centaur_actions.rule index 5eb5716ee..acc68a0e2 100644 --- a/src/usr/diag/prdf/common/plat/cen/cen_centaur_actions.rule +++ b/src/usr/diag/prdf/common/plat/cen/cen_centaur_actions.rule @@ -23,6 +23,20 @@ # # IBM_PROLOG_END_TAG +/** There is a small window during the IPL where the MEM chiplet may be offline + * while the rest of the chip is working. Therefore, we cannot capture those + * registers unless we have an active attention from the MEM chiplet. */ +actionclass analyzeMemChipletFir +{ + capture(MemChipletRegs); + analyze(gMEM_CHIPLET_FIR); +}; +actionclass analyzeMemChipletSpa +{ + capture(MemChipletRegs); + analyze(gMEM_CHIPLET_SPA_FIR); +}; + /** Callout the connected MBA 0 */ actionclass calloutMba0 { callout(connected(TYPE_MBA, 0), MRU_MED); }; @@ -206,18 +220,26 @@ actionclass mainline_nce_handling_0 { funccall("AnalyzeFetchNce0"); }; actionclass mainline_nce_handling_1 { funccall("AnalyzeFetchNce1"); }; /** Fetch UE */ -actionclass mainline_ue_handling_0_UERE +actionclass mainline_ue_0 { funccall("AnalyzeFetchUe0"); threshold( field(33 / 30 min) ); SueSource; }; -actionclass mainline_ue_handling_1_UERE +actionclass mainline_ue_1 { funccall("AnalyzeFetchUe1"); threshold( field(33 / 30 min) ); SueSource; }; +actionclass mainline_ue_handling_0_UERE +{ + try ( funccall("analyzeMbaRcdParityError0"), mainline_ue_0 ); +}; +actionclass mainline_ue_handling_1_UERE +{ + try ( funccall("analyzeMbaRcdParityError1"), mainline_ue_1 ); +}; /** Fetch RCE or Prefetch UE */ actionclass mainline_rce_pue_handling_0 { funccall("AnalyzeFetchRcePue0"); }; diff --git a/src/usr/diag/prdf/common/plat/cen/cen_centaur_regs.rule b/src/usr/diag/prdf/common/plat/cen/cen_centaur_regs.rule index 6c375feec..aa0d70b66 100644 --- a/src/usr/diag/prdf/common/plat/cen/cen_centaur_regs.rule +++ b/src/usr/diag/prdf/common/plat/cen/cen_centaur_regs.rule @@ -27,6 +27,14 @@ # Centaur chip TP_LFIR ############################################################################ + register TP_LFIR_AND + { + name "Centaur chip TP_LFIR atomic AND"; + scomaddr 0x0104000b; + capture group never; + access write_only; + }; + register TP_LFIR_MASK_OR { name "Centaur chip TP_LFIR MASK atomic OR"; @@ -36,6 +44,18 @@ }; ############################################################################ + # Centaur chip MBIFIR + ############################################################################ + + register MBIFIR_AND + { + name "Centaur chip MBIFIR atomic AND"; + scomaddr 0x02010801; + capture group never; + access write_only; + }; + + ############################################################################ # Centaur chip MBSFIR ############################################################################ @@ -112,6 +132,227 @@ }; ############################################################################ + # TP chiplet error report registers + ############################################################################ + + register TP_ERROR_STATUS + { + name "TPTOP.TPC.ERROR_STATUS"; + scomaddr 0x01030009; + capture group default; + }; + + ############################################################################ + # NEST chiplet error report registers + ############################################################################ + + register NEST_ERROR_STATUS + { + name "TCN.ERROR_STATUS"; + scomaddr 0x02030009; + capture group default; + }; + + register MBIERPT + { + name "MBU.MBI.MBI.MBIERPT0"; + scomaddr 0x0201080F; + capture group default; + }; + + register MBSCERR1 + { + name "MBU.MBS.MBSCERR1Q"; + scomaddr 0x02011413; + capture group default; + }; + + register MBSCERR2 + { + name "MBU.MBS.MBSCERR2Q"; + scomaddr 0x0201142C; + capture group default; + }; + + register MBA0_MBSECCERRPT_0 + { + name "MBU.MBS.ECC01.MBSECCERR0"; + scomaddr 0x02011466; + capture group default; + capture group MaintCmdRegs_mba0; + }; + + register MBA0_MBSECCERRPT_1 + { + name "MBU.MBS.ECC01.MBSECCERR1"; + scomaddr 0x02011467; + capture group default; + capture group MaintCmdRegs_mba0; + }; + + register MBA1_MBSECCERRPT_0 + { + name "MBU.MBS.ECC23.MBSECCERR0"; + scomaddr 0x020114A6; + capture group default; + capture group MaintCmdRegs_mba1; + }; + + register MBA1_MBSECCERRPT_1 + { + name "MBU.MBS.ECC23.MBSECCERR1"; + scomaddr 0x020114A7; + capture group default; + capture group MaintCmdRegs_mba1; + }; + + register MBA0_MBXERRSTAT + { + name "MBU.MBS.MCBISTS01.SCOMFIR.MBXERRSTATQ"; + scomaddr 0x0201168f; + capture group default; + }; + + register MBA1_MBXERRSTAT + { + name "MBU.MBS.MCBISTS23.SCOMFIR.MBXERRSTATQ"; + scomaddr 0x0201178f; + capture group default; + }; + + register SENSORCACHEERRPT + { + name "SCAC.SCAC_ERRRPT"; + scomaddr 0x020115D4; + capture group default; + }; + + ############################################################################ + # MEM chiplet error report registers + ############################################################################ + + register MEM_ERROR_STATUS + { + name "TCM.ERROR_STATUS"; + scomaddr 0x03030009; + capture group MemChipletRegs; + }; + + ############################################################################ + # Memory ECC Error Address Registers + ############################################################################ + + register MBA0_MBNCER + { + name "MBA0: MBS Memory NCE Error Address Register"; + scomaddr 0x02011660; + capture group default; + }; + + register MBA0_MBRCER + { + name "MBA0: MBS Memory RCE Error Address Register"; + scomaddr 0x02011661; + capture group default; + }; + + register MBA0_MBMPER + { + name "MBA0: MBS Memory MPE Error Address Register"; + scomaddr 0x02011662; + capture group default; + }; + + register MBA0_MBUER + { + name "MBA0: MBS Memory UE Error Address Register"; + scomaddr 0x02011663; + capture group default; + }; + + register MBA1_MBNCER + { + name "MBA1: MBS Memory NCE Error Address Register"; + scomaddr 0x02011760; + capture group default; + }; + + register MBA1_MBRCER + { + name "MBA1: MBS Memory RCE Error Address Register"; + scomaddr 0x02011761; + capture group default; + }; + + register MBA1_MBMPER + { + name "MBA1: MBS Memory MPE Error Address Register"; + scomaddr 0x02011762; + capture group default; + }; + + register MBA1_MBUER + { + name "MBA1: MBS Memory UE Error Address Register"; + scomaddr 0x02011763; + capture group default; + }; + + ############################################################################ + # NEST Chiplet memory fetch error vector registers + ############################################################################ + + register MBA0_MBSEVR + { + name "MBU.MBS.MCBISTS01.SCOMFIR.MBSEVRQ"; + scomaddr 0x0201165f; + capture group default; + }; + + register MBA1_MBSEVR + { + name "MBU.MBS.MCBISTS23.SCOMFIR.MBSEVRQ"; + scomaddr 0x0201175f; + capture group default; + }; + + ############################################################################ + # NEST Chiplet memory maintenance error count registers + ############################################################################ + + register MBA0_MBSEC0 + { + name "MBU.MBS.MCBISTS01.SCOMFIR.MBSEC0Q"; + scomaddr 0x02011653; + capture group default; + capture group MaintCmdRegs_mba0; + }; + + register MBA0_MBSEC1 + { + name "MBU.MBS.MCBISTS01.SCOMFIR.MBSEC1Q"; + scomaddr 0x02011654; + capture group default; + capture group MaintCmdRegs_mba0; + }; + + register MBA1_MBSEC0 + { + name "MBU.MBS.MCBISTS23.SCOMFIR.MBSEC0Q"; + scomaddr 0x02011753; + capture group default; + capture group MaintCmdRegs_mba1; + }; + + register MBA1_MBSEC1 + { + name "MBU.MBS.MCBISTS23.SCOMFIR.MBSEC1Q"; + scomaddr 0x02011754; + capture group default; + capture group MaintCmdRegs_mba1; + }; + + ############################################################################ # Memory maintenance threshold control registers ############################################################################ @@ -132,6 +373,183 @@ }; ############################################################################ + # NEST Chiplet memory maintenance symbol error control registers + ############################################################################ + + register MBA0_MBSSYMEC0 + { + name "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC0Q"; + scomaddr 0x02011656; + capture group default; + capture group MaintCmdRegs_mba0; + }; + + register MBA0_MBSSYMEC1 + { + name "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC1Q"; + scomaddr 0x02011657; + capture group default; + capture group MaintCmdRegs_mba0; + }; + + register MBA0_MBSSYMEC2 + { + name "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC2Q"; + scomaddr 0x02011658; + capture group default; + capture group MaintCmdRegs_mba0; + }; + + register MBA0_MBSSYMEC3 + { + name "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC3Q"; + scomaddr 0x02011659; + capture group default; + capture group MaintCmdRegs_mba0; + }; + + register MBA0_MBSSYMEC4 + { + name "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC4Q"; + scomaddr 0x0201165a; + capture group default; + capture group MaintCmdRegs_mba0; + }; + + register MBA0_MBSSYMEC5 + { + name "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC5Q"; + scomaddr 0x0201165b; + capture group default; + capture group MaintCmdRegs_mba0; + }; + + register MBA0_MBSSYMEC6 + { + name "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC6Q"; + scomaddr 0x0201165c; + capture group default; + capture group MaintCmdRegs_mba0; + }; + + register MBA0_MBSSYMEC7 + { + name "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC7Q"; + scomaddr 0x0201165d; + capture group default; + capture group MaintCmdRegs_mba0; + }; + + register MBA0_MBSSYMEC8 + { + name "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC8Q"; + scomaddr 0x0201165e; + capture group default; + capture group MaintCmdRegs_mba0; + }; + + register MBA1_MBSSYMEC0 + { + name "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC0Q"; + scomaddr 0x02011756; + capture group default; + capture group MaintCmdRegs_mba1; + }; + + register MBA1_MBSSYMEC1 + { + name "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC1Q"; + scomaddr 0x02011757; + capture group default; + capture group MaintCmdRegs_mba1; + }; + + register MBA1_MBSSYMEC2 + { + name "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC2Q"; + scomaddr 0x02011758; + capture group default; + capture group MaintCmdRegs_mba1; + }; + + register MBA1_MBSSYMEC3 + { + name "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC3Q"; + scomaddr 0x02011759; + capture group default; + capture group MaintCmdRegs_mba1; + }; + + register MBA1_MBSSYMEC4 + { + name "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC4Q"; + scomaddr 0x0201175a; + capture group default; + capture group MaintCmdRegs_mba1; + }; + + register MBA1_MBSSYMEC5 + { + name "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC5Q"; + scomaddr 0x0201175b; + capture group default; + capture group MaintCmdRegs_mba1; + }; + + register MBA1_MBSSYMEC6 + { + name "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC6Q"; + scomaddr 0x0201175c; + capture group default; + capture group MaintCmdRegs_mba1; + }; + + register MBA1_MBSSYMEC7 + { + name "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC7Q"; + scomaddr 0x0201175d; + capture group default; + capture group MaintCmdRegs_mba1; + }; + + register MBA1_MBSSYMEC8 + { + name "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC8Q"; + scomaddr 0x0201175e; + capture group default; + capture group MaintCmdRegs_mba1; + }; + + ############################################################################ + # MBA Address Translate Control Register + ############################################################################ + + register MBA0_MBAXCR + { + name "MBU.MBS.ARB.RXLT.MBAXCR01Q"; + scomaddr 0x0201140B; + capture group default; + }; + + register MBA1_MBAXCR + { + name "MBU.MBS.ARB.RXLT.MBAXCR23Q"; + scomaddr 0x0201140C; + capture group default; + }; + + ############################################################################ + # MBS Address Translate Control Register + ############################################################################ + + register MBSXCR + { + name "MBU.MBS.ARB.RXLT.MBSXCRQ"; + scomaddr 0x0201140A; + capture group never; + }; + + ############################################################################ # Non-existent Registers for Capture ############################################################################ diff --git a/src/usr/diag/prdf/common/plat/cen/cen_mba.rule b/src/usr/diag/prdf/common/plat/cen/cen_mba.rule index 25ef56c00..69a532b5d 100644 --- a/src/usr/diag/prdf/common/plat/cen/cen_mba.rule +++ b/src/usr/diag/prdf/common/plat/cen/cen_mba.rule @@ -143,6 +143,7 @@ chip cen_mba reset (&, 0x03010612); mask (|, 0x03010614); capture group default; + capture group MaintCmdRegs; }; register MBASPA_MASK @@ -150,6 +151,7 @@ chip cen_mba name "Centaur chip MBA target MBASPA MASK"; scomaddr 0x03010614; capture group default; + capture group MaintCmdRegs; }; ############################################################################ diff --git a/src/usr/diag/prdf/common/plat/cen/cen_mba_regs.rule b/src/usr/diag/prdf/common/plat/cen/cen_mba_regs.rule index a4b32d98c..9d9b0a05d 100644 --- a/src/usr/diag/prdf/common/plat/cen/cen_mba_regs.rule +++ b/src/usr/diag/prdf/common/plat/cen/cen_mba_regs.rule @@ -88,6 +88,52 @@ }; ############################################################################ + # Error Report Registers + ############################################################################ + + register MBA_ERR_REPORT + { + name "MBU.MBA_SRQ.MBA_ERR_REPORTQ"; + scomaddr 0x0301041A; + capture group default; + }; + + register MBA_MCBERRPTQ + { + name "MBU.MBA_MCBIST.SCOMFIR.MBA_MCBERRPTQ"; + scomaddr 0x030106E7; + capture group default; + }; + + register DDRPHY_APB_FIR_ERR0_P0 + { + name "DDRPHY_APB_FIR_ERR0_P0"; + scomaddr 0x8000D0060301143F; + capture group default; + }; + + register DDRPHY_APB_FIR_ERR1_P0 + { + name "DDRPHY_APB_FIR_ERR1_P0"; + scomaddr 0x8000D0070301143F; + capture group default; + }; + + register DDRPHY_APB_FIR_ERR0_P1 + { + name "DDRPHY_APB_FIR_ERR0_P1"; + scomaddr 0x8001D0060301143F; + capture group default; + }; + + register DDRPHY_APB_FIR_ERR1_P1 + { + name "DDRPHY_APB_FIR_ERR1_P1"; + scomaddr 0x8001D0070301143F; + capture group default; + }; + + ############################################################################ # Maintenance Command Registers ############################################################################ diff --git a/src/usr/diag/prdf/common/plat/pegasus/Mba.rule b/src/usr/diag/prdf/common/plat/pegasus/Mba.rule deleted file mode 100755 index c651d8281..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Mba.rule +++ /dev/null @@ -1,729 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Mba.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2018 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -chip cen_mba -{ - name "Centaur MBA chiplet"; - targettype TYPE_MBA; - sigoff 0x9000; - dump DUMP_CONTENT_HW; - scomlen 64; - -.include "prdfCenMbaExtraSig.H"; - - ############################################################################# - # # - # ###### # - # # # ###### #### ### #### ##### ###### ##### #### # - # # # # # # # # # # # # # # - # ###### ##### # # #### # ##### # # #### # - # # # # # ### # # # # ##### # # - # # # # # # # # # # # # # # # # - # # # ###### #### ### #### # ###### # # #### # - # # - ############################################################################# - - ############################################################################ - # Centaur chip MBA target MBACALFIR - ############################################################################ - - register MBACALFIR - { - name "Centaur chip MBA target MBACALFIR"; - scomaddr 0x03010400; - reset (&, 0x03010401); - mask (|, 0x03010405); - capture group FirRegs; - capture group MemChipletRegs; - }; - - register MBACALFIR_MASK - { - name "Centaur chip MBA target MBACALFIR MASK"; - scomaddr 0x03010403; - capture group FirRegs; - capture group MemChipletRegs; - }; - - register MBACALFIR_ACT0 - { - name "Centaur chip MBA target MBACALFIR ACT0"; - scomaddr 0x03010406; - capture group FirRegs; - capture group MemChipletRegs; - capture req nonzero("MBACALFIR"); - }; - - register MBACALFIR_ACT1 - { - name "Centaur chip MBA target MBACALFIR ACT1"; - scomaddr 0x03010407; - capture group FirRegs; - capture group MemChipletRegs; - capture req nonzero("MBACALFIR"); - }; - - ############################################################################ - # Centaur chip MBA target MBASECUREFIR - ############################################################################ - - # This register is hardwired to channel failure (checkstop) and we cannot - # mask or change the state of the action registers. - register MBASECUREFIR - { - name "Centaur chip MBA target MBASECUREFIR"; - scomaddr 0x0301041b; - reset (&, 0x0301041c); - capture group FirRegs; - capture group MemChipletRegs; - }; - - ############################################################################ - # Centaur chip MBA target MBAFIR - ############################################################################ - - register MBAFIR - { - name "Centaur chip MBA target MBAFIR"; - scomaddr 0x03010600; - reset (&, 0x03010601); - mask (|, 0x03010605); - capture group FirRegs; - capture group MemChipletRegs; - }; - - register MBAFIR_MASK - { - name "Centaur chip MBA target MBAFIR MASK"; - scomaddr 0x03010603; - capture group FirRegs; - capture group MemChipletRegs; - }; - - register MBAFIR_ACT0 - { - name "Centaur chip MBA target MBAFIR ACT0"; - scomaddr 0x03010606; - capture group FirRegs; - capture group MemChipletRegs; - capture req nonzero("MBAFIR"); - }; - - register MBAFIR_ACT1 - { - name "Centaur chip MBA target MBAFIR ACT1"; - scomaddr 0x03010607; - capture group FirRegs; - capture group MemChipletRegs; - capture req nonzero("MBAFIR"); - }; - - ############################################################################ - # Centaur chip MBA target MBASPA - ############################################################################ - - register MBASPA - { - name "Centaur chip MBA target MBASPA"; - scomaddr 0x03010611; - reset (&, 0x03010612); - mask (|, 0x03010614); - capture group FirRegs; - capture group MemChipletRegs; - capture group MaintCmdRegs; - }; - - register MBASPA_MASK - { - name "Centaur chip MBA target MBASPA MASK"; - scomaddr 0x03010614; - capture group FirRegs; - capture group MemChipletRegs; - capture group MaintCmdRegs; - }; - - ############################################################################ - # Centaur chip MBA target MBADDRPHYFIR - ############################################################################ - - register MBADDRPHYFIR - { - name "Centaur chip MBA target MBADDRPHYFIR"; - scomaddr 0x800200900301143F; - reset (&, 0x800200910301143F); - mask (|, 0x800200950301143F); - capture group FirRegs; - capture group MemChipletRegs; - }; - - register MBADDRPHYFIR_MASK - { - name "Centaur chip MBA target MBADDRPHYFIR MASK"; - scomaddr 0x800200930301143F; - capture group FirRegs; - capture group MemChipletRegs; - }; - - register MBADDRPHYFIR_ACT0 - { - name "Centaur chip MBA target MBADDRPHYFIR ACT0"; - scomaddr 0x800200960301143F; - capture group FirRegs; - capture group MemChipletRegs; - capture req nonzero("MBADDRPHYFIR"); - }; - - register MBADDRPHYFIR_ACT1 - { - name "Centaur chip MBA target MBADDRPHYFIR ACT1"; - scomaddr 0x800200970301143F; - capture group FirRegs; - capture group MemChipletRegs; - capture req nonzero("MBADDRPHYFIR"); - }; - - ############################################################################ - # Error Report Registers - ############################################################################ - - register MBA_ERR_REPORT - { - name "MBU.MBA_SRQ.MBA_ERR_REPORTQ"; - scomaddr 0x0301041A; - capture group CerrRegs; - capture group MemChipletRegs; - }; - - register MBA_MCBERRPTQ - { - name "MBU.MBA_MCBIST.SCOMFIR.MBA_MCBERRPTQ"; - scomaddr 0x030106E7; - capture group CerrRegs; - capture group MemChipletRegs; - }; - - register DDRPHY_APB_FIR_ERR0_P0 - { - name "DDRPHY_APB_FIR_ERR0_P0"; - scomaddr 0x8000D0060301143F; - capture group CerrRegs; - capture group MemChipletRegs; - }; - - register DDRPHY_APB_FIR_ERR1_P0 - { - name "DDRPHY_APB_FIR_ERR1_P0"; - scomaddr 0x8000D0070301143F; - capture group CerrRegs; - capture group MemChipletRegs; - }; - - register DDRPHY_APB_FIR_ERR0_P1 - { - name "DDRPHY_APB_FIR_ERR0_P1"; - scomaddr 0x8001D0060301143F; - capture group CerrRegs; - capture group MemChipletRegs; - }; - - register DDRPHY_APB_FIR_ERR1_P1 - { - name "DDRPHY_APB_FIR_ERR1_P1"; - scomaddr 0x8001D0070301143F; - capture group CerrRegs; - capture group MemChipletRegs; - }; - -}; - - ############################################################################## - # # - # #### # # - # # # # # # ##### ### # # # ## ##### ### ### # # ### # - # # # # # # # # # # # # # # # # # ## # # # - # #### # # # #### ### # ####### # # # # # # # # ### # - # # # # # # # # # # # # # # # # # # ## # # - # # # ### #### ##### ### # # # ## # ### ### # # ### # - # # - ############################################################################## - -################################################################################ -# Summary for MBA -################################################################################ - -rule rMBA -{ - UNIT_CS: - summary( 0, rMBACALFIR ) | - summary( 1, rMBASECUREFIR ) | - summary( 2, rMBAFIR ) | - summary( 3, rMBADDRPHYFIR ); - - RECOVERABLE: - summary( 0, rMBACALFIR ) | - summary( 1, rMBASECUREFIR ) | - summary( 2, rMBAFIR ) | - summary( 3, rMBADDRPHYFIR ); - - HOST_ATTN: - summary( 4, rMBASPA ); -}; - -group gMBA attntype UNIT_CS, RECOVERABLE, HOST_ATTN filter singlebit -{ - (rMBA, bit(0)) ? analyze(gMBACALFIR); - (rMBA, bit(1)) ? analyze(gMBASECUREFIR); - (rMBA, bit(2)) ? analyze(gMBAFIR); - (rMBA, bit(3)) ? analyze(gMBADDRPHYFIR); - (rMBA, bit(4)) ? analyze(gMBASPA); -}; - -################################################################################ -# Centaur chip MBA target MBACALFIR -################################################################################ - -rule rMBACALFIR -{ - UNIT_CS: - MBACALFIR & ~MBACALFIR_MASK & ~MBACALFIR_ACT0 & ~MBACALFIR_ACT1; - RECOVERABLE: - MBACALFIR & ~MBACALFIR_MASK & ~MBACALFIR_ACT0 & MBACALFIR_ACT1; -}; - -group gMBACALFIR filter singlebit, cs_root_cause( 4, 7 ) -{ - /** MBACALFIR[0] - * MBA_RECOVERABLE_ERROR - */ - (rMBACALFIR, bit(0)) ? self_th_1; - - /** MBACALFIR[1] - * MBA_NONRECOVERABLE_ERROR - */ - (rMBACALFIR, bit(1)) ? self_th_1; - - /** MBACALFIR[2] - * REFRESH_OVERRUN - */ - (rMBACALFIR, bit(2)) ? self_th_32perDay; - - /** MBACALFIR[3] - * WAT_ERROR - */ - (rMBACALFIR, bit(3)) ? defaultMaskedError; - - /** MBACALFIR[4] - * RCD parity error on port 0 - */ - (rMBACALFIR, bit(4)) ? rcd_parity_error_port0_UERE; - - /** MBACALFIR[5] - * DDR0_CAL_TIMEOUT_ERR - */ - (rMBACALFIR, bit(5)) ? self_th_1; - - /** MBACALFIR[6] - * DDR1_CAL_TIMEOUT_ERR - */ - (rMBACALFIR, bit(6)) ? self_th_1; - - /** MBACALFIR[7] - * RCD parity error on port 1 - */ - (rMBACALFIR, bit(7)) ? rcd_parity_error_port1_UERE; - - /** MBACALFIR[8] - * MBX_TO_MBA_PAR_ERROR - */ - (rMBACALFIR, bit(8)) ? self_th_1; - - /** MBACALFIR[9] - * MBA_WRD_UE - */ - (rMBACALFIR, bit(9)) ? self_th_1; - - /** MBACALFIR[10] - * MBA_WRD_CE - */ - (rMBACALFIR, bit(10)) ? threshold_and_mask_self; - - /** MBACALFIR[11] - * MBA_MAINT_UE - */ - (rMBACALFIR, bit(11)) ? self_th_1; - - /** MBACALFIR[12] - * MBA_MAINT_CE - */ - (rMBACALFIR, bit(12)) ? self_th_32perDay; - - /** MBACALFIR[13] - * DDR_CAL_RESET_TIMEOUT - */ - (rMBACALFIR, bit(13)) ? self_th_1; - - /** MBACALFIR[14] - * WRQ_DATA_CE - */ - (rMBACALFIR, bit(14)) ? threshold_and_mask_self; - - /** MBACALFIR[15] - * WRQ_DATA_UE - */ - (rMBACALFIR, bit(15)) ? self_th_1; - - /** MBACALFIR[16] - * WRQ_DATA_SUE - */ - (rMBACALFIR, bit(16)) ? defaultMaskedError; - - /** MBACALFIR[17] - * WRQ_RRQ_HANG_ERR - */ - (rMBACALFIR, bit(17)) ? self_th_1; - - /** MBACALFIR[18] - * SM_1HOT_ERR - */ - (rMBACALFIR, bit(18)) ? self_th_1; - - /** MBACALFIR[19] - * WRD_SCOM_ERROR - */ - (rMBACALFIR, bit(19)) ? threshold_and_mask_self; - - /** MBACALFIR[20] - * RHMR_PRIM_REACHED_MAX - */ - (rMBACALFIR, bit(20)) ? defaultMaskedError; - - /** MBACALFIR[21] - * RHMR_SEC_REACHED_MAX - */ - (rMBACALFIR, bit(21)) ? defaultMaskedError; - - /** MBACALFIR[22] - * RHMR_SEC_ALREADY_FULL - */ - (rMBACALFIR, bit(22)) ? defaultMaskedError; - - /** MBACALFIR[23] - * Reserved - */ - (rMBACALFIR, bit(23)) ? defaultMaskedError; - - /** MBACALFIR[24] - * SCOM FIR error - */ - (rMBACALFIR, bit(24)) ? threshold_and_mask_self; - - /** MBACALFIR[25] - * SCOM FIR error clone - */ - (rMBACALFIR, bit(25)) ? threshold_and_mask_self; - -}; - -################################################################################ -# Centaur chip MBA target MBASECUREFIR -################################################################################ - -rule rMBASECUREFIR -{ - UNIT_CS: - MBASECUREFIR; -}; - -group gMBASECUREFIR filter singlebit, cs_root_cause( 0, 1, 2, 3, 4, 5 ) -{ - /** MBASECUREFIR[0] - * Invalid MBA_CALQ0 access - */ - (rMBASECUREFIR, bit(0)) ? level2_th_1_UERE; - - /** MBASECUREFIR[1] - * Invalid MBA_CALQ1 access - */ - (rMBASECUREFIR, bit(1)) ? level2_th_1_UERE; - - /** MBASECUREFIR[2] - * Invalid MBA_CAL2Q access - */ - (rMBASECUREFIR, bit(2)) ? level2_th_1_UERE; - - /** MBASECUREFIR[3] - * Invalid MBA_CAL3Q access - */ - (rMBASECUREFIR, bit(3)) ? level2_th_1_UERE; - - /** MBASECUREFIR[4] - * Invalid DDR config reg access - */ - (rMBASECUREFIR, bit(4)) ? level2_th_1_UERE; - - /** MBASECUREFIR[5] - * Invalid SIR mask or action reg access - */ - (rMBASECUREFIR, bit(5)) ? level2_th_1_UERE; - -}; - -################################################################################ -# Centaur chip MBA target MBAFIR -################################################################################ - -rule rMBAFIR -{ - UNIT_CS: - MBAFIR & ~MBAFIR_MASK & ~MBAFIR_ACT0 & ~MBAFIR_ACT1; - RECOVERABLE: - MBAFIR & ~MBAFIR_MASK & ~MBAFIR_ACT0 & MBAFIR_ACT1; -}; - -group gMBAFIR filter singlebit, cs_root_cause( 3, 5, 6, 7, 8 ) -{ - /** MBAFIR[0] - * Invalid Maintenance Command - */ - (rMBAFIR, bit(0)) ? defaultMaskedError; - - /** MBAFIR[1] - * Invalid Maintenance Address - */ - (rMBAFIR, bit(1)) ? defaultMaskedError; - - /** MBAFIR[2] - * Multi-address Maintenance Cmd Timeout - */ - (rMBAFIR, bit(2)) ? self_th_1; - - /** MBAFIR[3] - * Internal FSM parity error - */ - (rMBAFIR, bit(3)) ? self_th_1; - - /** MBAFIR[4] - * MCBIST error - */ - (rMBAFIR, bit(4)) ? defaultMaskedError; - - /** MBAFIR[5] - * SCOM command register parity error - */ - (rMBAFIR, bit(5)) ? self_th_1; - - /** MBAFIR[6] - * Unrecoverable channel error - */ - (rMBAFIR, bit(6)) ? self_th_1; - - /** MBAFIR[7] - * UE or CE Error in WRD caw2 data latches - */ - (rMBAFIR, bit(7)) ? self_th_1; - - /** MBAFIR[8] - * Illegal transition maint state machine - */ - (rMBAFIR, bit(8)) ? self_th_1; - - /** MBAFIR[9:14] - * RESERVED - */ - (rMBAFIR, bit(9|10|11|12|13|14)) ? defaultMaskedError; - - /** MBAFIR[15] - * SCOM Internal Error - */ - (rMBAFIR, bit(15)) ? threshold_and_mask_self; - - /** MBAFIR[16] - * SCOM Internal Error Copy - */ - (rMBAFIR, bit(16)) ? threshold_and_mask_self; - -}; - -################################################################################ -# Centaur chip MBA target MBASPA -################################################################################ - -rule rMBASPA -{ - HOST_ATTN: - MBASPA & ~MBASPA_MASK; -}; - -group gMBASPA filter singlebit, cs_root_cause -{ - /** MBASPA[0] - * Maintenance command complete - */ - (rMBASPA, bit(0)) ? maint_cmd_complete; - - /** MBASPA[1] - * Hard NCE ETE - */ - (rMBASPA, bit(1)) ? defaultMaskedError; - - /** MBASPA[2] - * Soft NCE ETE - */ - (rMBASPA, bit(2)) ? defaultMaskedError; - - /** MBASPA[3] - * Intermittent NCE ETE - */ - (rMBASPA, bit(3)) ? defaultMaskedError; - - /** MBASPA[4] - * Retry CE ETE - */ - (rMBASPA, bit(4)) ? defaultMaskedError; - - /** MBASPA[5] - * Emergency throttle action detected - */ - (rMBASPA, bit(5)) ? defaultMaskedError; - - /** MBASPA[6] - * Firmware generated attention 0 - */ - (rMBASPA, bit(6)) ? defaultMaskedError; - - /** MBASPA[7] - * Firmware generated attention 1 - */ - (rMBASPA, bit(7)) ? defaultMaskedError; - - /** MBASPA[8] - * WAT debug attention - */ - (rMBASPA, bit(8)) ? defaultMaskedError; - - /** MBASPA[9] - * Spare - */ - (rMBASPA, bit(9)) ? defaultMaskedError; - - /** MBASPA[10] - * MCBIST done - */ - (rMBASPA, bit(10)) ? defaultMaskedError; - -}; - -################################################################################ -# Centaur chip MBA target MBADDRPHYFIR -################################################################################ - -rule rMBADDRPHYFIR -{ - UNIT_CS: - MBADDRPHYFIR & ~MBADDRPHYFIR_MASK & ~MBADDRPHYFIR_ACT0 & ~MBADDRPHYFIR_ACT1; - RECOVERABLE: - MBADDRPHYFIR & ~MBADDRPHYFIR_MASK & ~MBADDRPHYFIR_ACT0 & MBADDRPHYFIR_ACT1; -}; - -group gMBADDRPHYFIR filter singlebit, cs_root_cause -{ - /** MBADDRPHYFIR[48] - * FSM Error Checkstop - */ - (rMBADDRPHYFIR, bit(48)) ? self_th_1; - - /** MBADDRPHYFIR[49] - * Parity Error Checkstop - */ - (rMBADDRPHYFIR, bit(49)) ? self_th_1; - - /** MBADDRPHYFIR[50] - * Calibration Error RE - */ - (rMBADDRPHYFIR, bit(50)) ? defaultMaskedError; - - /** MBADDRPHYFIR[51] - * FSM Recoverable Error - */ - (rMBADDRPHYFIR, bit(51)) ? self_th_32perDay; - - /** MBADDRPHYFIR[52] - * Parity Recoverable Error - */ - (rMBADDRPHYFIR, bit(52)) ? self_th_32perDay; - - /** MBADDRPHYFIR[53] - * Parity Recoverable Error - */ - (rMBADDRPHYFIR, bit(53)) ? threshold_and_mask_self; - - /** MBADDRPHYFIR[54:55] - * Reserved - */ - (rMBADDRPHYFIR, bit(54|55)) ? defaultMaskedError; - - /** MBADDRPHYFIR[56] - * FSM Error Checkstop - */ - (rMBADDRPHYFIR, bit(56)) ? self_th_1; - - /** MBADDRPHYFIR[57] - * Parity Error Checkstop - */ - (rMBADDRPHYFIR, bit(57)) ? self_th_1; - - /** MBADDRPHYFIR[58] - * Calibration Error RE - */ - (rMBADDRPHYFIR, bit(58)) ? defaultMaskedError; - - /** MBADDRPHYFIR[59] - * FSM Recoverable Error - */ - (rMBADDRPHYFIR, bit(59)) ? self_th_32perDay; - - /** MBADDRPHYFIR[60] - * Parity Recoverable Error - */ - (rMBADDRPHYFIR, bit(60)) ? self_th_32perDay; - -}; - - ############################################################################## - # # - # # ### # - # # # ## ##### ### ### # # # # # # ### ### ### ### # - # # # # # # # # # ## # # # # # # # # # # - # ####### # # # # # # # # # # ##### ### ### ## ### # - # # # # # # # # # # ## # # # # # # # # # # - # # # ## # ### ### # # ### ### # # ### ### ### ### # - # # - ############################################################################## - -# Include the common action set. -.include "cen_common_actions.rule"; -# Include the chip-specific action set. -.include "cen_mba_actions.rule"; - diff --git a/src/usr/diag/prdf/common/plat/pegasus/Mcs.rule b/src/usr/diag/prdf/common/plat/pegasus/Mcs.rule index 3e8cced5f..7897d3e79 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/Mcs.rule +++ b/src/usr/diag/prdf/common/plat/pegasus/Mcs.rule @@ -77,7 +77,6 @@ chip Mcs reset (&, 0x02011841); mask (|, 0x02011845); capture group default; - capture group FirRegs; }; register MCIFIR_AND @@ -93,7 +92,6 @@ chip Mcs name "MC0.MCS0.RIGHT.MCI.SCOMFIR.MCIFIRMASK"; scomaddr 0x02011843; capture group default; - capture group FirRegs; }; register MCIFIR_ACT0 @@ -102,7 +100,6 @@ chip Mcs scomaddr 0x02011846; capture type secondary; capture group default; - capture group FirRegs; capture req nonzero("MCIFIR"); }; @@ -112,7 +109,6 @@ chip Mcs scomaddr 0x02011847; capture type secondary; capture group default; - capture group FirRegs; capture req nonzero("MCIFIR"); }; @@ -122,7 +118,6 @@ chip Mcs scomaddr 0x02011848; capture type secondary; capture group default; - capture group FirRegs; capture req nonzero("MCIFIR"); }; @@ -135,7 +130,6 @@ chip Mcs name "MC0.MCS0.LEFT.LEFT.MCERPT0"; scomaddr 0x0201181E; capture group default; - capture group CerrRegs; }; register MCIERPT0 @@ -143,7 +137,6 @@ chip Mcs name "MC0.MCS0.RIGHT.MCI.MCIERPT0"; scomaddr 0x0201184E; capture group default; - capture group CerrRegs; }; ############################################################################ diff --git a/src/usr/diag/prdf/common/plat/pegasus/Membuf.rule b/src/usr/diag/prdf/common/plat/pegasus/Membuf.rule deleted file mode 100755 index 99280eccc..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Membuf.rule +++ /dev/null @@ -1,2324 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Membuf.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2018 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -chip cen_centaur -{ - name "Centaur chip"; - targettype TYPE_MEMBUF; - sigoff 0x9000; - dump DUMP_CONTENT_HW; - scomlen 64; - -# Include Extra signatures -.include "prdfCenMembufExtraSig.H"; -.include "prdfP8ProcMbCommonExtraSig.H"; - - ############################################################################# - # # - # ###### # - # # # ###### #### ### #### ##### ###### ##### #### # - # # # # # # # # # # # # # # - # ###### ##### # # #### # ##### # # #### # - # # # # # ### # # # # ##### # # - # # # # # # # # # # # # # # # # - # # # ###### #### ### #### # ###### # # #### # - # # - ############################################################################# - - ############################################################################ - # Global Attention FIR - ############################################################################ - - register GLOBAL_CS_FIR - { - name "Global Checkstop Attention FIR"; - scomaddr 0x500F001C; - capture group default; - }; - - register GLOBAL_RE_FIR - { - name "Global Recoverable Attention FIR"; - scomaddr 0x500F001B; - capture group default; - }; - - ############################################################################ - # Global Special Attention FIR - ############################################################################ - - register GLOBAL_SPA_FIR - { - name "Global Special Attention FIR"; - scomaddr 0x500F001A; - capture group default; - }; - - ############################################################################ - # TP Chiplet FIR - ############################################################################ - - register TP_CHIPLET_CS_FIR - { - name "TP Chiplet Checkstop FIR"; - scomaddr 0x01040000; - capture group default; - capture group FirRegs; - }; - - register TP_CHIPLET_RE_FIR - { - name "TP Chiplet Recoverable FIR"; - scomaddr 0x01040001; - capture group default; - capture group FirRegs; - }; - - register TP_CHIPLET_FIR_MASK - { - name "TP Chiplet FIR MASK"; - scomaddr 0x01040002; - capture group default; - capture group FirRegs; - }; - - ############################################################################ - # Centaur chip TP_LFIR - ############################################################################ - - register TP_LFIR - { - name "Centaur chip TP_LFIR"; - scomaddr 0x0104000A; - reset (&, 0x0104000B); - mask (|, 0x0104000F); - capture group default; - capture group FirRegs; - }; - - register TP_LFIR_MASK - { - name "Centaur chip TP_LFIR MASK"; - scomaddr 0x0104000D; - capture group default; - capture group FirRegs; - }; - - register TP_LFIR_ACT0 - { - name "Centaur chip TP_LFIR ACT0"; - scomaddr 0x01040010; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("TP_LFIR"); - }; - - register TP_LFIR_ACT1 - { - name "Centaur chip TP_LFIR ACT1"; - scomaddr 0x01040011; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("TP_LFIR"); - }; - - ############################################################################ - # NEST Chiplet FIR - ############################################################################ - - register NEST_CHIPLET_CS_FIR - { - name "NEST Chiplet Checkstop FIR"; - scomaddr 0x02040000; - capture group default; - capture group FirRegs; - }; - - register NEST_CHIPLET_RE_FIR - { - name "NEST Chiplet Recoverable FIR"; - scomaddr 0x02040001; - capture group default; - capture group FirRegs; - }; - - register NEST_CHIPLET_FIR_MASK - { - name "NEST Chiplet FIR MASK"; - scomaddr 0x02040002; - capture group default; - capture group FirRegs; - }; - - ############################################################################ - # Centaur chip NEST_LFIR - ############################################################################ - - register NEST_LFIR - { - name "Centaur chip NEST_LFIR"; - scomaddr 0x0204000A; - reset (&, 0x0204000B); - mask (|, 0x0204000F); - capture group default; - capture group FirRegs; - }; - - register NEST_LFIR_MASK - { - name "Centaur chip NEST_LFIR MASK"; - scomaddr 0x0204000D; - capture group default; - capture group FirRegs; - }; - - register NEST_LFIR_ACT0 - { - name "Centaur chip NEST_LFIR ACT0"; - scomaddr 0x02040010; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("NEST_LFIR"); - }; - - register NEST_LFIR_ACT1 - { - name "Centaur chip NEST_LFIR ACT1"; - scomaddr 0x02040011; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("NEST_LFIR"); - }; - - ############################################################################ - # Centaur chip DMIFIR - ############################################################################ - - register DMIFIR - { - name "Centaur chip DMIFIR"; - scomaddr 0x02010400; - reset (&, 0x02010401); - mask (|, 0x02010405); - capture group default; - capture group FirRegs; - }; - - register DMIFIR_MASK - { - name "Centaur chip DMIFIR MASK"; - scomaddr 0x02010403; - capture group default; - capture group FirRegs; - }; - - register DMIFIR_ACT0 - { - name "Centaur chip DMIFIR ACT0"; - scomaddr 0x02010406; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("DMIFIR"); - }; - - register DMIFIR_ACT1 - { - name "Centaur chip DMIFIR ACT1"; - scomaddr 0x02010407; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("DMIFIR"); - }; - - ############################################################################ - # Centaur chip MBIFIR - ############################################################################ - - register MBIFIR - { - name "Centaur chip MBIFIR"; - scomaddr 0x02010800; - reset (&, 0x02010801); - mask (|, 0x02010805); - capture group default; - capture group FirRegs; - }; - - register MBIFIR_MASK - { - name "Centaur chip MBIFIR MASK"; - scomaddr 0x02010803; - capture group default; - capture group FirRegs; - }; - - register MBIFIR_ACT0 - { - name "Centaur chip MBIFIR ACT0"; - scomaddr 0x02010806; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("MBIFIR"); - }; - - register MBIFIR_ACT1 - { - name "Centaur chip MBIFIR ACT1"; - scomaddr 0x02010807; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("MBIFIR"); - }; - - ############################################################################ - # Centaur chip MBSFIR - ############################################################################ - - register MBSFIR - { - name "Centaur chip MBSFIR"; - scomaddr 0x02011400; - reset (&, 0x02011401); - mask (|, 0x02011405); - capture group default; - capture group FirRegs; - }; - - register MBSFIR_MASK - { - name "Centaur chip MBSFIR MASK"; - scomaddr 0x02011403; - capture group default; - capture group FirRegs; - }; - - register MBSFIR_ACT0 - { - name "Centaur chip MBSFIR ACT0"; - scomaddr 0x02011406; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("MBSFIR"); - }; - - register MBSFIR_ACT1 - { - name "Centaur chip MBSFIR ACT1"; - scomaddr 0x02011407; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("MBSFIR"); - }; - - ############################################################################ - # Centaur chip MBSSECUREFIR - ############################################################################ - - # This register is hardwired to channel failure (checkstop) and we cannot - # mask or change the state of the action registers. - register MBSSECUREFIR - { - name "Centaur chip MBSSECUREFIR"; - scomaddr 0x0201141e; - reset (&, 0x0201141f); - capture group default; - capture group FirRegs; - }; - - ############################################################################ - # Centaur chip MBSECCFIR 0 - ############################################################################ - - register MBSECCFIR_0 - { - name "Centaur chip MBSECCFIR 0"; - scomaddr 0x02011440; - reset (&, 0x02011441); - mask (|, 0x02011445); - capture group default; - capture group FirRegs; - capture group MaintCmdRegs_mba0; - }; - - register MBSECCFIR_0_MASK - { - name "Centaur chip MBSECCFIR 0 MASK"; - scomaddr 0x02011443; - capture group default; - capture group FirRegs; - capture group MaintCmdRegs_mba0; - }; - - register MBSECCFIR_0_ACT0 - { - name "Centaur chip MBSECCFIR 0 ACT0"; - scomaddr 0x02011446; - capture type secondary; - capture group default; - capture group FirRegs; - capture group MaintCmdRegs_mba0; - capture req nonzero("MBSECCFIR_0"); - }; - - register MBSECCFIR_0_ACT1 - { - name "Centaur chip MBSECCFIR 0 ACT1"; - scomaddr 0x02011447; - capture type secondary; - capture group default; - capture group FirRegs; - capture group MaintCmdRegs_mba0; - capture req nonzero("MBSECCFIR_0"); - }; - - ############################################################################ - # Centaur chip MBSECCFIR 1 - ############################################################################ - - register MBSECCFIR_1 - { - name "Centaur chip MBSECCFIR 1"; - scomaddr 0x02011480; - reset (&, 0x02011481); - mask (|, 0x02011485); - capture group default; - capture group FirRegs; - capture group MaintCmdRegs_mba1; - }; - - register MBSECCFIR_1_MASK - { - name "Centaur chip MBSECCFIR 1 MASK"; - scomaddr 0x02011483; - capture group default; - capture group FirRegs; - capture group MaintCmdRegs_mba1; - }; - - register MBSECCFIR_1_ACT0 - { - name "Centaur chip MBSECCFIR 1 ACT0"; - scomaddr 0x02011486; - capture type secondary; - capture group default; - capture group FirRegs; - capture group MaintCmdRegs_mba1; - capture req nonzero("MBSECCFIR_1"); - }; - - register MBSECCFIR_1_ACT1 - { - name "Centaur chip MBSECCFIR 1 ACT1"; - scomaddr 0x02011487; - capture type secondary; - capture group default; - capture group FirRegs; - capture group MaintCmdRegs_mba1; - capture req nonzero("MBSECCFIR_1"); - }; - - ############################################################################ - # Centaur chip SCACFIR - ############################################################################ - - register SCACFIR - { - name "Centaur chip SCACFIR"; - scomaddr 0x020115c0; - reset (&, 0x020115c1); - mask (|, 0x020115c5); - capture group default; - capture group FirRegs; - }; - - register SCACFIR_MASK - { - name "Centaur chip SCACFIR MASK"; - scomaddr 0x020115c3; - capture group default; - capture group FirRegs; - }; - - register SCACFIR_ACT0 - { - name "Centaur chip SCACFIR ACT0"; - scomaddr 0x020115c6; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("SCACFIR"); - }; - - register SCACFIR_ACT1 - { - name "Centaur chip SCACFIR ACT1"; - scomaddr 0x020115c7; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("SCACFIR"); - }; - - ############################################################################ - # Centaur chip MCBISTFIR 0 - ############################################################################ - - register MCBISTFIR_0 - { - name "Centaur chip MCBISTFIR 0"; - scomaddr 0x02011600; - reset (&, 0x02011601); - mask (|, 0x02011605); - capture group default; - capture group FirRegs; - }; - - register MCBISTFIR_0_MASK - { - name "Centaur chip MCBISTFIR 0 MASK"; - scomaddr 0x02011603; - capture group default; - capture group FirRegs; - }; - - register MCBISTFIR_0_ACT0 - { - name "Centaur chip MCBISTFIR 0 ACT0"; - scomaddr 0x02011606; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("MCBISTFIR_0"); - }; - - register MCBISTFIR_0_ACT1 - { - name "Centaur chip MCBISTFIR 0 ACT1"; - scomaddr 0x02011607; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("MCBISTFIR_0"); - }; - - ############################################################################ - # Centaur chip MCBISTFIR 1 - ############################################################################ - - register MCBISTFIR_1 - { - name "Centaur chip MCBISTFIR 1"; - scomaddr 0x02011700; - reset (&, 0x02011701); - mask (|, 0x02011705); - capture group default; - capture group FirRegs; - }; - - register MCBISTFIR_1_MASK - { - name "Centaur chip MCBISTFIR 1 MASK"; - scomaddr 0x02011703; - capture group default; - capture group FirRegs; - }; - - register MCBISTFIR_1_ACT0 - { - name "Centaur chip MCBISTFIR 1 ACT0"; - scomaddr 0x02011706; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("MCBISTFIR_1"); - }; - - register MCBISTFIR_1_ACT1 - { - name "Centaur chip MCBISTFIR 1 ACT1"; - scomaddr 0x02011707; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("MCBISTFIR_1"); - }; - - ############################################################################ - # MEM Chiplet FIR - ############################################################################ - - register MEM_CHIPLET_CS_FIR - { - name "MEM Chiplet Checkstop FIR"; - scomaddr 0x03040000; - capture group FirRegs; - capture group MemChipletRegs; - }; - - register MEM_CHIPLET_RE_FIR - { - name "MEM Chiplet Recoverable FIR"; - scomaddr 0x03040001; - capture group FirRegs; - capture group MemChipletRegs; - }; - - register MEM_CHIPLET_FIR_MASK - { - name "MEM Chiplet FIR MASK"; - scomaddr 0x03040002; - capture group FirRegs; - capture group MemChipletRegs; - }; - - ############################################################################ - # MEM Chiplet Special Attention FIR - ############################################################################ - - register MEM_CHIPLET_SPA_FIR - { - name "MEM Chiplet Special Attention FIR"; - scomaddr 0x03040004; - capture group FirRegs; - capture group MemChipletRegs; - }; - - register MEM_CHIPLET_SPA_FIR_MASK - { - name "MEM Chiplet Special Attention FIR MASK"; - scomaddr 0x03040007; - capture group FirRegs; - capture group MemChipletRegs; - }; - - ############################################################################ - # Centaur chip MEM_LFIR - ############################################################################ - - register MEM_LFIR - { - name "Centaur chip MEM_LFIR"; - scomaddr 0x0304000A; - reset (&, 0x0304000B); - mask (|, 0x0304000F); - capture group FirRegs; - capture group MemChipletRegs; - }; - - register MEM_LFIR_MASK - { - name "Centaur chip MEM_LFIR MASK"; - scomaddr 0x0304000D; - capture group FirRegs; - capture group MemChipletRegs; - }; - - register MEM_LFIR_ACT0 - { - name "Centaur chip MEM_LFIR ACT0"; - scomaddr 0x03040010; - capture type secondary; - capture group FirRegs; - capture group MemChipletRegs; - capture req nonzero("MEM_LFIR"); - }; - - register MEM_LFIR_ACT1 - { - name "Centaur chip MEM_LFIR ACT1"; - scomaddr 0x03040011; - capture type secondary; - capture group FirRegs; - capture group MemChipletRegs; - capture req nonzero("MEM_LFIR"); - }; - -# Import all of the chiplet registers -.include "Membuf_regs_TP.rule" -.include "Membuf_regs_NEST.rule" -.include "Membuf_regs_MEM.rule" - -}; - - ############################################################################## - # # - # #### # # - # # # # # # ##### ### # # # ## ##### ### ### # # ### # - # # # # # # # # # # # # # # # # # ## # # # - # #### # # # #### ### # ####### # # # # # # # # ### # - # # # # # # # # # # # # # # # # # # ## # # - # # # ### #### ##### ### # # # ## # ### ### # # ### # - # # - ############################################################################## - -################################################################################ -# Global Attention FIR -################################################################################ - -rule rGLOBAL_FIR -{ - UNIT_CS: - GLOBAL_CS_FIR; - RECOVERABLE: - GLOBAL_RE_FIR; -}; - -group gGLOBAL_FIR attntype UNIT_CS, RECOVERABLE filter singlebit -{ - /** GLOBAL_FIR[1] - * Attention from TP chiplet - */ - (rGLOBAL_FIR, bit(1)) ? analyze(gTP_CHIPLET_FIR); - - /** GLOBAL_FIR[2] - * Attention from NEST chiplet - */ - (rGLOBAL_FIR, bit(2)) ? analyze(gNEST_CHIPLET_FIR); - - /** GLOBAL_FIR[3] - * Attention from MEM chiplet - */ - (rGLOBAL_FIR, bit(3)) ? analyze(gMEM_CHIPLET_FIR); - -}; - -################################################################################ -# Global Special Attention FIR -################################################################################ - -rule rGLOBAL_SPA_FIR -{ - HOST_ATTN: - GLOBAL_SPA_FIR; -}; - -group gGLOBAL_SPA_FIR attntype HOST_ATTN filter singlebit -{ - /** GLOBAL_SPA_FIR[3] - * Attention from MEM chiplet - */ - (rGLOBAL_SPA_FIR, bit(3)) ? analyze(gMEM_CHIPLET_SPA_FIR); - -}; - -################################################################################ -# TP Chiplet FIR -################################################################################ - -rule rTP_CHIPLET_FIR -{ - UNIT_CS: - TP_CHIPLET_CS_FIR & ~TP_CHIPLET_FIR_MASK & `1fffffffffffffff`; - RECOVERABLE: - (TP_CHIPLET_RE_FIR >> 2) & ~TP_CHIPLET_FIR_MASK & `1fffffffffffffff`; -}; - -group gTP_CHIPLET_FIR filter singlebit -{ - /** TP_CHIPLET_FIR[3] - * Attention from TP_LFIR - */ - (rTP_CHIPLET_FIR, bit(3)) ? analyze(gTP_LFIR); - -}; - -################################################################################ -# Centaur chip TP_LFIR -################################################################################ - -rule rTP_LFIR -{ - UNIT_CS: - TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 & ~TP_LFIR_ACT1; - RECOVERABLE: - TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 & TP_LFIR_ACT1; -}; - -group gTP_LFIR filter singlebit, cs_root_cause( 19, 20 ) -{ - /** TP_LFIR[0] - * CFIR internal parity error - */ - (rTP_LFIR, bit(0)) ? threshold_and_mask_self; - - /** TP_LFIR[1] - * GPIO (PCB error) - */ - (rTP_LFIR, bit(1)) ? defaultMaskedError; - - /** TP_LFIR[2] - * CC (PCB error) - */ - (rTP_LFIR, bit(2)) ? defaultMaskedError; - - /** TP_LFIR[3] - * CC (OPCG, parity, scan collision, ...) - */ - (rTP_LFIR, bit(3)) ? defaultMaskedError; - - /** TP_LFIR[4] - * PSC (PCB error) - */ - (rTP_LFIR, bit(4)) ? defaultMaskedError; - - /** TP_LFIR[5] - * PSC (parity error) - */ - (rTP_LFIR, bit(5)) ? defaultMaskedError; - - /** TP_LFIR[6] - * Thermal (parity error) - */ - (rTP_LFIR, bit(6)) ? defaultMaskedError; - - /** TP_LFIR[7] - * Thermal (PCB error) - */ - (rTP_LFIR, bit(7)) ? defaultMaskedError; - - /** TP_LFIR[8] - * Thermal (critical trip error) - */ - (rTP_LFIR, bit(8)) ? defaultMaskedError; - - /** TP_LFIR[9] - * Thermal (fatal trip error) - */ - (rTP_LFIR, bit(9)) ? defaultMaskedError; - - /** TP_LFIR[10] - * Thermal (voltage trip error) - */ - (rTP_LFIR, bit(10)) ? defaultMaskedError; - - /** TP_LFIR[11] - * Trace Array ( error) - */ - (rTP_LFIR, bit(11)) ? defaultMaskedError; - - /** TP_LFIR[12] - * Trace Array ( error) - */ - (rTP_LFIR, bit(12)) ? defaultMaskedError; - - /** TP_LFIR[13:14] - * ITR - */ - (rTP_LFIR, bit(13|14)) ? threshold_and_mask_self; - - /** TP_LFIR[15] - * ITR (itr_tc_pcbsl_slave_fir_err) - */ - (rTP_LFIR, bit(15)) ? defaultMaskedError; - - /** TP_LFIR[16:18] - * PIB - */ - (rTP_LFIR, bit(16|17|18)) ? defaultMaskedError; - - /** TP_LFIR[19] - * NEST PLL unlock - */ - (rTP_LFIR, bit(19)) ? pll_unlock_UERE; - - /** TP_LFIR[20] - * MEM PLL unlock - */ - (rTP_LFIR, bit(20)) ? pll_unlock_UERE; - - /** TP_LFIR[21:39] - * Reserved - */ - (rTP_LFIR, bit(21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? defaultMaskedError; - - /** TP_LFIR[40] - * malfunction alert (local xstop in another chiplet) - */ - (rTP_LFIR, bit(40)) ? defaultMaskedError; - -}; - -################################################################################ -# NEST Chiplet FIR -################################################################################ - -rule rNEST_CHIPLET_FIR -{ - UNIT_CS: - NEST_CHIPLET_CS_FIR & ~NEST_CHIPLET_FIR_MASK & `1fffffffffffffff`; - RECOVERABLE: - (NEST_CHIPLET_RE_FIR >> 2) & ~NEST_CHIPLET_FIR_MASK & `1fffffffffffffff`; -}; - -group gNEST_CHIPLET_FIR filter priority( 3, 6, 5, 7 ) -{ - # NOTE: The MBIFIR must be analyzed before the DMIFIR and both the MBIFIR - # and DMIFIR must be analyzed before the MBSFIR. All other FIRs will be - # analyzed in order. - - /** NEST_CHIPLET_FIR[3] - * Attention from NEST_LFIR - */ - (rNEST_CHIPLET_FIR, bit(3)) ? analyze(gNEST_LFIR); - - /** NEST_CHIPLET_FIR[5] - * Attention from DMIFIR - */ - (rNEST_CHIPLET_FIR, bit(5)) ? analyze(gDMIFIR); - - /** NEST_CHIPLET_FIR[6] - * Attention from MBIFIR - */ - (rNEST_CHIPLET_FIR, bit(6)) ? analyze(gMBIFIR); - - /** NEST_CHIPLET_FIR[7] - * Attention from MBSFIR - */ - (rNEST_CHIPLET_FIR, bit(7)) ? analyze(gMBSFIR); - - /** NEST_CHIPLET_FIR[8] - * Attention from MCBISTFIR - */ - (rNEST_CHIPLET_FIR, bit(8)) ? analyze(gMCBISTFIR_0); - - /** NEST_CHIPLET_FIR[9] - * Attention from MCBISTFIR - */ - (rNEST_CHIPLET_FIR, bit(9)) ? analyze(gMCBISTFIR_1); - - /** NEST_CHIPLET_FIR[10] - * Attention from MBSECCFIR - */ - (rNEST_CHIPLET_FIR, bit(10)) ? analyze(gMBSECCFIR_0); - - /** NEST_CHIPLET_FIR[11] - * Attention from MBSECCFIR - */ - (rNEST_CHIPLET_FIR, bit(11)) ? analyze(gMBSECCFIR_1); - - /** NEST_CHIPLET_FIR[13] - * Attention from SCACFIR - */ - (rNEST_CHIPLET_FIR, bit(13)) ? analyze(gSCACFIR); - - /** NEST_CHIPLET_FIR[14] - * Attention from MBSSECUREFIR - */ - (rNEST_CHIPLET_FIR, bit(14)) ? analyze(gMBSSECUREFIR); - -}; - -################################################################################ -# Centaur chip NEST_LFIR -################################################################################ - -rule rNEST_LFIR -{ - UNIT_CS: - NEST_LFIR & ~NEST_LFIR_MASK & ~NEST_LFIR_ACT0 & ~NEST_LFIR_ACT1; - RECOVERABLE: - NEST_LFIR & ~NEST_LFIR_MASK & ~NEST_LFIR_ACT0 & NEST_LFIR_ACT1; -}; - -group gNEST_LFIR filter singlebit, cs_root_cause -{ - /** NEST_LFIR[0] - * CFIR internal parity error - */ - (rNEST_LFIR, bit(0)) ? threshold_and_mask_self; - - /** NEST_LFIR[1] - * GPIO (PCB error) - */ - (rNEST_LFIR, bit(1)) ? defaultMaskedError; - - /** NEST_LFIR[2] - * CC (PCB error) - */ - (rNEST_LFIR, bit(2)) ? defaultMaskedError; - - /** NEST_LFIR[3] - * CC (OPCG, parity, scan collision, ...) - */ - (rNEST_LFIR, bit(3)) ? defaultMaskedError; - - /** NEST_LFIR[4] - * PSC (PCB error) - */ - (rNEST_LFIR, bit(4)) ? defaultMaskedError; - - /** NEST_LFIR[5] - * PSC (parity error) - */ - (rNEST_LFIR, bit(5)) ? defaultMaskedError; - - /** NEST_LFIR[6] - * Thermal (parity error) - */ - (rNEST_LFIR, bit(6)) ? defaultMaskedError; - - /** NEST_LFIR[7] - * Thermal (PCB error) - */ - (rNEST_LFIR, bit(7)) ? defaultMaskedError; - - /** NEST_LFIR[8] - * Thermal (critical trip error) - */ - (rNEST_LFIR, bit(8)) ? defaultMaskedError; - - /** NEST_LFIR[9] - * Thermal (fatal trip error) - */ - (rNEST_LFIR, bit(9)) ? defaultMaskedError; - - /** NEST_LFIR[10] - * Thermal (voltage trip error) - */ - (rNEST_LFIR, bit(10)) ? defaultMaskedError; - - /** NEST_LFIR[11] - * Trace Array ( error) - */ - (rNEST_LFIR, bit(11)) ? defaultMaskedError; - - /** NEST_LFIR[12] - * Trace Array ( error) - */ - (rNEST_LFIR, bit(12)) ? defaultMaskedError; - - /** NEST_LFIR[13:39] - * Reserved - */ - (rNEST_LFIR, bit(13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? defaultMaskedError; - - /** NEST_LFIR[40] - * malfunction alert (local xstop in another chiplet) - */ - (rNEST_LFIR, bit(40)) ? defaultMaskedError; - -}; - -################################################################################ -# Centaur chip DMIFIR -################################################################################ - -rule rDMIFIR -{ - UNIT_CS: - DMIFIR & ~DMIFIR_MASK & ~DMIFIR_ACT0 & ~DMIFIR_ACT1; - RECOVERABLE: - DMIFIR & ~DMIFIR_MASK & ~DMIFIR_ACT0 & DMIFIR_ACT1; -}; - -group gDMIFIR filter priority( 10, 2, 11, 12, 9 ), - cs_root_cause( 10 ) -{ - /** DMIFIR[0] - * RX invalid state or parity error - */ - (rDMIFIR, bit(0)) ? defaultMaskedError; - - /** DMIFIR[1] - * TX invalid state or parity error - */ - (rDMIFIR, bit(1)) ? defaultMaskedError; - - /** DMIFIR[2] - * GCR hang error - */ - (rDMIFIR, bit(2)) ? self_th_1; - - /** DMIFIR[3:7] - * Reserved - */ - (rDMIFIR, bit(3|4|5|6|7)) ? defaultMaskedError; - - /** DMIFIR[8] - * Training error - */ - (rDMIFIR, bit(8)) ? defaultMaskedError; - - /** DMIFIR[9] - * Spare lane deployed - */ - (rDMIFIR, bit(9)) ? spareDeployed_dmibus; - - /** DMIFIR[10] - * Max spares exceeded - */ - (rDMIFIR, bit(10)) ? maxSparesExceeded_dmibus_UERE; - - /** DMIFIR[11] - * Recal or dynamic repair error - */ - (rDMIFIR, bit(11)) ? calloutBusInterface_dmibus_th1; - - /** DMIFIR[12] - * Too many bus errors - */ - (rDMIFIR, bit(12)) ? tooManyBusErrors_dmibus; - - /** DMIFIR[13:15] - * Reserved - */ - (rDMIFIR, bit(13|14|15)) ? defaultMaskedError; - - /** DMIFIR[16:23] - * Bus 1 - unused - */ - (rDMIFIR, bit(16|17|18|19|20|21|22|23)) ? defaultMaskedError; - - /** DMIFIR[24:31] - * Bus 2 - unused - */ - (rDMIFIR, bit(24|25|26|27|28|29|30|31)) ? defaultMaskedError; - - /** DMIFIR[32:39] - * Bus 3 - unused - */ - (rDMIFIR, bit(32|33|34|35|36|37|38|39)) ? defaultMaskedError; - - /** DMIFIR[40:47] - * Bus 4 - unused - */ - (rDMIFIR, bit(40|41|42|43|44|45|46|47)) ? defaultMaskedError; - - /** DMIFIR[48] - * scom error - */ - (rDMIFIR, bit(48)) ? threshold_and_mask_self; - - /** DMIFIR[49] - * scom error - */ - (rDMIFIR, bit(49)) ? threshold_and_mask_self; - -}; - -################################################################################ -# Centaur chip MBIFIR -################################################################################ - -rule rMBIFIR -{ - UNIT_CS: - MBIFIR & ~MBIFIR_MASK & ~MBIFIR_ACT0 & ~MBIFIR_ACT1; - RECOVERABLE: - MBIFIR & ~MBIFIR_MASK & ~MBIFIR_ACT0 & MBIFIR_ACT1; -}; - -group gMBIFIR filter priority( 8, 9, 19, 20, 6, 0, 16, 5, 10 ), - cs_root_cause( 0, 6, 8, 9, 19, 20 ) -{ - /** MBIFIR[0] - * Replay Timeout - */ - (rMBIFIR, bit(0)) ? replay_timeout_UERE; - - /** MBIFIR[1] - * Channel Fail - */ - (rMBIFIR, bit(1)) ? defaultMaskedError; - - /** MBIFIR[2] - * CRC Error - */ - (rMBIFIR, bit(2)) ? defaultMaskedError; - - /** MBIFIR[3] - * Frame NoAck - */ - (rMBIFIR, bit(3)) ? defaultMaskedError; - - /** MBIFIR[4] - * Seqid Out of Order - */ - (rMBIFIR, bit(4)) ? defaultMaskedError; - - /** MBIFIR[5] - * Replay Buffer ECC CE - */ - (rMBIFIR, bit(5)) ? self_th_5perHour; - - /** MBIFIR[6] - * Replay Buffer ECC UE - */ - (rMBIFIR, bit(6)) ? self_th_1_UERE; - - /** MBIFIR[7] - * MBI State Machine Timeout - */ - (rMBIFIR, bit(7)) ? defaultMaskedError; - - /** MBIFIR[8] - * MBI Internal Control Parity Error - */ - (rMBIFIR, bit(8)) ? self_th_1_UERE; - - /** MBIFIR[9] - * MBI Data Flow Parity Error - */ - (rMBIFIR, bit(9)) ? self_th_1_UERE; - - /** MBIFIR[10] - * CRC Performance Degradation - */ - (rMBIFIR, bit(10)) ? defaultMaskedError; - - /** MBIFIR[11] - * Global Host MC Checkstop - */ - (rMBIFIR, bit(11)) ? defaultMaskedError; - - /** MBIFIR[12] - * Host MC Tracestop - */ - (rMBIFIR, bit(12)) ? defaultMaskedError; - - /** MBIFIR[13] - * Channel Interlock Fail - */ - (rMBIFIR, bit(13)) ? defaultMaskedError; - - /** MBIFIR[14] - * Host MC Local Checkstop - */ - (rMBIFIR, bit(14)) ? defaultMaskedError; - - /** MBIFIR[15] - * FRTL Counter Overflow - */ - (rMBIFIR, bit(15)) ? defaultMaskedError; - - /** MBIFIR[16] - * SCOM Register parity error - */ - (rMBIFIR, bit(16)) ? self_th_1; - - /** MBIFIR[17] - * IO Fault - */ - (rMBIFIR, bit(17)) ? defaultMaskedError; - - /** MBIFIR[18] - * Multiple Replay - */ - (rMBIFIR, bit(18)) ? defaultMaskedError; - - /** MBIFIR[19] - * MBICFG parity error - */ - (rMBIFIR, bit(19)) ? self_th_1_UERE; - - /** MBIFIR[20] - * Replay Buffer Overrun - */ - (rMBIFIR, bit(20)) ? calloutBusInterface_dmibus_th1_UERE; - - /** MBIFIR[21] - * WAT error - */ - (rMBIFIR, bit(21)) ? defaultMaskedError; - - /** MBIFIR[22:24] - * Reserved - */ - (rMBIFIR, bit(22|23|24)) ? defaultMaskedError; - - /** MBIFIR[25] - * internal scom error - */ - (rMBIFIR, bit(25)) ? threshold_and_mask_self; - - /** MBIFIR[26] - * internal scom error clone - */ - (rMBIFIR, bit(26)) ? threshold_and_mask_self; - -}; - -################################################################################ -# Centaur chip MBSFIR -################################################################################ - -rule rMBSFIR -{ - UNIT_CS: - MBSFIR & ~MBSFIR_MASK & ~MBSFIR_ACT0 & ~MBSFIR_ACT1; - RECOVERABLE: - MBSFIR & ~MBSFIR_MASK & ~MBSFIR_ACT0 & MBSFIR_ACT1; -}; - -group gMBSFIR filter singlebit, cs_root_cause( 0, 1, 2, 4, 6, 8, 10, 13, 16, 18, 20, 27, 30 ) -{ - /** MBSFIR[0] - * HOST_PROTOCOL_ERROR - */ - (rMBSFIR, bit(0)) ? calloutBusInterface_dmibus_th1_UERE; - - /** MBSFIR[1] - * INT_PROTOCOL_ERROR - */ - (rMBSFIR, bit(1)) ? self_th_1_UERE; - - /** MBSFIR[2] - * INVALID_ADDRESS_ERROR - */ - (rMBSFIR, bit(2)) ? calloutBusInterface_dmibus_th1; - - /** MBSFIR[3] - * EXTERNAL_TIMEOUT - */ - (rMBSFIR, bit(3)) ? level2_th_1; - - /** MBSFIR[4] - * INTERNAL_TIMEOUT - */ - (rMBSFIR, bit(4)) ? mbs_internal_timeout; - - /** MBSFIR[3,4] - * EXTERNAL_TIMEOUT - */ - (rMBSFIR, bit(3,4)) ? mbs_int_ext_timeout; - - /** MBSFIR[5] - * INT_BUFFER_CE - */ - (rMBSFIR, bit(5)) ? self_th_32perDay; - - /** MBSFIR[6] - * INT_BUFFER_UE - */ - (rMBSFIR, bit(6)) ? self_th_1_UERE; - - /** MBSFIR[7] - * INT_BUFFER_SUE - */ - (rMBSFIR, bit(7)) ? defaultMaskedError; - - /** MBSFIR[8] - * INT_PARITY_ERROR - */ - (rMBSFIR, bit(8)) ? self_th_1_UERE; - - /** MBSFIR[9] - * CACHE_SRW_CE - */ - (rMBSFIR, bit(9)) ? l4_cache_srw_ce; - - /** MBSFIR[10] - * CACHE_SRW_UE - */ - (rMBSFIR, bit(10)) ? l4_cache_srw_ue_UERE; - - /** MBSFIR[11] - * CACHE_SRW_SUE - */ - (rMBSFIR, bit(11)) ? defaultMaskedError; - - /** MBSFIR[12] - * CACHE_CO_CE - */ - (rMBSFIR, bit(12)) ? l4_cache_co_ce; - - /** MBSFIR[13] - * CACHE_CO_UE - */ - (rMBSFIR, bit(13)) ? l4_cache_co_ue_UERE; - - /** MBSFIR[14] - * CACHE_CO_SUE - */ - (rMBSFIR, bit(14)) ? defaultMaskedError; - - /** MBSFIR[15] - * DIR_CE - */ - (rMBSFIR, bit(15)) ? l4_th_32perDay; - - /** MBSFIR[16] - * DIR_UE - */ - (rMBSFIR, bit(16)) ? l4_th_1_UERE; - - /** MBSFIR[17] - * DIR_MEMBER_DELETED - */ - (rMBSFIR, bit(17)) ? defaultMaskedError; - - /** MBSFIR[18] - * DIR_ALL_MEMBERS_DELETED - */ - (rMBSFIR, bit(18)) ? l4_th_1_UERE; - - /** MBSFIR[19] - * LRU_ERROR - */ - (rMBSFIR, bit(19)) ? l4_th_32perDay; - - /** MBSFIR[20] - * EDRAM ERROR - */ - (rMBSFIR, bit(20)) ? l4_th_1_UERE; - - /** MBSFIR[21] - * EMERGENCY_THROTTLE_SET - */ - (rMBSFIR, bit(21)) ? defaultMaskedError; - - /** MBSFIR[22] - * HOST_INBAND_READ_ERROR - */ - (rMBSFIR, bit(22)) ? defaultMaskedError; - - /** MBSFIR[23] - * HOST_INBAND_WRITE_ERROR - */ - (rMBSFIR, bit(23)) ? defaultMaskedError; - - /** MBSFIR[24] - * OCC_INBAND_READ_ERROR - */ - (rMBSFIR, bit(24)) ? defaultMaskedError; - - /** MBSFIR[25] - * OCC_INBAND_WRITE_ERROR - */ - (rMBSFIR, bit(25)) ? defaultMaskedError; - - /** MBSFIR[26] - * SRB_BUFFER_CE - */ - (rMBSFIR, bit(26)) ? threshold_and_mask_self; - - /** MBSFIR[27] - * SRB_BUFFER_UE - */ - (rMBSFIR, bit(27)) ? self_th_1_UERE; - - /** MBSFIR[28] - * SRB_BUFFER_SUE - */ - (rMBSFIR, bit(28)) ? defaultMaskedError; - - /** MBSFIR[29] - * DIR_PURGE_CE - */ - (rMBSFIR, bit(29)) ? defaultMaskedError; - - /** MBSFIR[30] - * PROXIMAL_CE_UE - */ - (rMBSFIR, bit(30)) ? l4_th_1_UERE; - - /** MBSFIR[31:32] - * Spare - */ - (rMBSFIR, bit(31|32)) ? defaultMaskedError; - - /** MBSFIR[33] - * SCOM FIR error - */ - (rMBSFIR, bit(33)) ? threshold_and_mask_self; - - /** MBSFIR[34] - * SCOM FIR error clone - */ - (rMBSFIR, bit(34)) ? threshold_and_mask_self; - -}; - -################################################################################ -# Centaur chip MBSSECUREFIR -################################################################################ - -rule rMBSSECUREFIR -{ - UNIT_CS: - MBSSECUREFIR; -}; - -group gMBSSECUREFIR filter singlebit, cs_root_cause( 0, 1, 2, 3, 4, 5 ) -{ - /** MBSSECUREFIR[0] - * Invalid MBSXCR access - */ - (rMBSSECUREFIR, bit(0)) ? level2_th_1_UERE; - - /** MBSSECUREFIR[1] - * Invalid MBSXCR01 access - */ - (rMBSSECUREFIR, bit(1)) ? level2_th_1_UERE; - - /** MBSSECUREFIR[2] - * Invalid MBSXCR23 access - */ - (rMBSSECUREFIR, bit(2)) ? level2_th_1_UERE; - - /** MBSSECUREFIR[3] - * Invalid MBSXCRMS access - */ - (rMBSSECUREFIR, bit(3)) ? level2_th_1_UERE; - - /** MBSSECUREFIR[4] - * spare - */ - (rMBSSECUREFIR, bit(4)) ? level2_th_1_UERE; - - /** MBSSECUREFIR[5] - * Invalid SIR mask or action reg access - */ - (rMBSSECUREFIR, bit(5)) ? level2_th_1_UERE; - -}; - -################################################################################ -# Centaur chip MBSECCFIR 0 -################################################################################ - -rule rMBSECCFIR_0 -{ - UNIT_CS: - MBSECCFIR_0 & ~MBSECCFIR_0_MASK & ~MBSECCFIR_0_ACT0 & ~MBSECCFIR_0_ACT1; - RECOVERABLE: - MBSECCFIR_0 & ~MBSECCFIR_0_MASK & ~MBSECCFIR_0_ACT0 & MBSECCFIR_0_ACT1; -}; - -group gMBSECCFIR_0 filter priority ( 19, 41 ), - cs_root_cause( 19, 44, 47, 49 ) -{ - /** MBSECCFIR_0[0] - * Memory chip mark on rank 0 - */ - (rMBSECCFIR_0, bit(0)) ? verify_chip_mark_0_0; - - /** MBSECCFIR_0[1] - * Memory chip mark on rank 1 - */ - (rMBSECCFIR_0, bit(1)) ? verify_chip_mark_0_1; - - /** MBSECCFIR_0[2] - * Memory chip mark on rank 2 - */ - (rMBSECCFIR_0, bit(2)) ? verify_chip_mark_0_2; - - /** MBSECCFIR_0[3] - * Memory chip mark on rank 3 - */ - (rMBSECCFIR_0, bit(3)) ? verify_chip_mark_0_3; - - /** MBSECCFIR_0[4] - * Memory chip mark on rank 4 - */ - (rMBSECCFIR_0, bit(4)) ? verify_chip_mark_0_4; - - /** MBSECCFIR_0[5] - * Memory chip mark on rank 5 - */ - (rMBSECCFIR_0, bit(5)) ? verify_chip_mark_0_5; - - /** MBSECCFIR_0[6] - * Memory chip mark on rank 6 - */ - (rMBSECCFIR_0, bit(6)) ? verify_chip_mark_0_6; - - /** MBSECCFIR_0[7] - * Memory chip mark on rank 7 - */ - (rMBSECCFIR_0, bit(7)) ? verify_chip_mark_0_7; - - /** MBSECCFIR_0[8:15] - * Reserved - */ - (rMBSECCFIR_0, bit(8|9|10|11|12|13|14|15)) ? defaultMaskedError; - - /** MBSECCFIR_0[16] - * Memory NCE - */ - (rMBSECCFIR_0, bit(16)) ? mainline_nce_handling_0; - - /** MBSECCFIR_0[17] - * Memory RCE - */ - (rMBSECCFIR_0, bit(17)) ? mainline_rce_pue_handling_0; - - /** MBSECCFIR_0[18] - * Memory SUE - */ - (rMBSECCFIR_0, bit(18)) ? defaultMaskedError; - - /** MBSECCFIR_0[19] - * Memory UE - */ - (rMBSECCFIR_0, bit(19)) ? mainline_ue_handling_0_UERE; - - /** MBSECCFIR_0[20:27] - * Maintenance chip mark - */ - (rMBSECCFIR_0, bit(20|21|22|23|24|25|26|27)) ? defaultMaskedError; - - /** MBSECCFIR_0[28:35] - * Reserved - */ - (rMBSECCFIR_0, bit(28|29|30|31|32|33|34|35)) ? defaultMaskedError; - - /** MBSECCFIR_0[36] - * Maintenance NCE - */ - (rMBSECCFIR_0, bit(36)) ? defaultMaskedError; - - /** MBSECCFIR_0[37] - * Maintenance SCE - */ - (rMBSECCFIR_0, bit(37)) ? defaultMaskedError; - - /** MBSECCFIR_0[38] - * Maintenance MCE - */ - (rMBSECCFIR_0, bit(38)) ? defaultMaskedError; - - /** MBSECCFIR_0[39] - * Maintenance RCE - */ - (rMBSECCFIR_0, bit(39)) ? defaultMaskedError; - - /** MBSECCFIR_0[40] - * Maintenance SUE - */ - (rMBSECCFIR_0, bit(40)) ? defaultMaskedError; - - /** MBSECCFIR_0[41] - * Maintenance UE - */ - (rMBSECCFIR_0, bit(41)) ? defaultMaskedError; - - /** MBSECCFIR_0[42] - * MPE during use maintenance mark mode - */ - (rMBSECCFIR_0, bit(42)) ? defaultMaskedError; - - /** MBSECCFIR_0[43] - * Prefetch Memory UE - */ - (rMBSECCFIR_0, bit(43)) ? mainline_rce_pue_handling_0; - - /** MBSECCFIR_0[44] - * Memory RCD parity error - */ - (rMBSECCFIR_0, bit(44)) ? self_th_1_UERE; # CUMULUS_10 - - /** MBSECCFIR_0[45] - * Maintenance RCD parity error - */ - (rMBSECCFIR_0, bit(45)) ? defaultMaskedError; - - /** MBSECCFIR_0[46] - * Recoverable config reg PE - */ - (rMBSECCFIR_0, bit(46)) ? mba0_th_1; - - /** MBSECCFIR_0[47] - * Unrecoverable config reg PE - */ - (rMBSECCFIR_0, bit(47)) ? mba0_th_1_UERE; - - /** MBSECCFIR_0[48] - * Maskable config reg PE - */ - (rMBSECCFIR_0, bit(48)) ? threshold_and_mask_mba0; - - /** MBSECCFIR_0[49] - * ECC datapath parity error - */ - (rMBSECCFIR_0, bit(49)) ? mba0_th_1_UERE; - - /** MBSECCFIR_0[50] - * internal scom error - */ - (rMBSECCFIR_0, bit(50)) ? threshold_and_mask_mba0; - - /** MBSECCFIR_0[51] - * internal scom error clone - */ - (rMBSECCFIR_0, bit(51)) ? threshold_and_mask_mba0; - -}; - -################################################################################ -# Centaur chip MBSECCFIR 1 -################################################################################ - -rule rMBSECCFIR_1 -{ - UNIT_CS: - MBSECCFIR_1 & ~MBSECCFIR_1_MASK & ~MBSECCFIR_1_ACT0 & ~MBSECCFIR_1_ACT1; - RECOVERABLE: - MBSECCFIR_1 & ~MBSECCFIR_1_MASK & ~MBSECCFIR_1_ACT0 & MBSECCFIR_1_ACT1; -}; - -group gMBSECCFIR_1 filter priority ( 19, 41 ), - cs_root_cause( 19, 44, 47, 49 ) -{ - /** MBSECCFIR_1[0] - * Memory chip mark on rank 0 - */ - (rMBSECCFIR_1, bit(0)) ? verify_chip_mark_1_0; - - /** MBSECCFIR_1[1] - * Memory chip mark on rank 1 - */ - (rMBSECCFIR_1, bit(1)) ? verify_chip_mark_1_1; - - /** MBSECCFIR_1[2] - * Memory chip mark on rank 2 - */ - (rMBSECCFIR_1, bit(2)) ? verify_chip_mark_1_2; - - /** MBSECCFIR_1[3] - * Memory chip mark on rank 3 - */ - (rMBSECCFIR_1, bit(3)) ? verify_chip_mark_1_3; - - /** MBSECCFIR_1[4] - * Memory chip mark on rank 4 - */ - (rMBSECCFIR_1, bit(4)) ? verify_chip_mark_1_4; - - /** MBSECCFIR_1[5] - * Memory chip mark on rank 5 - */ - (rMBSECCFIR_1, bit(5)) ? verify_chip_mark_1_5; - - /** MBSECCFIR_1[6] - * Memory chip mark on rank 6 - */ - (rMBSECCFIR_1, bit(6)) ? verify_chip_mark_1_6; - - /** MBSECCFIR_1[7] - * Memory chip mark on rank 7 - */ - (rMBSECCFIR_1, bit(7)) ? verify_chip_mark_1_7; - - /** MBSECCFIR_1[8:15] - * Reserved - */ - (rMBSECCFIR_1, bit(8|9|10|11|12|13|14|15)) ? defaultMaskedError; - - /** MBSECCFIR_1[16] - * Memory NCE - */ - (rMBSECCFIR_1, bit(16)) ? mainline_nce_handling_1; - - /** MBSECCFIR_1[17] - * Memory RCE - */ - (rMBSECCFIR_1, bit(17)) ? mainline_rce_pue_handling_1; - - /** MBSECCFIR_1[18] - * Memory SUE - */ - (rMBSECCFIR_1, bit(18)) ? defaultMaskedError; - - /** MBSECCFIR_1[19] - * Memory UE - */ - (rMBSECCFIR_1, bit(19)) ? mainline_ue_handling_1_UERE; - - /** MBSECCFIR_1[20:27] - * Maintenance chip mark - */ - (rMBSECCFIR_1, bit(20|21|22|23|24|25|26|27)) ? defaultMaskedError; - - /** MBSECCFIR_1[28:35] - * Reserved - */ - (rMBSECCFIR_1, bit(28|29|30|31|32|33|34|35)) ? defaultMaskedError; - - /** MBSECCFIR_1[36] - * Maintenance NCE - */ - (rMBSECCFIR_1, bit(36)) ? defaultMaskedError; - - /** MBSECCFIR_1[37] - * Maintenance SCE - */ - (rMBSECCFIR_1, bit(37)) ? defaultMaskedError; - - /** MBSECCFIR_1[38] - * Maintenance MCE - */ - (rMBSECCFIR_1, bit(38)) ? defaultMaskedError; - - /** MBSECCFIR_1[39] - * Maintenance RCE - */ - (rMBSECCFIR_1, bit(39)) ? defaultMaskedError; - - /** MBSECCFIR_1[40] - * Maintenance SUE - */ - (rMBSECCFIR_1, bit(40)) ? defaultMaskedError; - - /** MBSECCFIR_1[41] - * Maintenance UE - */ - (rMBSECCFIR_1, bit(41)) ? defaultMaskedError; - - /** MBSECCFIR_1[42] - * MPE during use maintenance mark mode - */ - (rMBSECCFIR_1, bit(42)) ? defaultMaskedError; - - /** MBSECCFIR_1[43] - * Prefetch Memory UE - */ - (rMBSECCFIR_1, bit(43)) ? mainline_rce_pue_handling_1; - - /** MBSECCFIR_1[44] - * Memory RCD parity error - */ - (rMBSECCFIR_1, bit(44)) ? self_th_1_UERE; # CUMULUS_10 - - /** MBSECCFIR_1[45] - * Maintenance RCD parity error - */ - (rMBSECCFIR_1, bit(45)) ? defaultMaskedError; - - /** MBSECCFIR_1[46] - * Recoverable config reg PE - */ - (rMBSECCFIR_1, bit(46)) ? mba1_th_1; - - /** MBSECCFIR_1[47] - * Unrecoverable config reg PE - */ - (rMBSECCFIR_1, bit(47)) ? mba1_th_1_UERE; - - /** MBSECCFIR_1[48] - * Maskable config reg PE - */ - (rMBSECCFIR_1, bit(48)) ? threshold_and_mask_mba1; - - /** MBSECCFIR_1[49] - * ECC datapath parity error - */ - (rMBSECCFIR_1, bit(49)) ? mba1_th_1_UERE; - - /** MBSECCFIR_1[50] - * internal scom error - */ - (rMBSECCFIR_1, bit(50)) ? threshold_and_mask_mba1; - - /** MBSECCFIR_1[51] - * internal scom error clone - */ - (rMBSECCFIR_1, bit(51)) ? threshold_and_mask_mba1; - -}; - -################################################################################ -# Centaur chip SCACFIR -################################################################################ - -rule rSCACFIR -{ - UNIT_CS: - SCACFIR & ~SCACFIR_MASK & ~SCACFIR_ACT0 & ~SCACFIR_ACT1; - RECOVERABLE: - SCACFIR & ~SCACFIR_MASK & ~SCACFIR_ACT0 & SCACFIR_ACT1; -}; - -group gSCACFIR filter singlebit, cs_root_cause( 25, 26 ) -{ - /** SCACFIR[0] - * I2CM(0) Invalid Address - */ - (rSCACFIR, bit(0)) ? defaultMaskedError; - - /** SCACFIR[1] - * I2CM(1) Invalid Write - */ - (rSCACFIR, bit(1)) ? defaultMaskedError; - - /** SCACFIR[2] - * I2CM(2) Invalid Read - */ - (rSCACFIR, bit(2)) ? defaultMaskedError; - - /** SCACFIR[3] - * I2CM(3) Pib Address Parity Error - */ - (rSCACFIR, bit(3)) ? defaultMaskedError; - - /** SCACFIR[4] - * I2CM(4) Pib Parity Error - */ - (rSCACFIR, bit(4)) ? defaultMaskedError; - - /** SCACFIR[5] - * I2CM(5) LB parity error - */ - (rSCACFIR, bit(5)) ? defaultMaskedError; - - /** SCACFIR[6:9] - * spare - */ - (rSCACFIR, bit(6|7|8|9)) ? defaultMaskedError; - - /** SCACFIR[10] - * I2CM(45) : Invalid Command - */ - (rSCACFIR, bit(10)) ? defaultMaskedError; - - /** SCACFIR[11] - * I2CM(46) : Parity Error - */ - (rSCACFIR, bit(11)) ? defaultMaskedError; - - /** SCACFIR[12] - * I2CM(47): Backend Overrun Error - */ - (rSCACFIR, bit(12)) ? defaultMaskedError; - - /** SCACFIR[13] - * I2CM(48): Backend Access Error - */ - (rSCACFIR, bit(13)) ? defaultMaskedError; - - /** SCACFIR[14] - * I2CM(49): Arbitration Lost Error - */ - (rSCACFIR, bit(14)) ? defaultMaskedError; - - /** SCACFIR[15] - * I2CM(50): Nack Received Error - */ - (rSCACFIR, bit(15)) ? defaultMaskedError; - - /** SCACFIR[16] - * I2CM(53): Stop Error - */ - (rSCACFIR, bit(16)) ? defaultMaskedError; - - /** SCACFIR[17] - * Local PIB Response code 1 - */ - (rSCACFIR, bit(17)) ? defaultMaskedError; - - /** SCACFIR[18] - * Local PIB Response code 2 - */ - (rSCACFIR, bit(18)) ? defaultMaskedError; - - /** SCACFIR[19] - * Local PIB Response code 3 - */ - (rSCACFIR, bit(19)) ? defaultMaskedError; - - /** SCACFIR[20] - * Local PIB Response code 4 - */ - (rSCACFIR, bit(20)) ? defaultMaskedError; - - /** SCACFIR[21] - * Local PIB Response code 5 - */ - (rSCACFIR, bit(21)) ? defaultMaskedError; - - /** SCACFIR[22] - * Local PIB Response code 6 - */ - (rSCACFIR, bit(22)) ? defaultMaskedError; - - /** SCACFIR[23] - * Local PIB Response code 7 - */ - (rSCACFIR, bit(23)) ? defaultMaskedError; - - /** SCACFIR[24] - * Stall Threshold Error - */ - (rSCACFIR, bit(24)) ? defaultMaskedError; - - /** SCACFIR[25] - * Parity Error on Internal Register - */ - (rSCACFIR, bit(25)) ? self_th_1_UERE; - - /** SCACFIR[26] - * Parity Error on Pib Target Register - */ - (rSCACFIR, bit(26)) ? self_th_1_UERE; - - /** SCACFIR[27:31] - * Reserved - */ - (rSCACFIR, bit(27|28|29|30|31)) ? defaultMaskedError; - - /** SCACFIR[32] - * State Machine / Ctrl Logic Error - */ - (rSCACFIR, bit(32)) ? self_th_1; - - /** SCACFIR[33] - * Register access error - */ - (rSCACFIR, bit(33)) ? level2_th_1; - - /** SCACFIR[34] - * PIB error initiating RESET cmd to I2CM - */ - (rSCACFIR, bit(34)) ? defaultMaskedError; - - /** SCACFIR[35] - * Internal SCOM Error - */ - (rSCACFIR, bit(35)) ? threshold_and_mask_self; - - /** SCACFIR[36] - * Internal SCOM Error - */ - (rSCACFIR, bit(36)) ? threshold_and_mask_self; - -}; - -################################################################################ -# Centaur chip MCBISTFIR 0 -################################################################################ - -rule rMCBISTFIR_0 -{ - UNIT_CS: - MCBISTFIR_0 & ~MCBISTFIR_0_MASK & ~MCBISTFIR_0_ACT0 & ~MCBISTFIR_0_ACT1; - RECOVERABLE: - MCBISTFIR_0 & ~MCBISTFIR_0_MASK & ~MCBISTFIR_0_ACT0 & MCBISTFIR_0_ACT1; -}; - -group gMCBISTFIR_0 filter singlebit, cs_root_cause( 0, 1 ) -{ - /** MCBISTFIR_0[0] - * SCOM Parity Errors - */ - (rMCBISTFIR_0, bit(0)) ? mba0_th_1_UERE; - - /** MCBISTFIR_0[1] - * MBX parity errors - */ - (rMCBISTFIR_0, bit(1)) ? mba0_th_1_UERE; - - /** MCBISTFIR_0[2] - * DRAM event 0 error - */ - (rMCBISTFIR_0, bit(2)) ? defaultMaskedError; - - /** MCBISTFIR_0[3] - * DRAM event 1 error - */ - (rMCBISTFIR_0, bit(3)) ? defaultMaskedError; - - /** MCBISTFIR_0[4:14] - * Reserved - */ - (rMCBISTFIR_0, bit(4|5|6|7|8|9|10|11|12|13|14)) ? defaultMaskedError; - - /** MCBISTFIR_0[15] - * SCOM FIR error - */ - (rMCBISTFIR_0, bit(15)) ? threshold_and_mask_mba0; - - /** MCBISTFIR_0[16] - * SCOM FIR error clone - */ - (rMCBISTFIR_0, bit(16)) ? threshold_and_mask_mba0; - -}; - -################################################################################ -# Centaur chip MCBISTFIR 1 -################################################################################ - -rule rMCBISTFIR_1 -{ - UNIT_CS: - MCBISTFIR_1 & ~MCBISTFIR_1_MASK & ~MCBISTFIR_1_ACT0 & ~MCBISTFIR_1_ACT1; - RECOVERABLE: - MCBISTFIR_1 & ~MCBISTFIR_1_MASK & ~MCBISTFIR_1_ACT0 & MCBISTFIR_1_ACT1; -}; - -group gMCBISTFIR_1 filter singlebit, cs_root_cause( 0, 1 ) -{ - /** MCBISTFIR_1[0] - * SCOM Parity Errors - */ - (rMCBISTFIR_1, bit(0)) ? mba1_th_1_UERE; - - /** MCBISTFIR_1[1] - * MBX parity errors - */ - (rMCBISTFIR_1, bit(1)) ? mba1_th_1_UERE; - - /** MCBISTFIR_1[2] - * DRAM event 0 error - */ - (rMCBISTFIR_1, bit(2)) ? defaultMaskedError; - - /** MCBISTFIR_1[3] - * DRAM event 1 error - */ - (rMCBISTFIR_1, bit(3)) ? defaultMaskedError; - - /** MCBISTFIR_1[4:14] - * Reserved - */ - (rMCBISTFIR_1, bit(4|5|6|7|8|9|10|11|12|13|14)) ? defaultMaskedError; - - /** MCBISTFIR_1[15] - * SCOM FIR error - */ - (rMCBISTFIR_1, bit(15)) ? threshold_and_mask_mba1; - - /** MCBISTFIR_1[16] - * SCOM FIR error clone - */ - (rMCBISTFIR_1, bit(16)) ? threshold_and_mask_mba1; - -}; - -################################################################################ -# MEM Chiplet FIR -################################################################################ - -rule rMEM_CHIPLET_FIR -{ - UNIT_CS: - MEM_CHIPLET_CS_FIR & ~MEM_CHIPLET_FIR_MASK & `1fffffffffffffff`; - RECOVERABLE: - (MEM_CHIPLET_RE_FIR >> 2) & ~MEM_CHIPLET_FIR_MASK & `1fffffffffffffff`; -}; - -group gMEM_CHIPLET_FIR filter singlebit -{ - /** MEM_CHIPLET_FIR[3] - * Attention from MEM_LFIR - */ - (rMEM_CHIPLET_FIR, bit(3)) ? analyze(gMEM_LFIR); - - /** MEM_CHIPLET_FIR[5] - * Attention from MBACALFIR 0 - */ - (rMEM_CHIPLET_FIR, bit(5)) ? analyzeConnectedMBA0; - - /** MEM_CHIPLET_FIR[6] - * Attention from MBAFIR 0 - */ - (rMEM_CHIPLET_FIR, bit(6)) ? analyzeConnectedMBA0; - - /** MEM_CHIPLET_FIR[7] - * Attention from MBACALFIR 1 - */ - (rMEM_CHIPLET_FIR, bit(7)) ? analyzeConnectedMBA1; - - /** MEM_CHIPLET_FIR[8] - * Attention from MBAFIR 1 - */ - (rMEM_CHIPLET_FIR, bit(8)) ? analyzeConnectedMBA1; - - /** MEM_CHIPLET_FIR[9] - * Attention from MBADDRPHYFIR 0 - */ - (rMEM_CHIPLET_FIR, bit(9)) ? analyzeConnectedMBA0; - - /** MEM_CHIPLET_FIR[10] - * Attention from MBADDRPHYFIR 1 - */ - (rMEM_CHIPLET_FIR, bit(10)) ? analyzeConnectedMBA1; - - /** MEM_CHIPLET_FIR[12] - * Attention from MBASECUREFIR 0 - */ - (rMEM_CHIPLET_FIR, bit(12)) ? analyzeConnectedMBA0; - - /** MEM_CHIPLET_FIR[13] - * Attention from MBASECUREFIR 1 - */ - (rMEM_CHIPLET_FIR, bit(13)) ? analyzeConnectedMBA1; - -}; - -################################################################################ -# MEM Chiplet Special Attention FIR -################################################################################ - -rule rMEM_CHIPLET_SPA_FIR -{ - HOST_ATTN: - MEM_CHIPLET_SPA_FIR & ~MEM_CHIPLET_SPA_FIR_MASK; -}; - -group gMEM_CHIPLET_SPA_FIR filter singlebit -{ - /** MEM_CHIPLET_SPA_FIR[0] - * Attention from MBASPA 0 - */ - (rMEM_CHIPLET_SPA_FIR, bit(0)) ? analyzeConnectedMBA0; - - /** MEM_CHIPLET_SPA_FIR[1] - * Attention from MBASPA 1 - */ - (rMEM_CHIPLET_SPA_FIR, bit(1)) ? analyzeConnectedMBA1; - -}; - -################################################################################ -# Centaur chip MEM_LFIR -################################################################################ - -rule rMEM_LFIR -{ - UNIT_CS: - MEM_LFIR & ~MEM_LFIR_MASK & ~MEM_LFIR_ACT0 & ~MEM_LFIR_ACT1; - RECOVERABLE: - MEM_LFIR & ~MEM_LFIR_MASK & ~MEM_LFIR_ACT0 & MEM_LFIR_ACT1; -}; - -group gMEM_LFIR filter singlebit, cs_root_cause -{ - /** MEM_LFIR[0] - * CFIR internal parity error - */ - (rMEM_LFIR, bit(0)) ? threshold_and_mask_self; - - /** MEM_LFIR[1] - * GPIO (PCB error) - */ - (rMEM_LFIR, bit(1)) ? defaultMaskedError; - - /** MEM_LFIR[2] - * CC (PCB error) - */ - (rMEM_LFIR, bit(2)) ? defaultMaskedError; - - /** MEM_LFIR[3] - * CC (OPCG, parity, scan collision, ...) - */ - (rMEM_LFIR, bit(3)) ? defaultMaskedError; - - /** MEM_LFIR[4] - * PSC (PCB error) - */ - (rMEM_LFIR, bit(4)) ? defaultMaskedError; - - /** MEM_LFIR[5] - * PSC (parity error) - */ - (rMEM_LFIR, bit(5)) ? defaultMaskedError; - - /** MEM_LFIR[6] - * Thermal (parity error) - */ - (rMEM_LFIR, bit(6)) ? defaultMaskedError; - - /** MEM_LFIR[7] - * Thermal (PCB error) - */ - (rMEM_LFIR, bit(7)) ? defaultMaskedError; - - /** MEM_LFIR[8] - * Thermal (critical trip error) - */ - (rMEM_LFIR, bit(8)) ? defaultMaskedError; - - /** MEM_LFIR[9] - * Thermal (fatal trip error) - */ - (rMEM_LFIR, bit(9)) ? defaultMaskedError; - - /** MEM_LFIR[10] - * Thermal (voltage trip error) - */ - (rMEM_LFIR, bit(10)) ? defaultMaskedError; - - /** MEM_LFIR[11] - * MBA01 Trace Array ( error) - */ - (rMEM_LFIR, bit(11)) ? defaultMaskedError; - - /** MEM_LFIR[12] - * MBA01 Trace Array ( error) - */ - (rMEM_LFIR, bit(12)) ? defaultMaskedError; - - /** MEM_LFIR[13] - * MBA23 Trace Array ( error) - */ - (rMEM_LFIR, bit(13)) ? defaultMaskedError; - - /** MEM_LFIR[14] - * MBA23 Trace Array ( error) - */ - (rMEM_LFIR, bit(14)) ? defaultMaskedError; - - /** MEM_LFIR[15:39] - * Reserved - */ - (rMEM_LFIR, bit(15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? defaultMaskedError; - - /** MEM_LFIR[40] - * malfunction alert (local xstop in another chiplet) - */ - (rMEM_LFIR, bit(40)) ? defaultMaskedError; - -}; - -# Import all of the chiplet rules and actions -.include "Membuf_acts_TP.rule" -.include "Membuf_acts_NEST.rule" -.include "Membuf_acts_MEM.rule" - - ############################################################################## - # # - # # ### # - # # # ## ##### ### ### # # # # # # ### ### ### ### # - # # # # # # # # # ## # # # # # # # # # # - # ####### # # # # # # # # # # ##### ### ### ## ### # - # # # # # # # # # # ## # # # # # # # # # # - # # # ## # ### ### # # ### ### # # ### ### ### ### # - # # - ############################################################################## - -# Include the common action set. -.include "CommonActions.rule" - diff --git a/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_NEST.rule b/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_NEST.rule deleted file mode 100755 index c1fbb30bc..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_NEST.rule +++ /dev/null @@ -1,55 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_NEST.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2018 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -################################################################################ -# Actions specific to NEST chiplet -################################################################################ - -/** Callout the DMI bus */ -actionclass calloutDmiBus -{ - calloutSelfMedA; - callout(connected(TYPE_MCS), MRU_MEDA); - funccall("calloutInterface_dmi"); -}; - -/** Handles MBACAL parity err if present, else handles MBA0 MBSECC Memory UE */ -actionclass mba0MemoryUe -{ - try ( funccall("analyzeMbaRcdParityError0"), analyzeFetchUe0 ); -}; - -/** Handles MBACAL parity err if present, else handles MBA1 MBSECC Memory UE */ -actionclass mba1MemoryUe -{ - try ( funccall("analyzeMbaRcdParityError1"), analyzeFetchUe1 ); -}; - -/** Callout the DMI bus, threshold 1 */ -actionclass calloutDmiBusTh1 { calloutDmiBus; threshold1; }; - -/** Callout the DMI bus, threshold 2 per day */ -actionclass calloutDmiBusTh2pday { calloutDmiBus; threshold2pday; }; - diff --git a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_MEM.rule b/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_MEM.rule deleted file mode 100755 index 8bf48cd6d..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_MEM.rule +++ /dev/null @@ -1,37 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_MEM.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2018 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - - ############################################################################ - # Error Report Registers - ############################################################################ - - register MEM_ERROR_STATUS - { - name "TCM.ERROR_STATUS"; - scomaddr 0x03030009; - capture group CerrRegs; - capture group MemChipletRegs; - }; - diff --git a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule b/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule deleted file mode 100755 index f996d93af..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule +++ /dev/null @@ -1,514 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2018 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - - ############################################################################ - # NEST Chiplet MBIFIR - ############################################################################ - - register MBIFIR_AND - { - name "MBU.MBI.MBI.SCOMFIR.MBIFIRQ AND"; - scomaddr 0x02010801; - capture group never; - access write_only; - }; - - ############################################################################ - # NEST Chiplet MBSECCFIR_0 - ############################################################################ - - register MBSECCFIR_0_AND - { - name "MBU.MBS.ECC01.MBECCFIR_AND"; - scomaddr 0x02011441; - capture group never; - access write_only; - }; - - register MBSECCFIR_0_MASK_AND - { - name "MBU.MBS.ECC01.MBECCFIR_MASK_AND"; - scomaddr 0x02011444; - capture group never; - access write_only; - }; - - register MBSECCFIR_0_MASK_OR - { - name "MBU.MBS.ECC01.MBECCFIR_MASK_OR"; - scomaddr 0x02011445; - capture group never; - access write_only; - }; - - ############################################################################ - # NEST Chiplet MBSECCFIR_1 - ############################################################################ - - register MBSECCFIR_1_AND - { - name "MBU.MBS.ECC23.MBECCFIR_AND"; - scomaddr 0x02011481; - capture group never; - access write_only; - }; - - register MBSECCFIR_1_MASK_AND - { - name "MBU.MBS.ECC23.MBECCFIR_MASK_AND"; - scomaddr 0x02011484; - capture group never; - access write_only; - }; - - register MBSECCFIR_1_MASK_OR - { - name "MBU.MBS.ECC23.MBECCFIR_MASK_OR"; - scomaddr 0x02011485; - capture group never; - access write_only; - }; - - ############################################################################ - # NEST Chiplet NESTFBISTFIR - ############################################################################ - - # FIR not used. Capture for FFDC only. - - register NESTFBISTFIR - { - name "FBIST.FBN.FBN_FIR_REG"; - scomaddr 0x02010880; - capture group default; - capture group FirRegs; - }; - - ############################################################################ - # Error Report Registers - ############################################################################ - - register NEST_ERROR_STATUS - { - name "TCN.ERROR_STATUS"; - scomaddr 0x02030009; - capture group default; - capture group CerrRegs; - }; - - register MBIERPT - { - name "MBU.MBI.MBI.MBIERPT0"; - scomaddr 0x0201080F; - capture group default; - capture group CerrRegs; - }; - - register MBSCERR1 - { - name "MBU.MBS.MBSCERR1Q"; - scomaddr 0x02011413; - capture group default; - capture group CerrRegs; - }; - - register MBSCERR2 - { - name "MBU.MBS.MBSCERR2Q"; - scomaddr 0x0201142C; - capture group default; - capture group CerrRegs; - }; - - register MBA0_MBSECCERRPT_0 - { - name "MBU.MBS.ECC01.MBSECCERR0"; - scomaddr 0x02011466; - capture group default; - capture group CerrRegs; - capture group MaintCmdRegs_mba0; - }; - - register MBA0_MBSECCERRPT_1 - { - name "MBU.MBS.ECC01.MBSECCERR1"; - scomaddr 0x02011467; - capture group default; - capture group CerrRegs; - capture group MaintCmdRegs_mba0; - }; - - register MBA1_MBSECCERRPT_0 - { - name "MBU.MBS.ECC23.MBSECCERR0"; - scomaddr 0x020114A6; - capture group default; - capture group CerrRegs; - capture group MaintCmdRegs_mba1; - }; - - register MBA1_MBSECCERRPT_1 - { - name "MBU.MBS.ECC23.MBSECCERR1"; - scomaddr 0x020114A7; - capture group default; - capture group CerrRegs; - capture group MaintCmdRegs_mba1; - }; - - register MBA0_MBXERRSTAT - { - name "MBU.MBS.MCBISTS01.SCOMFIR.MBXERRSTATQ"; - scomaddr 0x0201168f; - capture group default; - capture group CerrRegs; - }; - - register MBA1_MBXERRSTAT - { - name "MBU.MBS.MCBISTS23.SCOMFIR.MBXERRSTATQ"; - scomaddr 0x0201178f; - capture group default; - capture group CerrRegs; - }; - - register SENSORCACHEERRPT - { - name "SCAC.SCAC_ERRRPT"; - scomaddr 0x020115D4; - capture group default; - capture group CerrRegs; - }; - - ############################################################################ - # Memory ECC Error Address Registers - ############################################################################ - - register MBA0_MBNCER - { - name "MBA0: MBS Memory NCE Error Address Register"; - scomaddr 0x02011660; - capture group default; - }; - - register MBA0_MBRCER - { - name "MBA0: MBS Memory RCE Error Address Register"; - scomaddr 0x02011661; - capture group default; - }; - - register MBA0_MBMPER - { - name "MBA0: MBS Memory MPE Error Address Register"; - scomaddr 0x02011662; - capture group default; - }; - - register MBA0_MBUER - { - name "MBA0: MBS Memory UE Error Address Register"; - scomaddr 0x02011663; - capture group default; - }; - - register MBA1_MBNCER - { - name "MBA1: MBS Memory NCE Error Address Register"; - scomaddr 0x02011760; - capture group default; - }; - - register MBA1_MBRCER - { - name "MBA1: MBS Memory RCE Error Address Register"; - scomaddr 0x02011761; - capture group default; - }; - - register MBA1_MBMPER - { - name "MBA1: MBS Memory MPE Error Address Register"; - scomaddr 0x02011762; - capture group default; - }; - - register MBA1_MBUER - { - name "MBA1: MBS Memory UE Error Address Register"; - scomaddr 0x02011763; - capture group default; - }; - - ############################################################################ - # NEST Chiplet memory maintenance error count registers - ############################################################################ - - register MBA0_MBSEC0 - { - name "MBU.MBS.MCBISTS01.SCOMFIR.MBSEC0Q"; - scomaddr 0x02011653; - capture group default; - capture group MaintCmdRegs_mba0; - }; - - register MBA0_MBSEC1 - { - name "MBU.MBS.MCBISTS01.SCOMFIR.MBSEC1Q"; - scomaddr 0x02011654; - capture group default; - capture group MaintCmdRegs_mba0; - }; - - register MBA1_MBSEC0 - { - name "MBU.MBS.MCBISTS23.SCOMFIR.MBSEC0Q"; - scomaddr 0x02011753; - capture group default; - capture group MaintCmdRegs_mba1; - }; - - register MBA1_MBSEC1 - { - name "MBU.MBS.MCBISTS23.SCOMFIR.MBSEC1Q"; - scomaddr 0x02011754; - capture group default; - capture group MaintCmdRegs_mba1; - }; - - ############################################################################ - # NEST Chiplet memory maintenance threshold control registers - ############################################################################ - - register MBSTR_0 - { - name "MBU.MBS.MCBISTS01.SCOMFIR.MBSTRQ"; - scomaddr 0x02011655; - capture group default; - capture group MaintCmdRegs_mba0; - }; - - register MBSTR_1 - { - name "MBU.MBS.MCBISTS23.SCOMFIR.MBSTRQ"; - scomaddr 0x02011755; - capture group default; - capture group MaintCmdRegs_mba1; - }; - - ############################################################################ - # NEST Chiplet memory maintenance symbol error control registers - ############################################################################ - - register MBA0_MBSSYMEC0 - { - name "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC0Q"; - scomaddr 0x02011656; - capture group default; - capture group MaintCmdRegs_mba0; - }; - - register MBA0_MBSSYMEC1 - { - name "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC1Q"; - scomaddr 0x02011657; - capture group default; - capture group MaintCmdRegs_mba0; - }; - - register MBA0_MBSSYMEC2 - { - name "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC2Q"; - scomaddr 0x02011658; - capture group default; - capture group MaintCmdRegs_mba0; - }; - - register MBA0_MBSSYMEC3 - { - name "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC3Q"; - scomaddr 0x02011659; - capture group default; - capture group MaintCmdRegs_mba0; - }; - - register MBA0_MBSSYMEC4 - { - name "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC4Q"; - scomaddr 0x0201165a; - capture group default; - capture group MaintCmdRegs_mba0; - }; - - register MBA0_MBSSYMEC5 - { - name "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC5Q"; - scomaddr 0x0201165b; - capture group default; - capture group MaintCmdRegs_mba0; - }; - - register MBA0_MBSSYMEC6 - { - name "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC6Q"; - scomaddr 0x0201165c; - capture group default; - capture group MaintCmdRegs_mba0; - }; - - register MBA0_MBSSYMEC7 - { - name "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC7Q"; - scomaddr 0x0201165d; - capture group default; - capture group MaintCmdRegs_mba0; - }; - - register MBA0_MBSSYMEC8 - { - name "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC8Q"; - scomaddr 0x0201165e; - capture group default; - capture group MaintCmdRegs_mba0; - }; - - register MBA1_MBSSYMEC0 - { - name "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC0Q"; - scomaddr 0x02011756; - capture group default; - capture group MaintCmdRegs_mba1; - }; - - register MBA1_MBSSYMEC1 - { - name "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC1Q"; - scomaddr 0x02011757; - capture group default; - capture group MaintCmdRegs_mba1; - }; - - register MBA1_MBSSYMEC2 - { - name "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC2Q"; - scomaddr 0x02011758; - capture group default; - capture group MaintCmdRegs_mba1; - }; - - register MBA1_MBSSYMEC3 - { - name "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC3Q"; - scomaddr 0x02011759; - capture group default; - capture group MaintCmdRegs_mba1; - }; - - register MBA1_MBSSYMEC4 - { - name "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC4Q"; - scomaddr 0x0201175a; - capture group default; - capture group MaintCmdRegs_mba1; - }; - - register MBA1_MBSSYMEC5 - { - name "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC5Q"; - scomaddr 0x0201175b; - capture group default; - capture group MaintCmdRegs_mba1; - }; - - register MBA1_MBSSYMEC6 - { - name "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC6Q"; - scomaddr 0x0201175c; - capture group default; - capture group MaintCmdRegs_mba1; - }; - - register MBA1_MBSSYMEC7 - { - name "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC7Q"; - scomaddr 0x0201175d; - capture group default; - capture group MaintCmdRegs_mba1; - }; - - register MBA1_MBSSYMEC8 - { - name "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC8Q"; - scomaddr 0x0201175e; - capture group default; - capture group MaintCmdRegs_mba1; - }; - - ############################################################################ - # NEST Chiplet memory fetch error vector registers - ############################################################################ - - register MBA0_MBSEVR - { - name "MBU.MBS.MCBISTS01.SCOMFIR.MBSEVRQ"; - scomaddr 0x0201165f; - capture group default; - }; - - register MBA1_MBSEVR - { - name "MBU.MBS.MCBISTS23.SCOMFIR.MBSEVRQ"; - scomaddr 0x0201175f; - capture group default; - }; - - ############################################################################ - # MBA Address Translate Control Register - ############################################################################ - - register MBA0_MBAXCR - { - name "MBU.MBS.ARB.RXLT.MBAXCR01Q"; - scomaddr 0x0201140B; - capture group default; - }; - - register MBA1_MBAXCR - { - name "MBU.MBS.ARB.RXLT.MBAXCR23Q"; - scomaddr 0x0201140C; - capture group default; - }; - - ############################################################################ - # MBS Address Translate Control Register - ############################################################################ - - register MBSXCR - { - name "MBU.MBS.ARB.RXLT.MBSXCRQ"; - scomaddr 0x0201140A; - capture group never; - }; - diff --git a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_TP.rule b/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_TP.rule deleted file mode 100755 index 37c20f67d..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_TP.rule +++ /dev/null @@ -1,57 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_TP.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2018 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - - ############################################################################ - # TP Chiplet LFIR - ############################################################################ - - register TP_LFIR_AND - { - name "TPTOP.TPC.LOCAL_FIR_AND"; - scomaddr 0x0104000b; - capture group never; - access write_only; - }; - - register TP_LFIR_MASK_OR - { - name "TPTOP.TPC.EPS.FIR.LOCAL_FIR_MASK_OR"; - scomaddr 0x0104000f; - capture group never; - access write_only; - }; - - ############################################################################ - # Error Report Registers - ############################################################################ - - register TP_ERROR_STATUS - { - name "TPTOP.TPC.ERROR_STATUS"; - scomaddr 0x01030009; - capture group default; - capture group CerrRegs; - }; - diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaCaptureData.C b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaCaptureData.C index f6aa5b50a..57bdbac0e 100644 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaCaptureData.C +++ b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaCaptureData.C @@ -57,74 +57,6 @@ namespace CenMbaCaptureData //------------------------------------------------------------------------------ -void addMemChipletFirRegs( ExtensibleChip * i_membChip, CaptureData & io_cd ) -{ - #define PRDF_FUNC "[CenMbaCaptureData::addMemChipletFirRegs] " - - int32_t l_rc = SUCCESS; - - do - { - if ( NULL == i_membChip ) - { - PRDF_ERR( PRDF_FUNC "Given target is NULL" ); - break; - } - - if ( TYPE_MEMBUF != getTargetType(i_membChip->GetChipHandle()) ) - { - PRDF_ERR( PRDF_FUNC "Invalid target type: i_membChip=0x%08x", - i_membChip->GetId() ); - break; - } - - SCAN_COMM_REGISTER_CLASS * cs_global, * re_global, * spa_global; - cs_global = i_membChip->getRegister("GLOBAL_CS_FIR"); - re_global = i_membChip->getRegister("GLOBAL_RE_FIR"); - spa_global = i_membChip->getRegister("GLOBAL_SPA_FIR"); - l_rc = cs_global->Read() | re_global->Read() | spa_global->Read(); - if ( SUCCESS != l_rc ) - { - PRDF_ERR( PRDF_FUNC "Failed to read a GLOBAL register on " - "0x%08x", i_membChip->GetId() ); - break; - } - - // If global bit 3 is not on, can't scom mem chiplets or mba's - if( ! (cs_global->IsBitSet(3) || - re_global->IsBitSet(3) || - spa_global->IsBitSet(3)) ) - { - break; - } - - i_membChip->CaptureErrorData(io_cd, - Util::hashString("MemChipletRegs")); - - CenMembufDataBundle * membdb = getMembufDataBundle( i_membChip ); - - for ( uint32_t i = 0; i < MAX_MBA_PER_MEMBUF; i++ ) - { - ExtensibleChip * mbaChip = membdb->getMbaChip(i); - if ( NULL == mbaChip ) - { - PRDF_ERR( PRDF_FUNC "MEM_CHIPLET registers indicated an " - "attention but no chip found: i_membChip=0x%08x " - "i=%d", i_membChip->GetId(), i ); - continue; - } - - mbaChip->CaptureErrorData(io_cd, - Util::hashString("MemChipletRegs") ); - } - - } while (0); - - #undef PRDF_FUNC -} - -//------------------------------------------------------------------------------ - void addEccData( TargetHandle_t i_mbaTrgt, errlHndl_t io_errl ) { CaptureData cd; diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaCaptureData.H b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaCaptureData.H index daff6e42f..51a0dfe2b 100644 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaCaptureData.H +++ b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaCaptureData.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2016 */ +/* Contributors Listed Below - COPYRIGHT 2013,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -46,19 +46,6 @@ namespace CenMbaCaptureData { /** - * @brief Adds all Mem chiplet and MBA regs to the capture data for any MBA - * reporting an active attention via the MEM_CHIPLET_FIRs. - * @note This is only intended to be called in the MCS or MEMBUF PreAnalysis() - * plugins to capture the required FIR registers for FFDC. - * @note We are required to do the active attention check because there is a - * small window during the IPL where we may get an MCS or MEMBUF - * attention and the MBAs are not SCOMable at the time. - * @param i_membChip A MEMBUF chip. - * @param io_cd Capture data struct. - */ -void addMemChipletFirRegs( ExtensibleChip * i_membChip, CaptureData & io_cd ); - -/** * @brief Adds Memory ECC FFDC to an error log. * @note This is intended to be used in non-normal analysis paths that do not * have an SDC (i.e. Restore DRAM Repairs, IPL MNFG CE Isolation). diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMembuf.C b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMembuf.C index 2a2b8da3d..70ede507b 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMembuf.C +++ b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMembuf.C @@ -136,18 +136,6 @@ int32_t PreAnalysis( ExtensibleChip * i_mbChip, STEP_CODE_DATA_STRUCT & i_sc, o_analyzed = false; - // Get memory capture data. - CaptureData & cd = i_sc.service_data->GetCaptureData(); - CenMembufDataBundle * mbdb = getMembufDataBundle( i_mbChip ); - ExtensibleChip * mcsChip = mbdb->getMcsChip(); - if ( NULL != mcsChip ) - { - mcsChip->CaptureErrorData( cd, Util::hashString("FirRegs") ); - mcsChip->CaptureErrorData( cd, Util::hashString("CerrRegs") ); - - CenMbaCaptureData::addMemChipletFirRegs( i_mbChip, cd ); - } - // Check for a Centaur Checkstop do { diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfP8Mcs.C b/src/usr/diag/prdf/common/plat/pegasus/prdfP8Mcs.C index 02f021e76..dd206ba3e 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfP8Mcs.C +++ b/src/usr/diag/prdf/common/plat/pegasus/prdfP8Mcs.C @@ -84,18 +84,6 @@ int32_t PreAnalysis( ExtensibleChip * i_mcsChip, STEP_CODE_DATA_STRUCT & i_sc, { o_analyzed = false; - // Get memory capture data. - CaptureData & cd = i_sc.service_data->GetCaptureData(); - P8McsDataBundle * mcsdb = getMcsDataBundle( i_mcsChip ); - ExtensibleChip * membChip = mcsdb->getMembChip(); - if ( NULL != membChip ) - { - membChip->CaptureErrorData( cd, Util::hashString("FirRegs") ); - membChip->CaptureErrorData( cd, Util::hashString("CerrRegs") ); - - CenMbaCaptureData::addMemChipletFirRegs( membChip, cd ); - } - // Check for a Centaur Checkstop int32_t o_rc = MemUtils::checkMcsChannelFail( i_mcsChip, i_sc ); if ( SUCCESS != o_rc ) |
