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author | Luke Mulkey <lwmulkey@us.ibm.com> | 2017-07-10 11:44:24 -0500 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-01-13 13:50:59 -0500 |
commit | f230133c8502ad16a4e3b2bf9cf0bdd813caab60 (patch) | |
tree | e09f52d86632d8d8a4ffd0bb9253401e6c943dfd | |
parent | a9040e3c67fd7557cd6ba6b692cd20907e08b385 (diff) | |
download | talos-hostboot-f230133c8502ad16a4e3b2bf9cf0bdd813caab60.tar.gz talos-hostboot-f230133c8502ad16a4e3b2bf9cf0bdd813caab60.zip |
Lab tools for p9c.
mcbist wrapper via training_advanced_run
Change-Id: Idcdf0b10c3ca47d3c875a83cabd9f9b8a69f812d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44292
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44387
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
8 files changed, 256 insertions, 134 deletions
diff --git a/src/import/chips/centaur/procedures/hwp/memory/01common.mk b/src/import/chips/centaur/procedures/hwp/memory/01common.mk index 5b5035ac6..986b75bf1 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/01common.mk +++ b/src/import/chips/centaur/procedures/hwp/memory/01common.mk @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2015,2017 +# Contributors Listed Below - COPYRIGHT 2015,2018 # [+] International Business Machines Corp. # # @@ -30,8 +30,14 @@ CEN_INCLUDES += $(ROOTPATH)/chips/centaur/procedures/hwp/memory/lib CEN_INCLUDES += $(ROOTPATH)/chips/centaur/procedures/hwp/memory/lib/shared CEN_INCLUDES += $(ROOTPATH)/chips/centaur/procedures/hwp/initfiles/ +CEN_MSS_LAB_PATH := $(ROOTPATH)/chips/centaur/procedures/hwp/memory/lab + CEN_CATCH_UNIT_TESTS_INCLUDES := $(ROOTPATH)/hwpf/fapi2/test # ADD_MEMORY_INCDIRS # This macro will add additional include paths for all memory modules ADD_MEMORY_INCDIRS = $(call __ADD_MODULE_INCDIR,$(1),$(CEN_INCLUDES)) +ADD_MEMORY_SRCDIRS = $(call __ADD_MODULE_SRCDIR,$(1),$(ROOTPATH)/chips/centaur/procedures/hwp/memory) + +# Include main MSS Lab makefile +-include $(CEN_MSS_LAB_PATH)/01mss_lab.mk diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_access_delay_reg.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_access_delay_reg.C index 10fcda2bf..409261d0d 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_access_delay_reg.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_access_delay_reg.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,7 +38,7 @@ // My Includes //---------------------------------------------------------------------- #include <p9c_mss_access_delay_reg.H> - +#include <generic/memory/lib/utils/c_str.H> //---------------------------------------------------------------------- // Includes //---------------------------------------------------------------------- @@ -156,18 +156,26 @@ extern "C" { } FAPI_ASSERT(i_port_u8 < MAX_PORTS_PER_MBA, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "Wrong port specified (%d)", i_port_u8); FAPI_ASSERT(l_mbapos < MAX_MBA_PER_CEN, fapi2::CEN_MSS_ACCESS_DELAY_REG_BAD_MBA_POS(). - set_MBA_POS(l_mbapos), + set_MBA_POS(l_mbapos). + set_MBA_TARGET(i_target_mba), "Bad position from ATTR_CHIP_UNIT_POS (%d)", l_mbapos); FAPI_ASSERT((l_dram_width == fapi2::ENUM_ATTR_CEN_EFF_DRAM_WIDTH_X4) || (l_dram_width == fapi2::ENUM_ATTR_CEN_EFF_DRAM_WIDTH_X8), fapi2::CEN_MSS_ACCESS_DELAY_REG_BAD_DRAM_WIDTH(). - set_DRAM_WIDTH(l_dram_width), + set_DRAM_WIDTH(l_dram_width). + set_MBA_TARGET(i_target_mba), "Bad dram width from ATTR_EFF_DRAM_WIDTH (%d)", l_dram_width); if(i_verbose) @@ -180,7 +188,13 @@ extern "C" { if(l_dimmtype == fapi2::ENUM_ATTR_CEN_EFF_CUSTOM_DIMM_YES) { FAPI_ASSERT(i_input_index_u8 < CDIMM_MAX_DQ_80, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "CDIMM_DQ: Wrong input index specified (%d, max %d)" , i_input_index_u8, CDIMM_MAX_DQ_80); l_type = CDIMM_DQ; @@ -188,7 +202,13 @@ extern "C" { else { FAPI_ASSERT(i_input_index_u8 < ISDIMM_MAX_DQ_72, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "ISDIMM_DQ: Wrong input index specified (%d, max %d)", i_input_index_u8, ISDIMM_MAX_DQ_72); l_type = ISDIMM_DQ; @@ -219,7 +239,13 @@ extern "C" { else if(i_input_type_e == RAW_CDIMM_WR_DQ || i_input_type_e == RAW_CDIMM_RD_DQ) { FAPI_ASSERT(i_input_index_u8 <= CDIMM_MAX_DQ_80, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "CDIMM_DQ: Wrong input index specified (%d, max %d)" , i_input_index_u8, CDIMM_MAX_DQ_80); l_type = CDIMM_DQ; @@ -250,7 +276,13 @@ extern "C" { else if(i_input_type_e == ADDRESS) { FAPI_ASSERT(i_input_index_u8 < MAX_ADDR && (get_port(l_mbapos, i_port_u8)) < 4, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "Wrong input index specified (%d)", i_input_index_u8); l_lane = l_addr_lane[(get_port(l_mbapos, i_port_u8))][i_input_index_u8]; @@ -281,7 +313,13 @@ extern "C" { else if(i_input_type_e == DATA_DISABLE) { FAPI_ASSERT(i_input_index_u8 < MAX_DATA_DISABLE, //5 delay values for data bits disable register - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "Wrong input index specified (%d)", i_input_index_u8); l_block = i_input_index_u8; @@ -317,7 +355,13 @@ extern "C" { else { FAPI_ASSERT(false, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "Wrong input index specified (%d)", i_input_index_u8); } @@ -345,7 +389,13 @@ extern "C" { else if(i_input_type_e == CONTROL) { FAPI_ASSERT(i_input_index_u8 < MAX_CNT && (get_port(l_mbapos, i_port_u8)) < 4, // 20 delay values for Control - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "Wrong input index specified (%d)", i_input_index_u8); l_lane = l_cnt_lane[(get_port(l_mbapos, i_port_u8))][i_input_index_u8]; @@ -374,8 +424,14 @@ extern "C" { else if(i_input_type_e == CLOCK) { - FAPI_ASSERT(i_input_index_u8 <= MAX_CLK && (get_port(l_mbapos, i_port_u8)) < 4, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + FAPI_ASSERT(i_input_index_u8 < MAX_CLK && (get_port(l_mbapos, i_port_u8)) < 4, + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "Wrong input index specified (%d)", i_input_index_u8); l_lane = l_clk_lane[(get_port(l_mbapos, i_port_u8))][i_input_index_u8]; l_adr = l_clk_adr[(get_port(l_mbapos, i_port_u8))][i_input_index_u8]; @@ -502,7 +558,13 @@ extern "C" { else { FAPI_ASSERT(false, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "Wrong input index specified (%d)", i_input_index_u8); } @@ -562,7 +624,13 @@ extern "C" { else { FAPI_ASSERT(false, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "Wrong input index specified (%d)", i_input_index_u8); } @@ -619,7 +687,13 @@ extern "C" { else { FAPI_ASSERT(false, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "Wrong input index specified (%d)", i_input_index_u8); } @@ -675,7 +749,13 @@ extern "C" { else { FAPI_ASSERT(false, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "Wrong input index specified (%d)", i_input_index_u8); } @@ -731,7 +811,13 @@ extern "C" { else { FAPI_ASSERT(false, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "Wrong input index specified (%d)", i_input_index_u8); } @@ -787,7 +873,13 @@ extern "C" { else { FAPI_ASSERT(false, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "Wrong input index specified (%d)", i_input_index_u8); } @@ -843,7 +935,13 @@ extern "C" { else { FAPI_ASSERT(false, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "Wrong input index specified (%d)", i_input_index_u8); } @@ -898,7 +996,13 @@ extern "C" { else { FAPI_ASSERT(false, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "Wrong input index specified (%d)", i_input_index_u8); } @@ -931,7 +1035,13 @@ extern "C" { else { FAPI_ASSERT(false, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "Wrong input index specified (%d)", i_input_index_u8); } @@ -986,7 +1096,13 @@ extern "C" { else { FAPI_ASSERT(false, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "Wrong input index specified (%d)", i_input_index_u8); } @@ -1037,7 +1153,13 @@ extern "C" { else { FAPI_ASSERT(false, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "Wrong input index specified (%d)", i_input_index_u8); } @@ -1092,7 +1214,13 @@ extern "C" { else { FAPI_ASSERT(false, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "Wrong input index specified (%d)", i_input_index_u8); } @@ -1119,7 +1247,13 @@ extern "C" { else { FAPI_ASSERT(false, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "Wrong input type specified (%d)", i_input_type_e); } @@ -1184,7 +1318,13 @@ extern "C" { else { FAPI_ASSERT(false, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_ACCESS_TYPE_PARAM(i_access_type_e). + set_PORT_PARAM(i_port_u8). + set_RANK_PARAM(i_rank_u8). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index_u8), "Wrong input type specified (%d)", i_input_type_e); } @@ -1257,7 +1397,7 @@ extern "C" { uint8_t l_dram_width = 0; uint8_t l_lane = 0; uint8_t l_block = 0; - uint8_t l_lane_dqs[4]; + uint8_t l_lane_dqs[4] = {0}; uint8_t l_index = 0; uint8_t l_dq = 0; uint64_t l_scom_address_64 = 0x0ull; @@ -1274,7 +1414,12 @@ extern "C" { FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_DRAM_WIDTH, i_target_mba, l_dram_width)); FAPI_ASSERT(get_port(l_mbapos, i_port) < 4, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_PORT_PARAM(i_port). + set_RANK_PARAM(i_rank_pair). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index), "Port not valid (%d)", get_port(l_mbapos, i_port)); if(i_input_type_e == RD_DQ || i_input_type_e == WR_DQ || i_input_type_e == RAW_CDIMM_WR_DQ @@ -1312,21 +1457,10 @@ extern "C" { l_dq = l_dqs_dq_lane[get_port(l_mbapos, i_port)][i_input_index]; l_block = l_block_dqs[get_port(l_mbapos, i_port)][i_input_index]; - if(i_verbose) - { - FAPI_INF("l_block=%d", l_block); - FAPI_INF("l_dqs_dq_lane=%d", l_dq); - } - l_input_type = RD_CLK_t; FAPI_TRY(get_address(i_target_mba, i_port, i_rank_pair, l_input_type, l_block, l_lane, l_scom_address_64, l_start_bit, l_len)); - if(i_verbose) - { - FAPI_INF("read clock address=%llx", l_scom_address_64); - } - FAPI_TRY(fapi2::getScom(i_target_mba, l_scom_address_64, l_data_buffer_64)); if(l_dram_width == fapi2::ENUM_ATTR_CEN_EFF_DRAM_WIDTH_X4) @@ -1377,11 +1511,6 @@ extern "C" { l_index++; } - if(i_verbose) - { - FAPI_INF("array is=%d and %d and %d and %d", l_lane_dqs[0], l_lane_dqs[1], l_lane_dqs[2], l_lane_dqs[3]); - } - if(l_dq == 0) { l_lane = l_lane_dqs[0]; @@ -1399,10 +1528,6 @@ extern "C" { l_lane = l_lane_dqs[3]; } - if(i_verbose) - { - FAPI_INF("lane is=%d", l_lane); - } } //end if DRAM_WIDTH_X4 @@ -1617,10 +1742,6 @@ extern "C" { } } // end if dimm is not custom dimm - if(i_verbose) - { - FAPI_INF("lane is=%d", l_lane); - } } // end if dram width is not X4 if(i_input_type_e == WR_DQS) @@ -1644,9 +1765,11 @@ extern "C" { if(l_flag == 0) { - FAPI_ASSERT(false, - fapi2::CEN_CROSS_COUPLED_INVALID_DQS(), - "Invalid DQS and DQS lane=%d", l_lane); + FAPI_ASSERT_NOEXIT(false, + fapi2::CEN_CROSS_COUPLED_INVALID_DQS(). + set_INVALID_DQS(l_lane). + set_MBA_TARGET(i_target_mba), + "Invalid DQS and DQS lane=%d on %s lwm", l_lane, mss::c_str(i_target_mba)); } FAPI_TRY(get_address(i_target_mba, i_port, i_rank_pair, l_input_type, l_block, l_lane, l_scom_address_64, l_start_bit, @@ -1725,6 +1848,7 @@ extern "C" { { FAPI_ASSERT(false, fapi2::CEN_CROSS_COUPLED_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). set_TYPE_PARAM(i_input_type_e), "Wrong input type specified (%d)", i_input_type_e); } @@ -1805,7 +1929,11 @@ extern "C" { if(i_port > 1) { FAPI_ASSERT(false, - fapi2::CEN_ROSETTA_MAP_INVALID_INPUT(), + fapi2::CEN_ROSETTA_MAP_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_PORT_PARAM(i_port). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index), "Wrong port specified (%d)", i_port); } @@ -1814,6 +1942,7 @@ extern "C" { { FAPI_ASSERT(false, fapi2::CEN_ROSETTA_MAP_BAD_MBA_POS(). + set_MBA_TARGET(i_target_mba). set_MBA_POS(l_mbapos), "Bad position from ATTR_CHIP_UNIT_POS (%d)", l_mbapos); @@ -1962,7 +2091,11 @@ extern "C" { else { FAPI_ASSERT(false, - fapi2::CEN_ROSETTA_MAP_INVALID_INPUT(), + fapi2::CEN_ROSETTA_MAP_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_PORT_PARAM(i_port). + set_TYPE_PARAM(i_input_type_e). + set_INDEX_PARAM(i_input_index), "Wrong input type specified (%d)", i_input_type_e); } @@ -2713,7 +2846,10 @@ extern "C" { } FAPI_ASSERT( i_port < 2, - fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(), + fapi2::CEN_MSS_ACCESS_DELAY_REG_INVALID_INPUT(). + set_MBA_TARGET(i_target_mba). + set_PORT_PARAM(i_port). + set_RANK_PARAM(i_rank), "Port shall not be greater than 1.\n"); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_PRIMARY_RANK_GROUP0, i_target_mba, l_temp_rank)); diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_generic_shmoo.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_generic_shmoo.C index 049d028b6..1db9e4476 100755 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_generic_shmoo.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_generic_shmoo.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -484,15 +484,15 @@ extern "C" uint8_t l_max_byte = 10; struct subtest_info l_sub_info[30]; - - FAPI_TRY(schmoo_setup_mcb(i_target)); + FAPI_DBG("%s: enter sanity check", mss::c_str(i_target)); + FAPI_TRY(schmoo_setup_mcb(i_target), "Sanity Check failed schmoo_setup_mcb"); FAPI_DBG("%s: starting mcbist now", mss::c_str(i_target)); - FAPI_TRY(start_mcb(i_target)); + FAPI_TRY(start_mcb(i_target), "Sanity Check failed start_mcb"); FAPI_DBG("%s: polling mcbist now", mss::c_str(i_target)); FAPI_TRY(poll_mcb(i_target, &l_mcb_status, l_sub_info, 1), "generic_shmoo::do_mcbist_test: POLL MCBIST failed !!"); FAPI_DBG("%s: checking error map ", mss::c_str(i_target)); FAPI_TRY(mcb_error_map(i_target, mcbist_error_map, l_CDarray0, l_CDarray1, - count_bad_dq)); + count_bad_dq), "Failed mcb_error_map"); for (l_p = 0; l_p < MAX_PORT; l_p++) { @@ -4583,7 +4583,7 @@ extern "C" FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_MCBIST_TEST_TYPE, i_target, l_testtype)); } - FAPI_TRY(setup_mcbist(i_target, i_mcbbytemask1, 0, 0x0ull , l_sub_info, l_str_cust_addr)); + FAPI_TRY(setup_mcbist(i_target, i_mcbbytemask1, 0, 0x0ull , l_sub_info, l_str_cust_addr), "Failed setup_mcbist"); fapi_try_exit: return fapi2::current_err; } diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist.C index f992af05c..b5afb976b 100755 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -84,10 +84,10 @@ extern "C" } FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - W, 0, SF, FIX, 0, DEFAULT, FIX_ADDR, 0, 0, 1, l_sub_info)); + W, 0, SF, FIX, 0, DEFAULT, FIX_ADDR, 0, 0, 1, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - R, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 1, 1, 1, l_sub_info)); + R, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 1, 1, 1, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); } else if (i_test_type == MEMWRITE) @@ -98,7 +98,7 @@ extern "C" } FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - W, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 0, 0, 0, l_sub_info)); + W, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 0, 0, 0, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); } else if (i_test_type == MEMREAD) @@ -109,7 +109,7 @@ extern "C" } FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - R, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 0, 0, 0, l_sub_info)); + R, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 0, 0, 0, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); } else if (i_test_type == SIMPLE_FIX) { @@ -119,24 +119,24 @@ extern "C" } FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - W, 0, SF, FIX, 0, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info)); + W, 0, SF, FIX, 0, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - R, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info)); + R, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); l_done_bit = 1; FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_MCBIST_ADDR_BANK, i_target_mba, l_done_bit)); FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - R, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 2, 2, 4, l_sub_info)); + R, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 2, 2, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - OPER_RAND, 0, RF, FIX, 1, DEFAULT, FIX_ADDR, 3, 3, 4, l_sub_info)); + OPER_RAND, 0, RF, FIX, 1, DEFAULT, FIX_ADDR, 3, 3, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR1Q, - RW, 4, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 4, 4, l_sub_info)); + RW, 4, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 4, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); } else if (i_test_type == SIMPLE_RAND) { @@ -146,7 +146,7 @@ extern "C" } FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - WR, 0, SF, DATA_RF, 1, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info)); + WR, 0, SF, DATA_RF, 1, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); l_done_bit = 1; @@ -154,17 +154,17 @@ extern "C" FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - R, 1, SF, DATA_RF, 0, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info)); + R, 1, SF, DATA_RF, 0, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - W, 0, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 2, 2, 4, l_sub_info)); + W, 0, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 2, 2, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - R, 0, RF, DATA_RF, 1, DEFAULT, FIX_ADDR, 3, 3, 4, l_sub_info)); + R, 0, RF, DATA_RF, 1, DEFAULT, FIX_ADDR, 3, 3, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR1Q, - RW, 4, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 4, 4, l_sub_info)); + RW, 4, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 4, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); } else if (i_test_type == WR_ONLY) @@ -175,10 +175,10 @@ extern "C" } FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - W, 0, SF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info)); + W, 0, SF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - R, 0, SF, DATA_RF, 1, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info)); + R, 0, SF, DATA_RF, 1, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); l_done_bit = 1; @@ -186,14 +186,14 @@ extern "C" FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - W, 0, RF, FIX, 0, DEFAULT, FIX_ADDR, 2, 2, 4, l_sub_info)); + W, 0, RF, FIX, 0, DEFAULT, FIX_ADDR, 2, 2, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - OPER_RAND, 0, RF, FIX, 1, DEFAULT, FIX_ADDR, 3, 3, 4, l_sub_info)); + OPER_RAND, 0, RF, FIX, 1, DEFAULT, FIX_ADDR, 3, 3, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR1Q, - RW, 4, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 4, 4, l_sub_info)); + RW, 4, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 4, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); } else if (i_test_type == W_ONLY) @@ -204,7 +204,7 @@ extern "C" } FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - W, 0, SF, DATA_RF, 1, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info)); + W, 0, SF, DATA_RF, 1, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); l_done_bit = 1; @@ -212,18 +212,18 @@ extern "C" FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - R, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info)); + R, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, W, 0, RF, FIX, 0, DEFAULT, FIX_ADDR, 2, 2, 4, - l_sub_info)); + l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - OPER_RAND, 0, RF, FIX, 1, DEFAULT, FIX_ADDR, 3, 3, 4, l_sub_info)); + OPER_RAND, 0, RF, FIX, 1, DEFAULT, FIX_ADDR, 3, 3, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR1Q, - RW, 4, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 4, 4, l_sub_info)); + RW, 4, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 4, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); } else if (i_test_type == R_ONLY) @@ -234,7 +234,7 @@ extern "C" } FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - R, 0, SF, DATA_RF, 1, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info)); + R, 0, SF, DATA_RF, 1, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); l_done_bit = 1; @@ -242,17 +242,17 @@ extern "C" FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - GOTO, 0, SF, FIX, 0, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info)); + GOTO, 0, SF, FIX, 0, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - W, 0, RF, FIX, 0, DEFAULT, FIX_ADDR, 2, 2, 4, l_sub_info)); + W, 0, RF, FIX, 0, DEFAULT, FIX_ADDR, 2, 2, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - OPER_RAND, 0, RF, FIX, 1, DEFAULT, FIX_ADDR, 3, 3, 4, l_sub_info)); + OPER_RAND, 0, RF, FIX, 1, DEFAULT, FIX_ADDR, 3, 3, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR1Q, - RW, 4, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 4, 4, l_sub_info)); + RW, 4, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 4, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); } else if (i_test_type == SIMPLE_FIX_RF) @@ -260,10 +260,10 @@ extern "C" FAPI_DBG("%s:Current MCBIST TESTTYPE : SIMPLE_FIX_RF ", mss::c_str(i_target_mba)); FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - W, 0, SF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info)); + W, 0, SF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); FAPI_TRY(mcb_write_test_mem(i_target_mba, CEN_MBA_MCBMR0Q, - R, 0, SF, DATA_RF, 1, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info)); + R, 0, SF, DATA_RF, 1, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info), "cfg_mcb_test_mem failed mcb_write_test_mem"); l_done_bit = 1; FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_MCBIST_ADDR_BANK, i_target_mba, l_done_bit)); @@ -414,16 +414,6 @@ extern "C" const auto i_target_centaur = i_target_mba.getParent<fapi2::TARGET_TYPE_MEMBUF_CHIP>(); - if (l_print == 0) - { - FAPI_DBG("Error in getting parent chip!"); - } - - if (l_print == 0) - { - FAPI_DBG("Function cfg_mcb_dgen"); - } - //Read MBA position attribute 0 - MBA01 1 - MBA23 FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_mba, l_mbaPosition)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MCBIST_PRINTING_DISABLE, i_target_mba, l_print)); diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist_common.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist_common.C index 0642e337b..425aa18d4 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist_common.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist_common.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -110,7 +110,7 @@ extern "C" mss_conversion_testtype(i_target_mba, i_mcbtest, i_mcbtest1); mss_conversion_data(i_target_mba, i_mcbpatt, i_mcbpatt1); - FAPI_TRY(mcb_reset_trap(i_target_mba)); + FAPI_TRY(mcb_reset_trap(i_target_mba), "Failed mcb_reset_trap"); //should set attr for this 1st 8 or last 8 FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MCBIST_ERROR_CAPTURE, i_target_mba, l_bit32)); @@ -187,16 +187,16 @@ extern "C" FAPI_DBG("%s:steer mode is not enabled", mss::c_str(i_target_mba)); } - FAPI_TRY(cfg_mcb_test_mem(i_target_mba, i_mcbtest1, i_sub_info)); + FAPI_TRY(cfg_mcb_test_mem(i_target_mba, i_mcbtest1, i_sub_info), "Failed cfg_mcb_test_mem"); - FAPI_TRY(cfg_mcb_dgen(i_target_mba, i_mcbpatt1, i_mcbrotate, i_mcbrotdata)); + FAPI_TRY(cfg_mcb_dgen(i_target_mba, i_mcbpatt1, i_mcbrotate, i_mcbrotdata), "Failed cfg_mcb_dgen"); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MCBIST_ADDR_MODES, i_target_mba, l_new_addr)); if (l_new_addr != 0) { - FAPI_TRY(address_generation(i_target_mba, i_str_cust_addr)); + FAPI_TRY(address_generation(i_target_mba, i_str_cust_addr), "Failed address_generation"); } FAPI_INF( "+++ Enabling Refresh +++"); @@ -210,7 +210,7 @@ extern "C" if (i_mcbbytemask != NONE) { - FAPI_TRY(cfg_byte_mask(i_target_mba)); + FAPI_TRY(cfg_byte_mask(i_target_mba), "Failed cfg_byte_mask"); } @@ -812,8 +812,6 @@ extern "C" uint8_t o_val = 0; uint8_t i_byte1 = 0; uint8_t i_nibble1 = 0; - uint8_t l_zmode_port = 0; - uint8_t l_zmode = 0; uint8_t l_index = 0; uint8_t l_i = 0; uint8_t l_number = 0; @@ -935,15 +933,7 @@ extern "C" { for (l_nibble = 0; l_nibble < MAX_NIBBLES_PER_BYTE; l_nibble++) { - if (l_port == 0 && l_zmode == 1 && l_zmode_port == 1) - { - continue; - } - else if (l_port == 1 && l_zmode == 1 && l_zmode_port == 0) - { - continue; - } - else if (l_port == 0) + if (l_port == 0) { l_index0 = (l_rank * 20) + (l_byte * 2) + l_nibble; l_index1 = l_index0; @@ -1476,6 +1466,8 @@ extern "C" } } // for nibble } // for byte + + FAPI_DBG("%s", l_str); } // for rank } // ranks found } // for each port @@ -1547,7 +1539,7 @@ extern "C" if (l_done_bit == 1) { - return fapi2::FAPI2_RC_FALSE; + return fapi2::current_err; } i_sub_info[i_testnumber1].l_operation_type = l_operation_type; diff --git a/src/import/chips/centaur/procedures/xml/attribute_info/centaur_ec_attributes.xml b/src/import/chips/centaur/procedures/xml/attribute_info/centaur_ec_attributes.xml index 9f40aae51..80656eb1d 100644 --- a/src/import/chips/centaur/procedures/xml/attribute_info/centaur_ec_attributes.xml +++ b/src/import/chips/centaur/procedures/xml/attribute_info/centaur_ec_attributes.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016,2017 --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2018 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -345,7 +345,6 @@ Controls the ddr_phy_reset procedure. When set to TRUE, the procedure will cont </attribute> --> -<!-- <attribute> <id>ATTR_CEN_CENTAUR_EC_FEATURE_MCBIST_RANDOM_ADDRESS</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -362,7 +361,6 @@ Controls the ddr_phy_reset procedure. When set to TRUE, the procedure will cont </chip> </chipEcFeature> </attribute> ---> <!-- <attribute> diff --git a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml index 6744193b7..012be2b73 100644 --- a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml +++ b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2012,2017 --> +<!-- Contributors Listed Below - COPYRIGHT 2012,2018 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -102,7 +102,6 @@ firmware notes: none</description> <persistRuntime/> </attribute> -<!-- <attribute> <id>ATTR_CEN_MSS_FREQ_BIAS_PERCENTAGE</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -118,7 +117,6 @@ Set by: PLL settings written by Dave Cadigan</description> <odmChangeable/> <persistRuntime/> </attribute> ---> <attribute> <id>ATTR_CEN_MSS_VREF_CAL_CNTL</id> diff --git a/src/import/chips/centaur/procedures/xml/error_info/p9c_mss_access_delay_reg_errors.xml b/src/import/chips/centaur/procedures/xml/error_info/p9c_mss_access_delay_reg_errors.xml index c5b40c2c7..a1b46652a 100644 --- a/src/import/chips/centaur/procedures/xml/error_info/p9c_mss_access_delay_reg_errors.xml +++ b/src/import/chips/centaur/procedures/xml/error_info/p9c_mss_access_delay_reg_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016,2017 --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2018 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -87,6 +87,7 @@ The cross_coupled utility function received a bad input type parameter </description> <ffdc>TYPE_PARAM</ffdc> + <ffdc>MBA_TARGET</ffdc> <callout> <procedure>CODE</procedure> <priority>HIGH</priority> @@ -100,6 +101,7 @@ The cross_coupled utility function received a invalid DQS </description> <ffdc>INVALID_DQS</ffdc> + <ffdc>MBA_TARGET</ffdc> <callout> <procedure>CODE</procedure> <priority>HIGH</priority> |