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| author | Zane Shelley <zshelle@us.ibm.com> | 2018-04-24 11:26:06 -0500 |
|---|---|---|
| committer | Zane C. Shelley <zshelle@us.ibm.com> | 2018-04-27 21:29:49 -0400 |
| commit | ed55b087c5b070c99bdd4cb379e1291282d89897 (patch) | |
| tree | c0877310845d8fef26d9fe1229c0a45105966300 | |
| parent | 06d556e9b03c86d451b3a383f12834cb88302ae1 (diff) | |
| download | talos-hostboot-ed55b087c5b070c99bdd4cb379e1291282d89897.tar.gz talos-hostboot-ed55b087c5b070c99bdd4cb379e1291282d89897.zip | |
PRD: single bit analysis support for MEMBUF target
Change-Id: I9203af796be7f832d1aac1ed674252cb2df29e66
RTC: 187481
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57750
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com>
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57884
CI-Ready: Zane C. Shelley <zshelle@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
12 files changed, 2283 insertions, 2530 deletions
diff --git a/src/usr/diag/prdf/common/plat/cen/cen_centaur.rule b/src/usr/diag/prdf/common/plat/cen/cen_centaur.rule index f75ff5791..240615c62 100644 --- a/src/usr/diag/prdf/common/plat/cen/cen_centaur.rule +++ b/src/usr/diag/prdf/common/plat/cen/cen_centaur.rule @@ -790,8 +790,12 @@ rule rNEST_CHIPLET_FIR (NEST_CHIPLET_RE_FIR >> 2) & ~NEST_CHIPLET_FIR_MASK & `1fffffffffffffff`; }; -group gNEST_CHIPLET_FIR filter singlebit +group gNEST_CHIPLET_FIR filter priority( 3, 6, 5, 7 ) { + # NOTE: The MBIFIR must be analyzed before the DMIFIR and both the MBIFIR + # and DMIFIR must be analyzed before the MBSFIR. All other FIRs will be + # analyzed in order. + /** NEST_CHIPLET_FIR[3] * Attention from NEST_LFIR */ @@ -947,7 +951,8 @@ rule rDMIFIR DMIFIR & ~DMIFIR_MASK & ~DMIFIR_ACT0 & DMIFIR_ACT1; }; -group gDMIFIR filter singlebit, cs_root_cause( 10 ) +group gDMIFIR filter priority( 10, 2, 11, 12, 9 ), + cs_root_cause( 10 ) { /** DMIFIR[0] * RX invalid state or parity error @@ -1043,7 +1048,8 @@ rule rMBIFIR MBIFIR & ~MBIFIR_MASK & ~MBIFIR_ACT0 & MBIFIR_ACT1; }; -group gMBIFIR filter singlebit, cs_root_cause( 0, 6, 8, 9 ) +group gMBIFIR filter priority( 8, 9, 19, 20, 6, 0, 16, 5, 10 ), + cs_root_cause( 0, 6, 8, 9, 19, 20 ) { /** MBIFIR[0] * Replay Timeout @@ -1078,7 +1084,7 @@ group gMBIFIR filter singlebit, cs_root_cause( 0, 6, 8, 9 ) /** MBIFIR[6] * Replay Buffer ECC UE */ - (rMBIFIR, bit(6)) ? self_th_1; + (rMBIFIR, bit(6)) ? self_th_1_UERE; /** MBIFIR[7] * MBI State Machine Timeout @@ -1088,12 +1094,12 @@ group gMBIFIR filter singlebit, cs_root_cause( 0, 6, 8, 9 ) /** MBIFIR[8] * MBI Internal Control Parity Error */ - (rMBIFIR, bit(8)) ? self_th_1; + (rMBIFIR, bit(8)) ? self_th_1_UERE; /** MBIFIR[9] * MBI Data Flow Parity Error */ - (rMBIFIR, bit(9)) ? self_th_1; + (rMBIFIR, bit(9)) ? self_th_1_UERE; /** MBIFIR[10] * CRC Performance Degradation @@ -1143,7 +1149,7 @@ group gMBIFIR filter singlebit, cs_root_cause( 0, 6, 8, 9 ) /** MBIFIR[19] * MBICFG parity error */ - (rMBIFIR, bit(19)) ? self_th_1; + (rMBIFIR, bit(19)) ? self_th_1_UERE; /** MBIFIR[20] * Replay Buffer Overrun @@ -1194,12 +1200,12 @@ group gMBSFIR filter singlebit, cs_root_cause( 0, 1, 2, 4, 6, 8, 10, 13, 16, 18, /** MBSFIR[1] * INT_PROTOCOL_ERROR */ - (rMBSFIR, bit(1)) ? self_th_1; + (rMBSFIR, bit(1)) ? self_th_1_UERE; /** MBSFIR[2] * INVALID_ADDRESS_ERROR */ - (rMBSFIR, bit(2)) ? level2_th_1; + (rMBSFIR, bit(2)) ? level2_th_1_UERE; /** MBSFIR[3] * EXTERNAL_TIMEOUT @@ -1219,7 +1225,7 @@ group gMBSFIR filter singlebit, cs_root_cause( 0, 1, 2, 4, 6, 8, 10, 13, 16, 18, /** MBSFIR[6] * INT_BUFFER_UE */ - (rMBSFIR, bit(6)) ? self_th_1; + (rMBSFIR, bit(6)) ? self_th_1_UERE; /** MBSFIR[7] * INT_BUFFER_SUE @@ -1229,7 +1235,7 @@ group gMBSFIR filter singlebit, cs_root_cause( 0, 1, 2, 4, 6, 8, 10, 13, 16, 18, /** MBSFIR[8] * INT_PARITY_ERROR */ - (rMBSFIR, bit(8)) ? self_th_1; + (rMBSFIR, bit(8)) ? self_th_1_UERE; /** MBSFIR[9] * CACHE_SRW_CE @@ -1264,12 +1270,12 @@ group gMBSFIR filter singlebit, cs_root_cause( 0, 1, 2, 4, 6, 8, 10, 13, 16, 18, /** MBSFIR[15] * DIR_CE */ - (rMBSFIR, bit(15)) ? TBDDefaultCallout; + (rMBSFIR, bit(15)) ? l4_th_32perDay; /** MBSFIR[16] * DIR_UE */ - (rMBSFIR, bit(16)) ? TBDDefaultCallout; + (rMBSFIR, bit(16)) ? l4_th_1_UERE; /** MBSFIR[17] * DIR_MEMBER_DELETED @@ -1279,17 +1285,17 @@ group gMBSFIR filter singlebit, cs_root_cause( 0, 1, 2, 4, 6, 8, 10, 13, 16, 18, /** MBSFIR[18] * DIR_ALL_MEMBERS_DELETED */ - (rMBSFIR, bit(18)) ? TBDDefaultCallout; + (rMBSFIR, bit(18)) ? l4_th_1_UERE; /** MBSFIR[19] * LRU_ERROR */ - (rMBSFIR, bit(19)) ? TBDDefaultCallout; + (rMBSFIR, bit(19)) ? l4_th_32perDay; /** MBSFIR[20] * EDRAM ERROR */ - (rMBSFIR, bit(20)) ? TBDDefaultCallout; + (rMBSFIR, bit(20)) ? l4_th_1_UERE; /** MBSFIR[21] * EMERGENCY_THROTTLE_SET @@ -1324,7 +1330,7 @@ group gMBSFIR filter singlebit, cs_root_cause( 0, 1, 2, 4, 6, 8, 10, 13, 16, 18, /** MBSFIR[27] * SRB_BUFFER_UE */ - (rMBSFIR, bit(27)) ? self_th_1; + (rMBSFIR, bit(27)) ? self_th_1_UERE; /** MBSFIR[28] * SRB_BUFFER_SUE @@ -1339,7 +1345,7 @@ group gMBSFIR filter singlebit, cs_root_cause( 0, 1, 2, 4, 6, 8, 10, 13, 16, 18, /** MBSFIR[30] * PROXIMAL_CE_UE */ - (rMBSFIR, bit(30)) ? TBDDefaultCallout; + (rMBSFIR, bit(30)) ? l4_th_1_UERE; /** MBSFIR[31:32] * Spare @@ -1414,7 +1420,7 @@ rule rMBSECCFIR_0 MBSECCFIR_0 & ~MBSECCFIR_0_MASK & ~MBSECCFIR_0_ACT0 & MBSECCFIR_0_ACT1; }; -group gMBSECCFIR_0 filter singlebit, cs_root_cause +group gMBSECCFIR_0 filter singlebit, cs_root_cause( 19, 44, 47, 49 ) { /** MBSECCFIR_0[0] * Memory chip mark on rank 0 @@ -1534,7 +1540,7 @@ group gMBSECCFIR_0 filter singlebit, cs_root_cause /** MBSECCFIR_0[44] * Memory RCD parity error */ - (rMBSECCFIR_0, bit(44)) ? self_th_1; # CUMULUS_10 + (rMBSECCFIR_0, bit(44)) ? self_th_1_UERE; # CUMULUS_10 /** MBSECCFIR_0[45] * Maintenance RCD parity error @@ -1544,32 +1550,32 @@ group gMBSECCFIR_0 filter singlebit, cs_root_cause /** MBSECCFIR_0[46] * Recoverable config reg PE */ - (rMBSECCFIR_0, bit(46)) ? TBDDefaultCallout; + (rMBSECCFIR_0, bit(46)) ? mba0_th_1; /** MBSECCFIR_0[47] * Unrecoverable config reg PE */ - (rMBSECCFIR_0, bit(47)) ? TBDDefaultCallout; + (rMBSECCFIR_0, bit(47)) ? mba0_th_1_UERE; /** MBSECCFIR_0[48] * Maskable config reg PE */ - (rMBSECCFIR_0, bit(48)) ? TBDDefaultCallout; + (rMBSECCFIR_0, bit(48)) ? threshold_and_mask_mba0; /** MBSECCFIR_0[49] * ECC datapath parity error */ - (rMBSECCFIR_0, bit(49)) ? TBDDefaultCallout; + (rMBSECCFIR_0, bit(49)) ? mba0_th_1_UERE; /** MBSECCFIR_0[50] * internal scom error */ - (rMBSECCFIR_0, bit(50)) ? TBDDefaultCallout; + (rMBSECCFIR_0, bit(50)) ? threshold_and_mask_mba0; /** MBSECCFIR_0[51] * internal scom error clone */ - (rMBSECCFIR_0, bit(51)) ? TBDDefaultCallout; + (rMBSECCFIR_0, bit(51)) ? threshold_and_mask_mba0; }; @@ -1585,7 +1591,7 @@ rule rMBSECCFIR_1 MBSECCFIR_1 & ~MBSECCFIR_1_MASK & ~MBSECCFIR_1_ACT0 & MBSECCFIR_1_ACT1; }; -group gMBSECCFIR_1 filter singlebit +group gMBSECCFIR_1 filter singlebit, cs_root_cause( 19, 44, 47, 49 ) { /** MBSECCFIR_1[0] * Memory chip mark on rank 0 @@ -1705,7 +1711,7 @@ group gMBSECCFIR_1 filter singlebit /** MBSECCFIR_1[44] * Memory RCD parity error */ - (rMBSECCFIR_1, bit(44)) ? self_th_1; # CUMULUS_10 + (rMBSECCFIR_1, bit(44)) ? self_th_1_UERE; # CUMULUS_10 /** MBSECCFIR_1[45] * Maintenance RCD parity error @@ -1715,32 +1721,32 @@ group gMBSECCFIR_1 filter singlebit /** MBSECCFIR_1[46] * Recoverable config reg PE */ - (rMBSECCFIR_1, bit(46)) ? TBDDefaultCallout; + (rMBSECCFIR_1, bit(46)) ? mba1_th_1; /** MBSECCFIR_1[47] * Unrecoverable config reg PE */ - (rMBSECCFIR_1, bit(47)) ? TBDDefaultCallout; + (rMBSECCFIR_1, bit(47)) ? mba1_th_1_UERE; /** MBSECCFIR_1[48] * Maskable config reg PE */ - (rMBSECCFIR_1, bit(48)) ? TBDDefaultCallout; + (rMBSECCFIR_1, bit(48)) ? threshold_and_mask_mba1; /** MBSECCFIR_1[49] * ECC datapath parity error */ - (rMBSECCFIR_1, bit(49)) ? TBDDefaultCallout; + (rMBSECCFIR_1, bit(49)) ? mba1_th_1_UERE; /** MBSECCFIR_1[50] * internal scom error */ - (rMBSECCFIR_1, bit(50)) ? TBDDefaultCallout; + (rMBSECCFIR_1, bit(50)) ? threshold_and_mask_mba1; /** MBSECCFIR_1[51] * internal scom error clone */ - (rMBSECCFIR_1, bit(51)) ? TBDDefaultCallout; + (rMBSECCFIR_1, bit(51)) ? threshold_and_mask_mba1; }; @@ -1756,7 +1762,7 @@ rule rSCACFIR SCACFIR & ~SCACFIR_MASK & ~SCACFIR_ACT0 & SCACFIR_ACT1; }; -group gSCACFIR filter singlebit, cs_root_cause +group gSCACFIR filter singlebit, cs_root_cause( 25, 26 ) { /** SCACFIR[0] * I2CM(0) Invalid Address @@ -1871,12 +1877,12 @@ group gSCACFIR filter singlebit, cs_root_cause /** SCACFIR[25] * Parity Error on Internal Register */ - (rSCACFIR, bit(25)) ? self_th_1; + (rSCACFIR, bit(25)) ? self_th_1_UERE; /** SCACFIR[26] * Parity Error on Pib Target Register */ - (rSCACFIR, bit(26)) ? self_th_1; + (rSCACFIR, bit(26)) ? self_th_1_UERE; /** SCACFIR[27:31] * Reserved @@ -1922,17 +1928,17 @@ rule rMCBISTFIR_0 MCBISTFIR_0 & ~MCBISTFIR_0_MASK & ~MCBISTFIR_0_ACT0 & MCBISTFIR_0_ACT1; }; -group gMCBISTFIR_0 filter singlebit, cs_root_cause +group gMCBISTFIR_0 filter singlebit, cs_root_cause( 0, 1 ) { /** MCBISTFIR_0[0] * SCOM Parity Errors */ - (rMCBISTFIR_0, bit(0)) ? TBDDefaultCallout; + (rMCBISTFIR_0, bit(0)) ? mba0_th_1_UERE; /** MCBISTFIR_0[1] * MBX parity errors */ - (rMCBISTFIR_0, bit(1)) ? TBDDefaultCallout; + (rMCBISTFIR_0, bit(1)) ? mba0_th_1_UERE; /** MCBISTFIR_0[2] * DRAM event 0 error @@ -1952,12 +1958,12 @@ group gMCBISTFIR_0 filter singlebit, cs_root_cause /** MCBISTFIR_0[15] * SCOM FIR error */ - (rMCBISTFIR_0, bit(15)) ? TBDDefaultCallout; + (rMCBISTFIR_0, bit(15)) ? threshold_and_mask_mba0; /** MCBISTFIR_0[16] * SCOM FIR error clone */ - (rMCBISTFIR_0, bit(16)) ? TBDDefaultCallout; + (rMCBISTFIR_0, bit(16)) ? threshold_and_mask_mba0; }; @@ -1973,17 +1979,17 @@ rule rMCBISTFIR_1 MCBISTFIR_1 & ~MCBISTFIR_1_MASK & ~MCBISTFIR_1_ACT0 & MCBISTFIR_1_ACT1; }; -group gMCBISTFIR_1 filter singlebit, cs_root_cause +group gMCBISTFIR_1 filter singlebit, cs_root_cause( 0, 1 ) { /** MCBISTFIR_1[0] * SCOM Parity Errors */ - (rMCBISTFIR_1, bit(0)) ? TBDDefaultCallout; + (rMCBISTFIR_1, bit(0)) ? mba1_th_1_UERE; /** MCBISTFIR_1[1] * MBX parity errors */ - (rMCBISTFIR_1, bit(1)) ? TBDDefaultCallout; + (rMCBISTFIR_1, bit(1)) ? mba1_th_1_UERE; /** MCBISTFIR_1[2] * DRAM event 0 error @@ -2003,12 +2009,12 @@ group gMCBISTFIR_1 filter singlebit, cs_root_cause /** MCBISTFIR_1[15] * SCOM FIR error */ - (rMCBISTFIR_1, bit(15)) ? TBDDefaultCallout; + (rMCBISTFIR_1, bit(15)) ? threshold_and_mask_mba1; /** MCBISTFIR_1[16] * SCOM FIR error clone */ - (rMCBISTFIR_1, bit(16)) ? TBDDefaultCallout; + (rMCBISTFIR_1, bit(16)) ? threshold_and_mask_mba1; }; diff --git a/src/usr/diag/prdf/common/plat/cen/cen_centaur_actions.rule b/src/usr/diag/prdf/common/plat/cen/cen_centaur_actions.rule index 9ee085a9b..47a75bfad 100644 --- a/src/usr/diag/prdf/common/plat/cen/cen_centaur_actions.rule +++ b/src/usr/diag/prdf/common/plat/cen/cen_centaur_actions.rule @@ -23,9 +23,42 @@ # # IBM_PROLOG_END_TAG +/** Callout the connected MBA 0 */ +actionclass calloutMba0 { callout(connected(TYPE_MBA, 0), MRU_MED); }; + +/** Callout the connected MBA 1 */ +actionclass calloutMba1 { callout(connected(TYPE_MBA, 1), MRU_MED); }; + +/** Callout the connected MBA 0, threshold 1 */ +actionclass mba0_th_1 { calloutMba0; threshold1; }; + +/** Callout the connected MBA 1, threshold 1 */ +actionclass mba1_th_1 { calloutMba1; threshold1; }; + +/** Callout the connected MBA 0, threshold 1, SUE source */ +actionclass mba0_th_1_UERE { mba0_th_1; SueSource; }; + +/** Callout the connected MBA 1, threshold 1, SUE source */ +actionclass mba1_th_1_UERE { mba1_th_1; SueSource; }; + +/** Threshold and mask policy (MBA 0) */ +actionclass threshold_and_mask_mba0 { calloutMba0; threshold_and_mask; }; + +/** Threshold and mask policy (MBA 1) */ +actionclass threshold_and_mask_mba1 { calloutMba1; threshold_and_mask; }; + /** Callout the connected L4 */ actionclass calloutL4 { callout(connected(TYPE_L4), MRU_MED); }; +/** Callout the connected L4, threshold 1 */ +actionclass l4_th_1 { calloutL4; threshold1; }; + +/** Callout the connected L4, threshold 32/day */ +actionclass l4_th_32perDay { calloutL4; threshold32pday; }; + +/** Callout the connected L4, threshold 1, SUE source */ +actionclass l4_th_1_UERE { l4_th_1; SueSource; }; + /** L4 cache SRW CE */ actionclass l4_cache_srw_ce { diff --git a/src/usr/diag/prdf/common/plat/mem/prdfMemUtils.C b/src/usr/diag/prdf/common/plat/mem/prdfMemUtils.C index 9b715c8a7..7f47b5d9c 100755 --- a/src/usr/diag/prdf/common/plat/mem/prdfMemUtils.C +++ b/src/usr/diag/prdf/common/plat/mem/prdfMemUtils.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2017 */ +/* Contributors Listed Below - COPYRIGHT 2013,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -648,7 +648,7 @@ int32_t chnlCsCleanup( ExtensibleChip *i_mbChip, l_tpfirmask = i_mbChip->getRegister("TP_CHIPLET_FIR_MASK"); l_nestfirmask = i_mbChip->getRegister("NEST_CHIPLET_FIR_MASK"); l_memfirmask = i_mbChip->getRegister("MEM_CHIPLET_FIR_MASK"); - l_memspamask = i_mbChip->getRegister("MEM_CHIPLET_SPA_MASK"); + l_memspamask = i_mbChip->getRegister("MEM_CHIPLET_SPA_FIR_MASK"); l_tpfirmask->setAllBits(); o_rc |= l_tpfirmask->Write(); l_nestfirmask->setAllBits(); o_rc |= l_nestfirmask->Write(); diff --git a/src/usr/diag/prdf/common/plat/pegasus/Membuf.rule b/src/usr/diag/prdf/common/plat/pegasus/Membuf.rule index f99345328..b499a2981 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/Membuf.rule +++ b/src/usr/diag/prdf/common/plat/pegasus/Membuf.rule @@ -5,7 +5,9 @@ # # OpenPOWER HostBoot Project # -# COPYRIGHT International Business Machines Corp. 2012,2014 +# Contributors Listed Below - COPYRIGHT 2012,2018 +# [+] International Business Machines Corp. +# # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -21,27 +23,11 @@ # # IBM_PROLOG_END_TAG -################################################################################ -# -# Scope: -# Registers and actions for the following chiplets: -# -# Chiplet Register Adddresses Description -# ======= ======================= ============================================ -# TP 0x01000000 - 0x01FFFFFF TP pervasive logic -# NEST 0x02000000 - 0x02FFFFFF NEST pervasive logic -# MEM 0x03000000 - 0x03FFFFFF MEM pervasive logic, note that this does -# include the SCOM addresses characterized by -# the MBA target. See Mba.rule for those -# address ranges. -# -################################################################################ - -chip Membuf +chip cen_centaur { - name "Centaur Chip"; + name "Centaur chip"; targettype TYPE_MEMBUF; - sigoff 0x8000; + sigoff 0x9000; dump DUMP_CONTENT_HW; scomlen 64; @@ -62,82 +48,627 @@ chip Membuf ############################################################################# ############################################################################ - # Global Broadcast Registers + # Global Attention FIR ############################################################################ register GLOBAL_CS_FIR { name "Global Checkstop Attention FIR"; - scomaddr 0x570F001C; + scomaddr 0x500F001C; capture group default; }; register GLOBAL_RE_FIR { name "Global Recoverable Attention FIR"; - scomaddr 0x570F001B; + scomaddr 0x500F001B; capture group default; }; - register GLOBAL_SPA + ############################################################################ + # Global Special Attention FIR + ############################################################################ + + register GLOBAL_SPA_FIR { name "Global Special Attention FIR"; - scomaddr 0x570F001A; + scomaddr 0x500F001A; capture group default; }; -# Import all of the chiplet registers -.include "Membuf_regs_TP.rule" -.include "Membuf_regs_NEST.rule" -.include "Membuf_regs_MEM.rule" + ############################################################################ + # TP Chiplet FIR + ############################################################################ + + register TP_CHIPLET_CS_FIR + { + name "TP Chiplet Checkstop FIR"; + scomaddr 0x01040000; + capture group default; + capture group FirRegs; + }; + + register TP_CHIPLET_RE_FIR + { + name "TP Chiplet Recoverable FIR"; + scomaddr 0x01040001; + capture group default; + capture group FirRegs; + }; + + register TP_CHIPLET_FIR_MASK + { + name "TP Chiplet FIR MASK"; + scomaddr 0x01040002; + capture group default; + capture group FirRegs; + }; + + ############################################################################ + # Centaur chip TP_LFIR + ############################################################################ + + register TP_LFIR + { + name "Centaur chip TP_LFIR"; + scomaddr 0x0104000A; + reset (&, 0x0104000B); + mask (|, 0x0104000F); + capture group default; + capture group FirRegs; + }; + + register TP_LFIR_MASK + { + name "Centaur chip TP_LFIR MASK"; + scomaddr 0x0104000D; + capture group default; + capture group FirRegs; + }; + + register TP_LFIR_ACT0 + { + name "Centaur chip TP_LFIR ACT0"; + scomaddr 0x01040010; + capture type secondary; + capture group default; + capture group FirRegs; + capture req nonzero("TP_LFIR"); + }; + + register TP_LFIR_ACT1 + { + name "Centaur chip TP_LFIR ACT1"; + scomaddr 0x01040011; + capture type secondary; + capture group default; + capture group FirRegs; + capture req nonzero("TP_LFIR"); + }; + + ############################################################################ + # NEST Chiplet FIR + ############################################################################ + + register NEST_CHIPLET_CS_FIR + { + name "NEST Chiplet Checkstop FIR"; + scomaddr 0x02040000; + capture group default; + capture group FirRegs; + }; + + register NEST_CHIPLET_RE_FIR + { + name "NEST Chiplet Recoverable FIR"; + scomaddr 0x02040001; + capture group default; + capture group FirRegs; + }; + + register NEST_CHIPLET_FIR_MASK + { + name "NEST Chiplet FIR MASK"; + scomaddr 0x02040002; + capture group default; + capture group FirRegs; + }; + + ############################################################################ + # Centaur chip NEST_LFIR + ############################################################################ + + register NEST_LFIR + { + name "Centaur chip NEST_LFIR"; + scomaddr 0x0204000A; + reset (&, 0x0204000B); + mask (|, 0x0204000F); + capture group default; + capture group FirRegs; + }; + + register NEST_LFIR_MASK + { + name "Centaur chip NEST_LFIR MASK"; + scomaddr 0x0204000D; + capture group default; + capture group FirRegs; + }; + + register NEST_LFIR_ACT0 + { + name "Centaur chip NEST_LFIR ACT0"; + scomaddr 0x02040010; + capture type secondary; + capture group default; + capture group FirRegs; + capture req nonzero("NEST_LFIR"); + }; + + register NEST_LFIR_ACT1 + { + name "Centaur chip NEST_LFIR ACT1"; + scomaddr 0x02040011; + capture type secondary; + capture group default; + capture group FirRegs; + capture req nonzero("NEST_LFIR"); + }; + + ############################################################################ + # Centaur chip DMIFIR + ############################################################################ + + register DMIFIR + { + name "Centaur chip DMIFIR"; + scomaddr 0x02010400; + reset (&, 0x02010401); + mask (|, 0x02010405); + capture group default; + capture group FirRegs; + }; + + register DMIFIR_MASK + { + name "Centaur chip DMIFIR MASK"; + scomaddr 0x02010403; + capture group default; + capture group FirRegs; + }; + + register DMIFIR_ACT0 + { + name "Centaur chip DMIFIR ACT0"; + scomaddr 0x02010406; + capture type secondary; + capture group default; + capture group FirRegs; + capture req nonzero("DMIFIR"); + }; + + register DMIFIR_ACT1 + { + name "Centaur chip DMIFIR ACT1"; + scomaddr 0x02010407; + capture type secondary; + capture group default; + capture group FirRegs; + capture req nonzero("DMIFIR"); + }; + + ############################################################################ + # Centaur chip MBIFIR + ############################################################################ + + register MBIFIR + { + name "Centaur chip MBIFIR"; + scomaddr 0x02010800; + reset (&, 0x02010801); + mask (|, 0x02010805); + capture group default; + capture group FirRegs; + }; + + register MBIFIR_MASK + { + name "Centaur chip MBIFIR MASK"; + scomaddr 0x02010803; + capture group default; + capture group FirRegs; + }; + + register MBIFIR_ACT0 + { + name "Centaur chip MBIFIR ACT0"; + scomaddr 0x02010806; + capture type secondary; + capture group default; + capture group FirRegs; + capture req nonzero("MBIFIR"); + }; + + register MBIFIR_ACT1 + { + name "Centaur chip MBIFIR ACT1"; + scomaddr 0x02010807; + capture type secondary; + capture group default; + capture group FirRegs; + capture req nonzero("MBIFIR"); + }; ############################################################################ - # Non-existent Registers for Capture + # Centaur chip MBSFIR ############################################################################ - register VPD_FAILED_LANES_0TO63 + register MBSFIR { - name "Bit map 0-63 of failed lanes read from VPD"; - scomaddr 0xFFFF0001; - access no_access; - capture group never; + name "Centaur chip MBSFIR"; + scomaddr 0x02011400; + reset (&, 0x02011401); + mask (|, 0x02011405); + capture group default; + capture group FirRegs; }; - register VPD_FAILED_LANES_64TO127 + register MBSFIR_MASK { - name "Bit map 64-127 of failed lanes read from VPD"; - scomaddr 0xFFFF0002; - access no_access; - capture group never; + name "Centaur chip MBSFIR MASK"; + scomaddr 0x02011403; + capture group default; + capture group FirRegs; }; - register ALL_FAILED_LANES_0TO63 + register MBSFIR_ACT0 { - name "Bit map 0-63 of failed lanes from io_read_erepair"; - scomaddr 0xFFFF0003; - access no_access; - capture group never; + name "Centaur chip MBSFIR ACT0"; + scomaddr 0x02011406; + capture type secondary; + capture group default; + capture group FirRegs; + capture req nonzero("MBSFIR"); }; - register ALL_FAILED_LANES_64TO127 + register MBSFIR_ACT1 { - name "Bit map 64-127 of failed lanes from io_read_erepair"; - scomaddr 0xFFFF0004; - access no_access; - capture group never; + name "Centaur chip MBSFIR ACT1"; + scomaddr 0x02011407; + capture type secondary; + capture group default; + capture group FirRegs; + capture req nonzero("MBSFIR"); }; ############################################################################ - # PLL Registers + # Centaur chip MBSSECUREFIR ############################################################################ - register CFAM_FSI_STATUS + # This register is hardwired to channel failure (checkstop) and we cannot + # mask or change the state of the action registers. + register MBSSECUREFIR + { + name "Centaur chip MBSSECUREFIR"; + scomaddr 0x0201141e; + reset (&, 0x0201141f); + capture group default; + capture group FirRegs; + }; + + ############################################################################ + # Centaur chip MBSECCFIR 0 + ############################################################################ + + register MBSECCFIR_0 + { + name "Centaur chip MBSECCFIR 0"; + scomaddr 0x02011440; + reset (&, 0x02011441); + mask (|, 0x02011445); + capture group default; + capture group FirRegs; + capture group MaintCmdRegs_mba0; + }; + + register MBSECCFIR_0_MASK + { + name "Centaur chip MBSECCFIR 0 MASK"; + scomaddr 0x02011443; + capture group default; + capture group FirRegs; + capture group MaintCmdRegs_mba0; + }; + + register MBSECCFIR_0_ACT0 { - name "VI.FSI.STATUS"; - scomaddr 0x00001007; - capture group never; + name "Centaur chip MBSECCFIR 0 ACT0"; + scomaddr 0x02011446; + capture type secondary; + capture group default; + capture group FirRegs; + capture group MaintCmdRegs_mba0; + capture req nonzero("MBSECCFIR_0"); }; + register MBSECCFIR_0_ACT1 + { + name "Centaur chip MBSECCFIR 0 ACT1"; + scomaddr 0x02011447; + capture type secondary; + capture group default; + capture group FirRegs; + capture group MaintCmdRegs_mba0; + capture req nonzero("MBSECCFIR_0"); + }; + + ############################################################################ + # Centaur chip MBSECCFIR 1 + ############################################################################ + + register MBSECCFIR_1 + { + name "Centaur chip MBSECCFIR 1"; + scomaddr 0x02011480; + reset (&, 0x02011481); + mask (|, 0x02011485); + capture group default; + capture group FirRegs; + capture group MaintCmdRegs_mba1; + }; + + register MBSECCFIR_1_MASK + { + name "Centaur chip MBSECCFIR 1 MASK"; + scomaddr 0x02011483; + capture group default; + capture group FirRegs; + capture group MaintCmdRegs_mba1; + }; + + register MBSECCFIR_1_ACT0 + { + name "Centaur chip MBSECCFIR 1 ACT0"; + scomaddr 0x02011486; + capture type secondary; + capture group default; + capture group FirRegs; + capture group MaintCmdRegs_mba1; + capture req nonzero("MBSECCFIR_1"); + }; + + register MBSECCFIR_1_ACT1 + { + name "Centaur chip MBSECCFIR 1 ACT1"; + scomaddr 0x02011487; + capture type secondary; + capture group default; + capture group FirRegs; + capture group MaintCmdRegs_mba1; + capture req nonzero("MBSECCFIR_1"); + }; + + ############################################################################ + # Centaur chip SCACFIR + ############################################################################ + + register SCACFIR + { + name "Centaur chip SCACFIR"; + scomaddr 0x020115c0; + reset (&, 0x020115c1); + mask (|, 0x020115c5); + capture group default; + capture group FirRegs; + }; + + register SCACFIR_MASK + { + name "Centaur chip SCACFIR MASK"; + scomaddr 0x020115c3; + capture group default; + capture group FirRegs; + }; + + register SCACFIR_ACT0 + { + name "Centaur chip SCACFIR ACT0"; + scomaddr 0x020115c6; + capture type secondary; + capture group default; + capture group FirRegs; + capture req nonzero("SCACFIR"); + }; + + register SCACFIR_ACT1 + { + name "Centaur chip SCACFIR ACT1"; + scomaddr 0x020115c7; + capture type secondary; + capture group default; + capture group FirRegs; + capture req nonzero("SCACFIR"); + }; + + ############################################################################ + # Centaur chip MCBISTFIR 0 + ############################################################################ + + register MCBISTFIR_0 + { + name "Centaur chip MCBISTFIR 0"; + scomaddr 0x02011600; + reset (&, 0x02011601); + mask (|, 0x02011605); + capture group default; + capture group FirRegs; + }; + + register MCBISTFIR_0_MASK + { + name "Centaur chip MCBISTFIR 0 MASK"; + scomaddr 0x02011603; + capture group default; + capture group FirRegs; + }; + + register MCBISTFIR_0_ACT0 + { + name "Centaur chip MCBISTFIR 0 ACT0"; + scomaddr 0x02011606; + capture type secondary; + capture group default; + capture group FirRegs; + capture req nonzero("MCBISTFIR_0"); + }; + + register MCBISTFIR_0_ACT1 + { + name "Centaur chip MCBISTFIR 0 ACT1"; + scomaddr 0x02011607; + capture type secondary; + capture group default; + capture group FirRegs; + capture req nonzero("MCBISTFIR_0"); + }; + + ############################################################################ + # Centaur chip MCBISTFIR 1 + ############################################################################ + + register MCBISTFIR_1 + { + name "Centaur chip MCBISTFIR 1"; + scomaddr 0x02011700; + reset (&, 0x02011701); + mask (|, 0x02011705); + capture group default; + capture group FirRegs; + }; + + register MCBISTFIR_1_MASK + { + name "Centaur chip MCBISTFIR 1 MASK"; + scomaddr 0x02011703; + capture group default; + capture group FirRegs; + }; + + register MCBISTFIR_1_ACT0 + { + name "Centaur chip MCBISTFIR 1 ACT0"; + scomaddr 0x02011706; + capture type secondary; + capture group default; + capture group FirRegs; + capture req nonzero("MCBISTFIR_1"); + }; + + register MCBISTFIR_1_ACT1 + { + name "Centaur chip MCBISTFIR 1 ACT1"; + scomaddr 0x02011707; + capture type secondary; + capture group default; + capture group FirRegs; + capture req nonzero("MCBISTFIR_1"); + }; + + ############################################################################ + # MEM Chiplet FIR + ############################################################################ + + register MEM_CHIPLET_CS_FIR + { + name "MEM Chiplet Checkstop FIR"; + scomaddr 0x03040000; + capture group FirRegs; + capture group MemChipletRegs; + }; + + register MEM_CHIPLET_RE_FIR + { + name "MEM Chiplet Recoverable FIR"; + scomaddr 0x03040001; + capture group FirRegs; + capture group MemChipletRegs; + }; + + register MEM_CHIPLET_FIR_MASK + { + name "MEM Chiplet FIR MASK"; + scomaddr 0x03040002; + capture group FirRegs; + capture group MemChipletRegs; + }; + + ############################################################################ + # MEM Chiplet Special Attention FIR + ############################################################################ + + register MEM_CHIPLET_SPA_FIR + { + name "MEM Chiplet Special Attention FIR"; + scomaddr 0x03040004; + capture group FirRegs; + capture group MemChipletRegs; + }; + + register MEM_CHIPLET_SPA_FIR_MASK + { + name "MEM Chiplet Special Attention FIR MASK"; + scomaddr 0x03040007; + capture group FirRegs; + capture group MemChipletRegs; + }; + + ############################################################################ + # Centaur chip MEM_LFIR + ############################################################################ + + register MEM_LFIR + { + name "Centaur chip MEM_LFIR"; + scomaddr 0x0304000A; + reset (&, 0x0304000B); + mask (|, 0x0304000F); + capture group FirRegs; + capture group MemChipletRegs; + }; + + register MEM_LFIR_MASK + { + name "Centaur chip MEM_LFIR MASK"; + scomaddr 0x0304000D; + capture group FirRegs; + capture group MemChipletRegs; + }; + + register MEM_LFIR_ACT0 + { + name "Centaur chip MEM_LFIR ACT0"; + scomaddr 0x03040010; + capture type secondary; + capture group FirRegs; + capture group MemChipletRegs; + capture req nonzero("MEM_LFIR"); + }; + + register MEM_LFIR_ACT1 + { + name "Centaur chip MEM_LFIR ACT1"; + scomaddr 0x03040011; + capture type secondary; + capture group FirRegs; + capture group MemChipletRegs; + capture req nonzero("MEM_LFIR"); + }; + +# Import all of the chiplet registers +.include "Membuf_regs_TP.rule" +.include "Membuf_regs_NEST.rule" +.include "Membuf_regs_MEM.rule" }; @@ -153,47 +684,1632 @@ chip Membuf ############################################################################## ################################################################################ -# Global Broadcast Registers +# Global Attention FIR ################################################################################ -rule GlobalFir +rule rGLOBAL_FIR { - CHECK_STOP: GLOBAL_CS_FIR; - RECOVERABLE: GLOBAL_RE_FIR; - - # All of the Centaur CS (channel fail) bits are set as checkstop. - UNIT_CS: GLOBAL_CS_FIR; + UNIT_CS: + GLOBAL_CS_FIR; + RECOVERABLE: + GLOBAL_RE_FIR; }; -group gGlobalFir attntype CHECK_STOP, RECOVERABLE, UNIT_CS filter singlebit +group gGLOBAL_FIR attntype UNIT_CS, RECOVERABLE filter singlebit { /** GLOBAL_FIR[1] * Attention from TP chiplet */ - (GlobalFir, bit(1)) ? analyze(gTpChipletFir); + (rGLOBAL_FIR, bit(1)) ? analyze(gTP_CHIPLET_FIR); /** GLOBAL_FIR[2] * Attention from NEST chiplet */ - (GlobalFir, bit(2)) ? analyze(gNestChipletFir); + (rGLOBAL_FIR, bit(2)) ? analyze(gNEST_CHIPLET_FIR); /** GLOBAL_FIR[3] * Attention from MEM chiplet */ - (GlobalFir, bit(3)) ? analyze(gMemChipletFir); + (rGLOBAL_FIR, bit(3)) ? analyze(gMEM_CHIPLET_FIR); + }; -rule GlobalSpa +################################################################################ +# Global Special Attention FIR +################################################################################ + +rule rGLOBAL_SPA_FIR { - SPECIAL: GLOBAL_SPA; + HOST_ATTN: + GLOBAL_SPA_FIR; }; -group gGlobalSpa attntype SPECIAL filter singlebit +group gGLOBAL_SPA_FIR attntype HOST_ATTN filter singlebit { - /** GLOBAL_SPA[3] + /** GLOBAL_SPA_FIR[3] * Attention from MEM chiplet */ - (GlobalSpa, bit(3)) ? analyze(gMemChipletSpa); + (rGLOBAL_SPA_FIR, bit(3)) ? analyze(gMEM_CHIPLET_SPA_FIR); + +}; + +################################################################################ +# TP Chiplet FIR +################################################################################ + +rule rTP_CHIPLET_FIR +{ + UNIT_CS: + TP_CHIPLET_CS_FIR & ~TP_CHIPLET_FIR_MASK & `1fffffffffffffff`; + RECOVERABLE: + (TP_CHIPLET_RE_FIR >> 2) & ~TP_CHIPLET_FIR_MASK & `1fffffffffffffff`; +}; + +group gTP_CHIPLET_FIR filter singlebit +{ + /** TP_CHIPLET_FIR[3] + * Attention from TP_LFIR + */ + (rTP_CHIPLET_FIR, bit(3)) ? analyze(gTP_LFIR); + +}; + +################################################################################ +# Centaur chip TP_LFIR +################################################################################ + +rule rTP_LFIR +{ + UNIT_CS: + TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 & ~TP_LFIR_ACT1; + RECOVERABLE: + TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 & TP_LFIR_ACT1; +}; + +group gTP_LFIR filter singlebit, cs_root_cause( 19, 20 ) +{ + /** TP_LFIR[0] + * CFIR internal parity error + */ + (rTP_LFIR, bit(0)) ? threshold_and_mask_self; + + /** TP_LFIR[1] + * GPIO (PCB error) + */ + (rTP_LFIR, bit(1)) ? defaultMaskedError; + + /** TP_LFIR[2] + * CC (PCB error) + */ + (rTP_LFIR, bit(2)) ? defaultMaskedError; + + /** TP_LFIR[3] + * CC (OPCG, parity, scan collision, ...) + */ + (rTP_LFIR, bit(3)) ? defaultMaskedError; + + /** TP_LFIR[4] + * PSC (PCB error) + */ + (rTP_LFIR, bit(4)) ? defaultMaskedError; + + /** TP_LFIR[5] + * PSC (parity error) + */ + (rTP_LFIR, bit(5)) ? defaultMaskedError; + + /** TP_LFIR[6] + * Thermal (parity error) + */ + (rTP_LFIR, bit(6)) ? defaultMaskedError; + + /** TP_LFIR[7] + * Thermal (PCB error) + */ + (rTP_LFIR, bit(7)) ? defaultMaskedError; + + /** TP_LFIR[8] + * Thermal (critical trip error) + */ + (rTP_LFIR, bit(8)) ? defaultMaskedError; + + /** TP_LFIR[9] + * Thermal (fatal trip error) + */ + (rTP_LFIR, bit(9)) ? defaultMaskedError; + + /** TP_LFIR[10] + * Thermal (voltage trip error) + */ + (rTP_LFIR, bit(10)) ? defaultMaskedError; + + /** TP_LFIR[11] + * Trace Array ( error) + */ + (rTP_LFIR, bit(11)) ? defaultMaskedError; + + /** TP_LFIR[12] + * Trace Array ( error) + */ + (rTP_LFIR, bit(12)) ? defaultMaskedError; + + /** TP_LFIR[13:14] + * ITR + */ + (rTP_LFIR, bit(13|14)) ? threshold_and_mask_self; + + /** TP_LFIR[15] + * ITR (itr_tc_pcbsl_slave_fir_err) + */ + (rTP_LFIR, bit(15)) ? defaultMaskedError; + + /** TP_LFIR[16:18] + * PIB + */ + (rTP_LFIR, bit(16|17|18)) ? defaultMaskedError; + + /** TP_LFIR[19] + * NEST PLL unlock + */ + (rTP_LFIR, bit(19)) ? pll_unlock_UERE; + + /** TP_LFIR[20] + * MEM PLL unlock + */ + (rTP_LFIR, bit(20)) ? pll_unlock_UERE; + + /** TP_LFIR[21:39] + * Reserved + */ + (rTP_LFIR, bit(21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? defaultMaskedError; + + /** TP_LFIR[40] + * malfunction alert (local xstop in another chiplet) + */ + (rTP_LFIR, bit(40)) ? defaultMaskedError; + +}; + +################################################################################ +# NEST Chiplet FIR +################################################################################ + +rule rNEST_CHIPLET_FIR +{ + UNIT_CS: + NEST_CHIPLET_CS_FIR & ~NEST_CHIPLET_FIR_MASK & `1fffffffffffffff`; + RECOVERABLE: + (NEST_CHIPLET_RE_FIR >> 2) & ~NEST_CHIPLET_FIR_MASK & `1fffffffffffffff`; +}; + +group gNEST_CHIPLET_FIR filter priority( 3, 6, 5, 7 ) +{ + # NOTE: The MBIFIR must be analyzed before the DMIFIR and both the MBIFIR + # and DMIFIR must be analyzed before the MBSFIR. All other FIRs will be + # analyzed in order. + + /** NEST_CHIPLET_FIR[3] + * Attention from NEST_LFIR + */ + (rNEST_CHIPLET_FIR, bit(3)) ? analyze(gNEST_LFIR); + + /** NEST_CHIPLET_FIR[5] + * Attention from DMIFIR + */ + (rNEST_CHIPLET_FIR, bit(5)) ? analyze(gDMIFIR); + + /** NEST_CHIPLET_FIR[6] + * Attention from MBIFIR + */ + (rNEST_CHIPLET_FIR, bit(6)) ? analyze(gMBIFIR); + + /** NEST_CHIPLET_FIR[7] + * Attention from MBSFIR + */ + (rNEST_CHIPLET_FIR, bit(7)) ? analyze(gMBSFIR); + + /** NEST_CHIPLET_FIR[8] + * Attention from MCBISTFIR + */ + (rNEST_CHIPLET_FIR, bit(8)) ? analyze(gMCBISTFIR_0); + + /** NEST_CHIPLET_FIR[9] + * Attention from MCBISTFIR + */ + (rNEST_CHIPLET_FIR, bit(9)) ? analyze(gMCBISTFIR_1); + + /** NEST_CHIPLET_FIR[10] + * Attention from MBSECCFIR + */ + (rNEST_CHIPLET_FIR, bit(10)) ? analyze(gMBSECCFIR_0); + + /** NEST_CHIPLET_FIR[11] + * Attention from MBSECCFIR + */ + (rNEST_CHIPLET_FIR, bit(11)) ? analyze(gMBSECCFIR_1); + + /** NEST_CHIPLET_FIR[13] + * Attention from SCACFIR + */ + (rNEST_CHIPLET_FIR, bit(13)) ? analyze(gSCACFIR); + + /** NEST_CHIPLET_FIR[14] + * Attention from MBSSECUREFIR + */ + (rNEST_CHIPLET_FIR, bit(14)) ? analyze(gMBSSECUREFIR); + +}; + +################################################################################ +# Centaur chip NEST_LFIR +################################################################################ + +rule rNEST_LFIR +{ + UNIT_CS: + NEST_LFIR & ~NEST_LFIR_MASK & ~NEST_LFIR_ACT0 & ~NEST_LFIR_ACT1; + RECOVERABLE: + NEST_LFIR & ~NEST_LFIR_MASK & ~NEST_LFIR_ACT0 & NEST_LFIR_ACT1; +}; + +group gNEST_LFIR filter singlebit, cs_root_cause +{ + /** NEST_LFIR[0] + * CFIR internal parity error + */ + (rNEST_LFIR, bit(0)) ? threshold_and_mask_self; + + /** NEST_LFIR[1] + * GPIO (PCB error) + */ + (rNEST_LFIR, bit(1)) ? defaultMaskedError; + + /** NEST_LFIR[2] + * CC (PCB error) + */ + (rNEST_LFIR, bit(2)) ? defaultMaskedError; + + /** NEST_LFIR[3] + * CC (OPCG, parity, scan collision, ...) + */ + (rNEST_LFIR, bit(3)) ? defaultMaskedError; + + /** NEST_LFIR[4] + * PSC (PCB error) + */ + (rNEST_LFIR, bit(4)) ? defaultMaskedError; + + /** NEST_LFIR[5] + * PSC (parity error) + */ + (rNEST_LFIR, bit(5)) ? defaultMaskedError; + + /** NEST_LFIR[6] + * Thermal (parity error) + */ + (rNEST_LFIR, bit(6)) ? defaultMaskedError; + + /** NEST_LFIR[7] + * Thermal (PCB error) + */ + (rNEST_LFIR, bit(7)) ? defaultMaskedError; + + /** NEST_LFIR[8] + * Thermal (critical trip error) + */ + (rNEST_LFIR, bit(8)) ? defaultMaskedError; + + /** NEST_LFIR[9] + * Thermal (fatal trip error) + */ + (rNEST_LFIR, bit(9)) ? defaultMaskedError; + + /** NEST_LFIR[10] + * Thermal (voltage trip error) + */ + (rNEST_LFIR, bit(10)) ? defaultMaskedError; + + /** NEST_LFIR[11] + * Trace Array ( error) + */ + (rNEST_LFIR, bit(11)) ? defaultMaskedError; + + /** NEST_LFIR[12] + * Trace Array ( error) + */ + (rNEST_LFIR, bit(12)) ? defaultMaskedError; + + /** NEST_LFIR[13:39] + * Reserved + */ + (rNEST_LFIR, bit(13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? defaultMaskedError; + + /** NEST_LFIR[40] + * malfunction alert (local xstop in another chiplet) + */ + (rNEST_LFIR, bit(40)) ? defaultMaskedError; + +}; + +################################################################################ +# Centaur chip DMIFIR +################################################################################ + +rule rDMIFIR +{ + UNIT_CS: + DMIFIR & ~DMIFIR_MASK & ~DMIFIR_ACT0 & ~DMIFIR_ACT1; + RECOVERABLE: + DMIFIR & ~DMIFIR_MASK & ~DMIFIR_ACT0 & DMIFIR_ACT1; +}; + +group gDMIFIR filter priority( 10, 2, 11, 12, 9 ), + cs_root_cause( 10 ) +{ + /** DMIFIR[0] + * RX invalid state or parity error + */ + (rDMIFIR, bit(0)) ? defaultMaskedError; + + /** DMIFIR[1] + * TX invalid state or parity error + */ + (rDMIFIR, bit(1)) ? defaultMaskedError; + + /** DMIFIR[2] + * GCR hang error + */ + (rDMIFIR, bit(2)) ? self_th_1; + + /** DMIFIR[3:7] + * Reserved + */ + (rDMIFIR, bit(3|4|5|6|7)) ? defaultMaskedError; + + /** DMIFIR[8] + * Training error + */ + (rDMIFIR, bit(8)) ? defaultMaskedError; + + /** DMIFIR[9] + * Spare lane deployed + */ + (rDMIFIR, bit(9)) ? spareDeployed_dmibus; + + /** DMIFIR[10] + * Max spares exceeded + */ + (rDMIFIR, bit(10)) ? maxSparesExceeded_dmibus_UERE; + + /** DMIFIR[11] + * Recal or dynamic repair error + */ + (rDMIFIR, bit(11)) ? calloutBusInterface_dmibus_th1; + + /** DMIFIR[12] + * Too many bus errors + */ + (rDMIFIR, bit(12)) ? tooManyBusErrors_dmibus; + + /** DMIFIR[13:15] + * Reserved + */ + (rDMIFIR, bit(13|14|15)) ? defaultMaskedError; + + /** DMIFIR[16:23] + * Bus 1 - unused + */ + (rDMIFIR, bit(16|17|18|19|20|21|22|23)) ? defaultMaskedError; + + /** DMIFIR[24:31] + * Bus 2 - unused + */ + (rDMIFIR, bit(24|25|26|27|28|29|30|31)) ? defaultMaskedError; + + /** DMIFIR[32:39] + * Bus 3 - unused + */ + (rDMIFIR, bit(32|33|34|35|36|37|38|39)) ? defaultMaskedError; + + /** DMIFIR[40:47] + * Bus 4 - unused + */ + (rDMIFIR, bit(40|41|42|43|44|45|46|47)) ? defaultMaskedError; + + /** DMIFIR[48] + * scom error + */ + (rDMIFIR, bit(48)) ? threshold_and_mask_self; + + /** DMIFIR[49] + * scom error + */ + (rDMIFIR, bit(49)) ? threshold_and_mask_self; + +}; + +################################################################################ +# Centaur chip MBIFIR +################################################################################ + +rule rMBIFIR +{ + UNIT_CS: + MBIFIR & ~MBIFIR_MASK & ~MBIFIR_ACT0 & ~MBIFIR_ACT1; + RECOVERABLE: + MBIFIR & ~MBIFIR_MASK & ~MBIFIR_ACT0 & MBIFIR_ACT1; +}; + +group gMBIFIR filter priority( 8, 9, 19, 20, 6, 0, 16, 5, 10 ), + cs_root_cause( 0, 6, 8, 9, 19, 20 ) +{ + /** MBIFIR[0] + * Replay Timeout + */ + (rMBIFIR, bit(0)) ? replayTimeOutError; + + /** MBIFIR[1] + * Channel Fail + */ + (rMBIFIR, bit(1)) ? defaultMaskedError; + + /** MBIFIR[2] + * CRC Error + */ + (rMBIFIR, bit(2)) ? defaultMaskedError; + + /** MBIFIR[3] + * Frame NoAck + */ + (rMBIFIR, bit(3)) ? defaultMaskedError; + + /** MBIFIR[4] + * Seqid Out of Order + */ + (rMBIFIR, bit(4)) ? defaultMaskedError; + + /** MBIFIR[5] + * Replay Buffer ECC CE + */ + (rMBIFIR, bit(5)) ? self_th_5perHour; + + /** MBIFIR[6] + * Replay Buffer ECC UE + */ + (rMBIFIR, bit(6)) ? self_th_1_UERE; + + /** MBIFIR[7] + * MBI State Machine Timeout + */ + (rMBIFIR, bit(7)) ? defaultMaskedError; + + /** MBIFIR[8] + * MBI Internal Control Parity Error + */ + (rMBIFIR, bit(8)) ? self_th_1_UERE; + + /** MBIFIR[9] + * MBI Data Flow Parity Error + */ + (rMBIFIR, bit(9)) ? self_th_1_UERE; + + /** MBIFIR[10] + * CRC Performance Degradation + */ + (rMBIFIR, bit(10)) ? analyzeSpareBitAndThr; + + /** MBIFIR[11] + * Global Host MC Checkstop + */ + (rMBIFIR, bit(11)) ? defaultMaskedError; + + /** MBIFIR[12] + * Host MC Tracestop + */ + (rMBIFIR, bit(12)) ? defaultMaskedError; + + /** MBIFIR[13] + * Channel Interlock Fail + */ + (rMBIFIR, bit(13)) ? defaultMaskedError; + + /** MBIFIR[14] + * Host MC Local Checkstop + */ + (rMBIFIR, bit(14)) ? defaultMaskedError; + + /** MBIFIR[15] + * FRTL Counter Overflow + */ + (rMBIFIR, bit(15)) ? defaultMaskedError; + + /** MBIFIR[16] + * SCOM Register parity error + */ + (rMBIFIR, bit(16)) ? self_th_1; + + /** MBIFIR[17] + * IO Fault + */ + (rMBIFIR, bit(17)) ? defaultMaskedError; + + /** MBIFIR[18] + * Multiple Replay + */ + (rMBIFIR, bit(18)) ? defaultMaskedError; + + /** MBIFIR[19] + * MBICFG parity error + */ + (rMBIFIR, bit(19)) ? self_th_1_UERE; + + /** MBIFIR[20] + * Replay Buffer Overrun + */ + (rMBIFIR, bit(20)) ? calloutBusInterface_dmibus_th1_UERE; + + /** MBIFIR[21] + * WAT error + */ + (rMBIFIR, bit(21)) ? defaultMaskedError; + + /** MBIFIR[22:24] + * Reserved + */ + (rMBIFIR, bit(22|23|24)) ? defaultMaskedError; + + /** MBIFIR[25] + * internal scom error + */ + (rMBIFIR, bit(25)) ? threshold_and_mask_self; + + /** MBIFIR[26] + * internal scom error clone + */ + (rMBIFIR, bit(26)) ? threshold_and_mask_self; + +}; + +################################################################################ +# Centaur chip MBSFIR +################################################################################ + +rule rMBSFIR +{ + UNIT_CS: + MBSFIR & ~MBSFIR_MASK & ~MBSFIR_ACT0 & ~MBSFIR_ACT1; + RECOVERABLE: + MBSFIR & ~MBSFIR_MASK & ~MBSFIR_ACT0 & MBSFIR_ACT1; +}; + +group gMBSFIR filter singlebit, cs_root_cause( 0, 1, 2, 4, 6, 8, 10, 13, 16, 18, 20, 27, 30 ) +{ + /** MBSFIR[0] + * HOST_PROTOCOL_ERROR + */ + (rMBSFIR, bit(0)) ? calloutBusInterface_dmibus_th1_UERE; + + /** MBSFIR[1] + * INT_PROTOCOL_ERROR + */ + (rMBSFIR, bit(1)) ? self_th_1_UERE; + + /** MBSFIR[2] + * INVALID_ADDRESS_ERROR + */ + (rMBSFIR, bit(2)) ? calloutBusInterface_dmibus_th1; + + /** MBSFIR[3] + * EXTERNAL_TIMEOUT + */ + (rMBSFIR, bit(3)) ? level2_th_1; + + /** MBSFIR[4] + * INTERNAL_TIMEOUT + */ + (rMBSFIR, bit(4)) ? internalTimeout; + + /** MBSFIR[3,4] + * EXTERNAL_TIMEOUT + */ + # NOTE: The signature will match the external timeout, but we will still + # call the internalTimeout plugin because there is extra processing + # done to handle parity errors and such. + (rMBSFIR, bit(3,4)) ? internalTimeout; + + /** MBSFIR[5] + * INT_BUFFER_CE + */ + (rMBSFIR, bit(5)) ? self_th_32perDay; + + /** MBSFIR[6] + * INT_BUFFER_UE + */ + (rMBSFIR, bit(6)) ? self_th_1_UERE; + + /** MBSFIR[7] + * INT_BUFFER_SUE + */ + (rMBSFIR, bit(7)) ? defaultMaskedError; + + /** MBSFIR[8] + * INT_PARITY_ERROR + */ + (rMBSFIR, bit(8)) ? self_th_1_UERE; + + /** MBSFIR[9] + * CACHE_SRW_CE + */ + (rMBSFIR, bit(9)) ? l4_cache_srw_ce; + + /** MBSFIR[10] + * CACHE_SRW_UE + */ + (rMBSFIR, bit(10)) ? l4_cache_srw_ue_UERE; + + /** MBSFIR[11] + * CACHE_SRW_SUE + */ + (rMBSFIR, bit(11)) ? defaultMaskedError; + + /** MBSFIR[12] + * CACHE_CO_CE + */ + (rMBSFIR, bit(12)) ? l4_cache_co_ce; + + /** MBSFIR[13] + * CACHE_CO_UE + */ + (rMBSFIR, bit(13)) ? l4_cache_co_ue_UERE; + + /** MBSFIR[14] + * CACHE_CO_SUE + */ + (rMBSFIR, bit(14)) ? defaultMaskedError; + + /** MBSFIR[15] + * DIR_CE + */ + (rMBSFIR, bit(15)) ? l4_th_32perDay; + + /** MBSFIR[16] + * DIR_UE + */ + (rMBSFIR, bit(16)) ? l4_th_1_UERE; + + /** MBSFIR[17] + * DIR_MEMBER_DELETED + */ + (rMBSFIR, bit(17)) ? defaultMaskedError; + + /** MBSFIR[18] + * DIR_ALL_MEMBERS_DELETED + */ + (rMBSFIR, bit(18)) ? l4_th_1_UERE; + + /** MBSFIR[19] + * LRU_ERROR + */ + (rMBSFIR, bit(19)) ? l4_th_32perDay; + + /** MBSFIR[20] + * EDRAM ERROR + */ + (rMBSFIR, bit(20)) ? l4_th_1_UERE; + + /** MBSFIR[21] + * EMERGENCY_THROTTLE_SET + */ + (rMBSFIR, bit(21)) ? defaultMaskedError; + + /** MBSFIR[22] + * HOST_INBAND_READ_ERROR + */ + (rMBSFIR, bit(22)) ? defaultMaskedError; + + /** MBSFIR[23] + * HOST_INBAND_WRITE_ERROR + */ + (rMBSFIR, bit(23)) ? defaultMaskedError; + + /** MBSFIR[24] + * OCC_INBAND_READ_ERROR + */ + (rMBSFIR, bit(24)) ? defaultMaskedError; + + /** MBSFIR[25] + * OCC_INBAND_WRITE_ERROR + */ + (rMBSFIR, bit(25)) ? defaultMaskedError; + + /** MBSFIR[26] + * SRB_BUFFER_CE + */ + (rMBSFIR, bit(26)) ? threshold_and_mask_self; + + /** MBSFIR[27] + * SRB_BUFFER_UE + */ + (rMBSFIR, bit(27)) ? self_th_1_UERE; + + /** MBSFIR[28] + * SRB_BUFFER_SUE + */ + (rMBSFIR, bit(28)) ? defaultMaskedError; + + /** MBSFIR[29] + * DIR_PURGE_CE + */ + (rMBSFIR, bit(29)) ? defaultMaskedError; + + /** MBSFIR[30] + * PROXIMAL_CE_UE + */ + (rMBSFIR, bit(30)) ? l4_th_1_UERE; + + /** MBSFIR[31:32] + * Spare + */ + (rMBSFIR, bit(31|32)) ? defaultMaskedError; + + /** MBSFIR[33] + * SCOM FIR error + */ + (rMBSFIR, bit(33)) ? threshold_and_mask_self; + + /** MBSFIR[34] + * SCOM FIR error clone + */ + (rMBSFIR, bit(34)) ? threshold_and_mask_self; + +}; + +################################################################################ +# Centaur chip MBSSECUREFIR +################################################################################ + +rule rMBSSECUREFIR +{ + UNIT_CS: + MBSSECUREFIR; +}; + +group gMBSSECUREFIR filter singlebit, cs_root_cause( 0, 1, 2, 3, 4, 5 ) +{ + /** MBSSECUREFIR[0] + * Invalid MBSXCR access + */ + (rMBSSECUREFIR, bit(0)) ? level2_th_1_UERE; + + /** MBSSECUREFIR[1] + * Invalid MBSXCR01 access + */ + (rMBSSECUREFIR, bit(1)) ? level2_th_1_UERE; + + /** MBSSECUREFIR[2] + * Invalid MBSXCR23 access + */ + (rMBSSECUREFIR, bit(2)) ? level2_th_1_UERE; + + /** MBSSECUREFIR[3] + * Invalid MBSXCRMS access + */ + (rMBSSECUREFIR, bit(3)) ? level2_th_1_UERE; + + /** MBSSECUREFIR[4] + * spare + */ + (rMBSSECUREFIR, bit(4)) ? level2_th_1_UERE; + + /** MBSSECUREFIR[5] + * Invalid SIR mask or action reg access + */ + (rMBSSECUREFIR, bit(5)) ? level2_th_1_UERE; + +}; + +################################################################################ +# Centaur chip MBSECCFIR 0 +################################################################################ + +rule rMBSECCFIR_0 +{ + UNIT_CS: + MBSECCFIR_0 & ~MBSECCFIR_0_MASK & ~MBSECCFIR_0_ACT0 & ~MBSECCFIR_0_ACT1; + RECOVERABLE: + MBSECCFIR_0 & ~MBSECCFIR_0_MASK & ~MBSECCFIR_0_ACT0 & MBSECCFIR_0_ACT1; +}; + +group gMBSECCFIR_0 filter priority ( 19, 41 ), + secondarybits(0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16, + 17,18,20,21,22,23,24,25,26,27,28,29,30,31, + 32,33,34,35,36,37,38,39,40,41,42,43,44,45, + 48,50,51) +{ + /** MBSECCFIR_0[0] + * Memory chip mark on rank 0 + */ + (rMBSECCFIR_0, bit(0)) ? analyzeFetchMpe0_0; + + /** MBSECCFIR_0[1] + * Memory chip mark on rank 1 + */ + (rMBSECCFIR_0, bit(1)) ? analyzeFetchMpe0_1; + + /** MBSECCFIR_0[2] + * Memory chip mark on rank 2 + */ + (rMBSECCFIR_0, bit(2)) ? analyzeFetchMpe0_2; + + /** MBSECCFIR_0[3] + * Memory chip mark on rank 3 + */ + (rMBSECCFIR_0, bit(3)) ? analyzeFetchMpe0_3; + + /** MBSECCFIR_0[4] + * Memory chip mark on rank 4 + */ + (rMBSECCFIR_0, bit(4)) ? analyzeFetchMpe0_4; + + /** MBSECCFIR_0[5] + * Memory chip mark on rank 5 + */ + (rMBSECCFIR_0, bit(5)) ? analyzeFetchMpe0_5; + + /** MBSECCFIR_0[6] + * Memory chip mark on rank 6 + */ + (rMBSECCFIR_0, bit(6)) ? analyzeFetchMpe0_6; + + /** MBSECCFIR_0[7] + * Memory chip mark on rank 7 + */ + (rMBSECCFIR_0, bit(7)) ? analyzeFetchMpe0_7; + + /** MBSECCFIR_0[8:15] + * Reserved + */ + (rMBSECCFIR_0, bit(8|9|10|11|12|13|14|15)) ? defaultMaskedError; + + /** MBSECCFIR_0[16] + * Memory NCE + */ + (rMBSECCFIR_0, bit(16)) ? analyzeFetchNce0; + + /** MBSECCFIR_0[17] + * Memory RCE + */ + (rMBSECCFIR_0, bit(17)) ? analyzeFetchRce0; + + /** MBSECCFIR_0[18] + * Memory SUE + */ + (rMBSECCFIR_0, bit(18)) ? defaultMaskedError; + + /** MBSECCFIR_0[19] + * Memory UE + */ + (rMBSECCFIR_0, bit(19)) ? mba0MemoryUe; + + /** MBSECCFIR_0[20:27] + * Maintenance chip mark + */ + (rMBSECCFIR_0, bit(20|21|22|23|24|25|26|27)) ? defaultMaskedError; + + /** MBSECCFIR_0[28:35] + * Reserved + */ + (rMBSECCFIR_0, bit(28|29|30|31|32|33|34|35)) ? defaultMaskedError; + + /** MBSECCFIR_0[36] + * Maintenance NCE + */ + (rMBSECCFIR_0, bit(36)) ? defaultMaskedError; + + /** MBSECCFIR_0[37] + * Maintenance SCE + */ + (rMBSECCFIR_0, bit(37)) ? defaultMaskedError; + + /** MBSECCFIR_0[38] + * Maintenance MCE + */ + (rMBSECCFIR_0, bit(38)) ? defaultMaskedError; + + /** MBSECCFIR_0[39] + * Maintenance RCE + */ + (rMBSECCFIR_0, bit(39)) ? defaultMaskedError; + + /** MBSECCFIR_0[40] + * Maintenance SUE + */ + (rMBSECCFIR_0, bit(40)) ? defaultMaskedError; + + /** MBSECCFIR_0[41] + * Maintenance UE + */ + (rMBSECCFIR_0, bit(41)) ? defaultMaskedError; + + /** MBSECCFIR_0[42] + * MPE during use maintenance mark mode + */ + (rMBSECCFIR_0, bit(42)) ? defaultMaskedError; + + /** MBSECCFIR_0[43] + * Prefetch Memory UE + */ + (rMBSECCFIR_0, bit(43)) ? analyzeFetchPreUe0; + + /** MBSECCFIR_0[44] + * Memory RCD parity error + */ + (rMBSECCFIR_0, bit(44)) ? defaultMaskedError; + + /** MBSECCFIR_0[45] + * Maintenance RCD parity error + */ + (rMBSECCFIR_0, bit(45)) ? defaultMaskedError; + + /** MBSECCFIR_0[46] + * Recoverable config reg PE + */ + (rMBSECCFIR_0, bit(46)) ? mba0_th_1; + + /** MBSECCFIR_0[47] + * Unrecoverable config reg PE + */ + (rMBSECCFIR_0, bit(47)) ? mba0_th_1_UERE; + + /** MBSECCFIR_0[48] + * Maskable config reg PE + */ + (rMBSECCFIR_0, bit(48)) ? threshold_and_mask_mba0; + + /** MBSECCFIR_0[49] + * ECC datapath parity error + */ + (rMBSECCFIR_0, bit(49)) ? mba0_th_1_UERE; + + /** MBSECCFIR_0[50] + * internal scom error + */ + (rMBSECCFIR_0, bit(50)) ? threshold_and_mask_mba0; + + /** MBSECCFIR_0[51] + * internal scom error clone + */ + (rMBSECCFIR_0, bit(51)) ? threshold_and_mask_mba0; + +}; + +################################################################################ +# Centaur chip MBSECCFIR 1 +################################################################################ + +rule rMBSECCFIR_1 +{ + UNIT_CS: + MBSECCFIR_1 & ~MBSECCFIR_1_MASK & ~MBSECCFIR_1_ACT0 & ~MBSECCFIR_1_ACT1; + RECOVERABLE: + MBSECCFIR_1 & ~MBSECCFIR_1_MASK & ~MBSECCFIR_1_ACT0 & MBSECCFIR_1_ACT1; +}; + +group gMBSECCFIR_1 filter priority ( 19, 41 ), + secondarybits(0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16, + 17,18,20,21,22,23,24,25,26,27,28,29,30,31, + 32,33,34,35,36,37,38,39,40,41,42,43,44,45, + 48,50,51) +{ + /** MBSECCFIR_1[0] + * Memory chip mark on rank 0 + */ + (rMBSECCFIR_1, bit(0)) ? analyzeFetchMpe1_0; + + /** MBSECCFIR_1[1] + * Memory chip mark on rank 1 + */ + (rMBSECCFIR_1, bit(1)) ? analyzeFetchMpe1_1; + + /** MBSECCFIR_1[2] + * Memory chip mark on rank 2 + */ + (rMBSECCFIR_1, bit(2)) ? analyzeFetchMpe1_2; + + /** MBSECCFIR_1[3] + * Memory chip mark on rank 3 + */ + (rMBSECCFIR_1, bit(3)) ? analyzeFetchMpe1_3; + + /** MBSECCFIR_1[4] + * Memory chip mark on rank 4 + */ + (rMBSECCFIR_1, bit(4)) ? analyzeFetchMpe1_4; + + /** MBSECCFIR_1[5] + * Memory chip mark on rank 5 + */ + (rMBSECCFIR_1, bit(5)) ? analyzeFetchMpe1_5; + + /** MBSECCFIR_1[6] + * Memory chip mark on rank 6 + */ + (rMBSECCFIR_1, bit(6)) ? analyzeFetchMpe1_6; + + /** MBSECCFIR_1[7] + * Memory chip mark on rank 7 + */ + (rMBSECCFIR_1, bit(7)) ? analyzeFetchMpe1_7; + + /** MBSECCFIR_1[8:15] + * Reserved + */ + (rMBSECCFIR_1, bit(8|9|10|11|12|13|14|15)) ? defaultMaskedError; + + /** MBSECCFIR_1[16] + * Memory NCE + */ + (rMBSECCFIR_1, bit(16)) ? analyzeFetchNce1; + + /** MBSECCFIR_1[17] + * Memory RCE + */ + (rMBSECCFIR_1, bit(17)) ? analyzeFetchRce1; + + /** MBSECCFIR_1[18] + * Memory SUE + */ + (rMBSECCFIR_1, bit(18)) ? defaultMaskedError; + + /** MBSECCFIR_1[19] + * Memory UE + */ + (rMBSECCFIR_1, bit(19)) ? mba1MemoryUe; + + /** MBSECCFIR_1[20:27] + * Maintenance chip mark + */ + (rMBSECCFIR_1, bit(20|21|22|23|24|25|26|27)) ? defaultMaskedError; + + /** MBSECCFIR_1[28:35] + * Reserved + */ + (rMBSECCFIR_1, bit(28|29|30|31|32|33|34|35)) ? defaultMaskedError; + + /** MBSECCFIR_1[36] + * Maintenance NCE + */ + (rMBSECCFIR_1, bit(36)) ? defaultMaskedError; + + /** MBSECCFIR_1[37] + * Maintenance SCE + */ + (rMBSECCFIR_1, bit(37)) ? defaultMaskedError; + + /** MBSECCFIR_1[38] + * Maintenance MCE + */ + (rMBSECCFIR_1, bit(38)) ? defaultMaskedError; + + /** MBSECCFIR_1[39] + * Maintenance RCE + */ + (rMBSECCFIR_1, bit(39)) ? defaultMaskedError; + + /** MBSECCFIR_1[40] + * Maintenance SUE + */ + (rMBSECCFIR_1, bit(40)) ? defaultMaskedError; + + /** MBSECCFIR_1[41] + * Maintenance UE + */ + (rMBSECCFIR_1, bit(41)) ? defaultMaskedError; + + /** MBSECCFIR_1[42] + * MPE during use maintenance mark mode + */ + (rMBSECCFIR_1, bit(42)) ? defaultMaskedError; + + /** MBSECCFIR_1[43] + * Prefetch Memory UE + */ + (rMBSECCFIR_1, bit(43)) ? analyzeFetchPreUe1; + + /** MBSECCFIR_1[44] + * Memory RCD parity error + */ + (rMBSECCFIR_1, bit(44)) ? defaultMaskedError; + + /** MBSECCFIR_1[45] + * Maintenance RCD parity error + */ + (rMBSECCFIR_1, bit(45)) ? defaultMaskedError; + + /** MBSECCFIR_1[46] + * Recoverable config reg PE + */ + (rMBSECCFIR_1, bit(46)) ? mba1_th_1; + + /** MBSECCFIR_1[47] + * Unrecoverable config reg PE + */ + (rMBSECCFIR_1, bit(47)) ? mba1_th_1_UERE; + + /** MBSECCFIR_1[48] + * Maskable config reg PE + */ + (rMBSECCFIR_1, bit(48)) ? threshold_and_mask_mba1; + + /** MBSECCFIR_1[49] + * ECC datapath parity error + */ + (rMBSECCFIR_1, bit(49)) ? mba1_th_1_UERE; + + /** MBSECCFIR_1[50] + * internal scom error + */ + (rMBSECCFIR_1, bit(50)) ? threshold_and_mask_mba1; + + /** MBSECCFIR_1[51] + * internal scom error clone + */ + (rMBSECCFIR_1, bit(51)) ? threshold_and_mask_mba1; + +}; + +################################################################################ +# Centaur chip SCACFIR +################################################################################ + +rule rSCACFIR +{ + UNIT_CS: + SCACFIR & ~SCACFIR_MASK & ~SCACFIR_ACT0 & ~SCACFIR_ACT1; + RECOVERABLE: + SCACFIR & ~SCACFIR_MASK & ~SCACFIR_ACT0 & SCACFIR_ACT1; +}; + +group gSCACFIR filter singlebit, cs_root_cause( 25, 26 ) +{ + /** SCACFIR[0] + * I2CM(0) Invalid Address + */ + (rSCACFIR, bit(0)) ? defaultMaskedError; + + /** SCACFIR[1] + * I2CM(1) Invalid Write + */ + (rSCACFIR, bit(1)) ? defaultMaskedError; + + /** SCACFIR[2] + * I2CM(2) Invalid Read + */ + (rSCACFIR, bit(2)) ? defaultMaskedError; + + /** SCACFIR[3] + * I2CM(3) Pib Address Parity Error + */ + (rSCACFIR, bit(3)) ? defaultMaskedError; + + /** SCACFIR[4] + * I2CM(4) Pib Parity Error + */ + (rSCACFIR, bit(4)) ? defaultMaskedError; + + /** SCACFIR[5] + * I2CM(5) LB parity error + */ + (rSCACFIR, bit(5)) ? defaultMaskedError; + + /** SCACFIR[6:9] + * spare + */ + (rSCACFIR, bit(6|7|8|9)) ? defaultMaskedError; + + /** SCACFIR[10] + * I2CM(45) : Invalid Command + */ + (rSCACFIR, bit(10)) ? defaultMaskedError; + + /** SCACFIR[11] + * I2CM(46) : Parity Error + */ + (rSCACFIR, bit(11)) ? defaultMaskedError; + + /** SCACFIR[12] + * I2CM(47): Backend Overrun Error + */ + (rSCACFIR, bit(12)) ? defaultMaskedError; + + /** SCACFIR[13] + * I2CM(48): Backend Access Error + */ + (rSCACFIR, bit(13)) ? defaultMaskedError; + + /** SCACFIR[14] + * I2CM(49): Arbitration Lost Error + */ + (rSCACFIR, bit(14)) ? defaultMaskedError; + + /** SCACFIR[15] + * I2CM(50): Nack Received Error + */ + (rSCACFIR, bit(15)) ? defaultMaskedError; + + /** SCACFIR[16] + * I2CM(53): Stop Error + */ + (rSCACFIR, bit(16)) ? defaultMaskedError; + + /** SCACFIR[17] + * Local PIB Response code 1 + */ + (rSCACFIR, bit(17)) ? defaultMaskedError; + + /** SCACFIR[18] + * Local PIB Response code 2 + */ + (rSCACFIR, bit(18)) ? defaultMaskedError; + + /** SCACFIR[19] + * Local PIB Response code 3 + */ + (rSCACFIR, bit(19)) ? defaultMaskedError; + + /** SCACFIR[20] + * Local PIB Response code 4 + */ + (rSCACFIR, bit(20)) ? defaultMaskedError; + + /** SCACFIR[21] + * Local PIB Response code 5 + */ + (rSCACFIR, bit(21)) ? defaultMaskedError; + + /** SCACFIR[22] + * Local PIB Response code 6 + */ + (rSCACFIR, bit(22)) ? defaultMaskedError; + + /** SCACFIR[23] + * Local PIB Response code 7 + */ + (rSCACFIR, bit(23)) ? defaultMaskedError; + + /** SCACFIR[24] + * Stall Threshold Error + */ + (rSCACFIR, bit(24)) ? defaultMaskedError; + + /** SCACFIR[25] + * Parity Error on Internal Register + */ + (rSCACFIR, bit(25)) ? self_th_1_UERE; + + /** SCACFIR[26] + * Parity Error on Pib Target Register + */ + (rSCACFIR, bit(26)) ? self_th_1_UERE; + + /** SCACFIR[27:31] + * Reserved + */ + (rSCACFIR, bit(27|28|29|30|31)) ? defaultMaskedError; + + /** SCACFIR[32] + * State Machine / Ctrl Logic Error + */ + (rSCACFIR, bit(32)) ? self_th_1; + + /** SCACFIR[33] + * Register access error + */ + (rSCACFIR, bit(33)) ? level2_th_1; + + /** SCACFIR[34] + * PIB error initiating RESET cmd to I2CM + */ + (rSCACFIR, bit(34)) ? defaultMaskedError; + + /** SCACFIR[35] + * Internal SCOM Error + */ + (rSCACFIR, bit(35)) ? threshold_and_mask_self; + + /** SCACFIR[36] + * Internal SCOM Error + */ + (rSCACFIR, bit(36)) ? threshold_and_mask_self; + +}; + +################################################################################ +# Centaur chip MCBISTFIR 0 +################################################################################ + +rule rMCBISTFIR_0 +{ + UNIT_CS: + MCBISTFIR_0 & ~MCBISTFIR_0_MASK & ~MCBISTFIR_0_ACT0 & ~MCBISTFIR_0_ACT1; + RECOVERABLE: + MCBISTFIR_0 & ~MCBISTFIR_0_MASK & ~MCBISTFIR_0_ACT0 & MCBISTFIR_0_ACT1; +}; + +group gMCBISTFIR_0 filter singlebit, cs_root_cause( 0, 1 ) +{ + /** MCBISTFIR_0[0] + * SCOM Parity Errors + */ + (rMCBISTFIR_0, bit(0)) ? mba0_th_1_UERE; + + /** MCBISTFIR_0[1] + * MBX parity errors + */ + (rMCBISTFIR_0, bit(1)) ? mba0_th_1_UERE; + + /** MCBISTFIR_0[2] + * DRAM event 0 error + */ + (rMCBISTFIR_0, bit(2)) ? defaultMaskedError; + + /** MCBISTFIR_0[3] + * DRAM event 1 error + */ + (rMCBISTFIR_0, bit(3)) ? defaultMaskedError; + + /** MCBISTFIR_0[4:14] + * Reserved + */ + (rMCBISTFIR_0, bit(4|5|6|7|8|9|10|11|12|13|14)) ? defaultMaskedError; + + /** MCBISTFIR_0[15] + * SCOM FIR error + */ + (rMCBISTFIR_0, bit(15)) ? threshold_and_mask_mba0; + + /** MCBISTFIR_0[16] + * SCOM FIR error clone + */ + (rMCBISTFIR_0, bit(16)) ? threshold_and_mask_mba0; + +}; + +################################################################################ +# Centaur chip MCBISTFIR 1 +################################################################################ + +rule rMCBISTFIR_1 +{ + UNIT_CS: + MCBISTFIR_1 & ~MCBISTFIR_1_MASK & ~MCBISTFIR_1_ACT0 & ~MCBISTFIR_1_ACT1; + RECOVERABLE: + MCBISTFIR_1 & ~MCBISTFIR_1_MASK & ~MCBISTFIR_1_ACT0 & MCBISTFIR_1_ACT1; +}; + +group gMCBISTFIR_1 filter singlebit, cs_root_cause( 0, 1 ) +{ + /** MCBISTFIR_1[0] + * SCOM Parity Errors + */ + (rMCBISTFIR_1, bit(0)) ? mba1_th_1_UERE; + + /** MCBISTFIR_1[1] + * MBX parity errors + */ + (rMCBISTFIR_1, bit(1)) ? mba1_th_1_UERE; + + /** MCBISTFIR_1[2] + * DRAM event 0 error + */ + (rMCBISTFIR_1, bit(2)) ? defaultMaskedError; + + /** MCBISTFIR_1[3] + * DRAM event 1 error + */ + (rMCBISTFIR_1, bit(3)) ? defaultMaskedError; + + /** MCBISTFIR_1[4:14] + * Reserved + */ + (rMCBISTFIR_1, bit(4|5|6|7|8|9|10|11|12|13|14)) ? defaultMaskedError; + + /** MCBISTFIR_1[15] + * SCOM FIR error + */ + (rMCBISTFIR_1, bit(15)) ? threshold_and_mask_mba1; + + /** MCBISTFIR_1[16] + * SCOM FIR error clone + */ + (rMCBISTFIR_1, bit(16)) ? threshold_and_mask_mba1; + +}; + +################################################################################ +# MEM Chiplet FIR +################################################################################ + +rule rMEM_CHIPLET_FIR +{ + UNIT_CS: + MEM_CHIPLET_CS_FIR & ~MEM_CHIPLET_FIR_MASK & `1fffffffffffffff`; + RECOVERABLE: + (MEM_CHIPLET_RE_FIR >> 2) & ~MEM_CHIPLET_FIR_MASK & `1fffffffffffffff`; +}; + +group gMEM_CHIPLET_FIR filter singlebit +{ + /** MEM_CHIPLET_FIR[3] + * Attention from MEM_LFIR + */ + (rMEM_CHIPLET_FIR, bit(3)) ? analyze(gMEM_LFIR); + + /** MEM_CHIPLET_FIR[5] + * Attention from MBACALFIR 0 + */ + (rMEM_CHIPLET_FIR, bit(5)) ? analyzeConnectedMBA0; + + /** MEM_CHIPLET_FIR[6] + * Attention from MBAFIR 0 + */ + (rMEM_CHIPLET_FIR, bit(6)) ? analyzeConnectedMBA0; + + /** MEM_CHIPLET_FIR[7] + * Attention from MBACALFIR 1 + */ + (rMEM_CHIPLET_FIR, bit(7)) ? analyzeConnectedMBA1; + + /** MEM_CHIPLET_FIR[8] + * Attention from MBAFIR 1 + */ + (rMEM_CHIPLET_FIR, bit(8)) ? analyzeConnectedMBA1; + + /** MEM_CHIPLET_FIR[9] + * Attention from MBADDRPHYFIR 0 + */ + (rMEM_CHIPLET_FIR, bit(9)) ? analyzeConnectedMBA0; + + /** MEM_CHIPLET_FIR[10] + * Attention from MBADDRPHYFIR 1 + */ + (rMEM_CHIPLET_FIR, bit(10)) ? analyzeConnectedMBA1; + + /** MEM_CHIPLET_FIR[12] + * Attention from MBASECUREFIR 0 + */ + (rMEM_CHIPLET_FIR, bit(12)) ? analyzeConnectedMBA0; + + /** MEM_CHIPLET_FIR[13] + * Attention from MBASECUREFIR 1 + */ + (rMEM_CHIPLET_FIR, bit(13)) ? analyzeConnectedMBA1; + +}; + +################################################################################ +# MEM Chiplet Special Attention FIR +################################################################################ + +rule rMEM_CHIPLET_SPA_FIR +{ + HOST_ATTN: + MEM_CHIPLET_SPA_FIR & ~MEM_CHIPLET_SPA_FIR_MASK; +}; + +group gMEM_CHIPLET_SPA_FIR filter singlebit +{ + /** MEM_CHIPLET_SPA_FIR[0] + * Attention from MBASPA 0 + */ + (rMEM_CHIPLET_SPA_FIR, bit(0)) ? analyzeConnectedMBA0; + + /** MEM_CHIPLET_SPA_FIR[1] + * Attention from MBASPA 1 + */ + (rMEM_CHIPLET_SPA_FIR, bit(1)) ? analyzeConnectedMBA1; + +}; + +################################################################################ +# Centaur chip MEM_LFIR +################################################################################ + +rule rMEM_LFIR +{ + UNIT_CS: + MEM_LFIR & ~MEM_LFIR_MASK & ~MEM_LFIR_ACT0 & ~MEM_LFIR_ACT1; + RECOVERABLE: + MEM_LFIR & ~MEM_LFIR_MASK & ~MEM_LFIR_ACT0 & MEM_LFIR_ACT1; +}; + +group gMEM_LFIR filter singlebit, cs_root_cause +{ + /** MEM_LFIR[0] + * CFIR internal parity error + */ + (rMEM_LFIR, bit(0)) ? threshold_and_mask_self; + + /** MEM_LFIR[1] + * GPIO (PCB error) + */ + (rMEM_LFIR, bit(1)) ? defaultMaskedError; + + /** MEM_LFIR[2] + * CC (PCB error) + */ + (rMEM_LFIR, bit(2)) ? defaultMaskedError; + + /** MEM_LFIR[3] + * CC (OPCG, parity, scan collision, ...) + */ + (rMEM_LFIR, bit(3)) ? defaultMaskedError; + + /** MEM_LFIR[4] + * PSC (PCB error) + */ + (rMEM_LFIR, bit(4)) ? defaultMaskedError; + + /** MEM_LFIR[5] + * PSC (parity error) + */ + (rMEM_LFIR, bit(5)) ? defaultMaskedError; + + /** MEM_LFIR[6] + * Thermal (parity error) + */ + (rMEM_LFIR, bit(6)) ? defaultMaskedError; + + /** MEM_LFIR[7] + * Thermal (PCB error) + */ + (rMEM_LFIR, bit(7)) ? defaultMaskedError; + + /** MEM_LFIR[8] + * Thermal (critical trip error) + */ + (rMEM_LFIR, bit(8)) ? defaultMaskedError; + + /** MEM_LFIR[9] + * Thermal (fatal trip error) + */ + (rMEM_LFIR, bit(9)) ? defaultMaskedError; + + /** MEM_LFIR[10] + * Thermal (voltage trip error) + */ + (rMEM_LFIR, bit(10)) ? defaultMaskedError; + + /** MEM_LFIR[11] + * MBA01 Trace Array ( error) + */ + (rMEM_LFIR, bit(11)) ? defaultMaskedError; + + /** MEM_LFIR[12] + * MBA01 Trace Array ( error) + */ + (rMEM_LFIR, bit(12)) ? defaultMaskedError; + + /** MEM_LFIR[13] + * MBA23 Trace Array ( error) + */ + (rMEM_LFIR, bit(13)) ? defaultMaskedError; + + /** MEM_LFIR[14] + * MBA23 Trace Array ( error) + */ + (rMEM_LFIR, bit(14)) ? defaultMaskedError; + + /** MEM_LFIR[15:39] + * Reserved + */ + (rMEM_LFIR, bit(15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? defaultMaskedError; + + /** MEM_LFIR[40] + * malfunction alert (local xstop in another chiplet) + */ + (rMEM_LFIR, bit(40)) ? defaultMaskedError; + }; # Import all of the chiplet rules and actions diff --git a/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_MEM.rule b/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_MEM.rule deleted file mode 100755 index f069dc465..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_MEM.rule +++ /dev/null @@ -1,207 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_MEM.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -################################################################################ -# MEM Chiplet Registers -################################################################################ - -rule MemChipletFir -{ - CHECK_STOP: - (MEM_CHIPLET_CS_FIR & `17fc000000000000`) & ~MEM_CHIPLET_FIR_MASK; - UNIT_CS: - (MEM_CHIPLET_CS_FIR & `17fc000000000000`) & ~MEM_CHIPLET_FIR_MASK; - RECOVERABLE: - ((MEM_CHIPLET_RE_FIR >> 2) & `17f0000000000000`) & ~MEM_CHIPLET_FIR_MASK; -}; - -group gMemChipletFir filter singlebit -{ - /** MEM_CHIPLET_FIR[3] - * Attention from LFIR - */ - (MemChipletFir, bit(3)) ? analyze(gMemLFir); - - /** MEM_CHIPLET_FIR[5] - * Attention from MBACALFIR (MBA 01) - */ - (MemChipletFir, bit(5)) ? analyzeMba0; - - /** MEM_CHIPLET_FIR[6] - * Attention from MBAFIR (MBA 01) - */ - (MemChipletFir, bit(6)) ? analyzeMba0; - - /** MEM_CHIPLET_FIR[7] - * Attention from MBACALFIR (MBA 23) - */ - (MemChipletFir, bit(7)) ? analyzeMba1; - - /** MEM_CHIPLET_FIR[8] - * Attention from MBAFIR (MBA 23) - */ - (MemChipletFir, bit(8)) ? analyzeMba1; - - /** MEM_CHIPLET_FIR[9] - * Attention from DDRPHYFIR (MBA 01) - */ - (MemChipletFir, bit(9)) ? analyzeMba0; - - /** MEM_CHIPLET_FIR[10] - * Attention from DDRPHYFIR (MBA 23) - */ - (MemChipletFir, bit(10)) ? analyzeMba1; - - /** MEM_CHIPLET_FIR[11] - * Attention from MEMFBISTFIR - */ - (MemChipletFir, bit(11)) ? defaultMaskedError; - - /** MEM_CHIPLET_FIR[12] - * Attention from MBASECUREFIR (MBA 01) - */ - (MemChipletFir, bit(12)) ? analyzeMba0; # Checkstop only - - /** MEM_CHIPLET_FIR[13] - * Attention from MBASECUREFIR (MBA 23) - */ - (MemChipletFir, bit(13)) ? analyzeMba1; # Checkstop only -}; - -rule MemChipletSpa -{ - SPECIAL: MEM_CHIPLET_SPA & ~MEM_CHIPLET_SPA_MASK; -}; - -group gMemChipletSpa filter singlebit -{ - /** MEM_CHIPLET_SPA[0] - * Attention from Mba 01 - */ - (MemChipletSpa, bit(0)) ? analyzeMba0; - - /** MEM_CHIPLET_SPA[1] - * Attention from Mba 1 - */ - (MemChipletSpa, bit(1)) ? analyzeMba1; -}; - -################################################################################ -# MEM Chiplet LFIR -################################################################################ -# RAS spreadsheet: p8dd1_mss_FFDC_37_ reviewd.xls - -rule MemLFir -{ - CHECK_STOP: MEM_LFIR & ~MEM_LFIR_MASK & ~MEM_LFIR_ACT0 & ~MEM_LFIR_ACT1; - UNIT_CS: MEM_LFIR & ~MEM_LFIR_MASK & ~MEM_LFIR_ACT0 & ~MEM_LFIR_ACT1; - RECOVERABLE: MEM_LFIR & ~MEM_LFIR_MASK & ~MEM_LFIR_ACT0 & MEM_LFIR_ACT1; -}; - -group gMemLFir filter singlebit, - secondarybits(0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17, - 18,19,20,21,22,23,24,25,26,27,28,29,30,31,32, - 33,34,35,36,37,38,39,40) -{ - /** MEM_LFIR[0] - * CFIR internal parity error - */ - (MemLFir, bit(0)) ? thresholdAndMask_self; - - /** MEM_LFIR[1] - * Local errors from GPIO (PCB error) - */ - (MemLFir, bit(1)) ? defaultMaskedError; - - /** MEM_LFIR[2] - * Local errors from CC (PCB error) - */ - (MemLFir, bit(2)) ? defaultMaskedError; - - /** MEM_LFIR[3] - * Local errors from CC (OPCG, parity, scan collision, ...) - */ - (MemLFir, bit(3)) ? defaultMaskedError; - - /** MEM_LFIR[4] - * Local errors from PSC (PCB error) - */ - (MemLFir, bit(4)) ? defaultMaskedError; - - /** MEM_LFIR[5] - * Local errors from PSC (parity error) - */ - (MemLFir, bit(5)) ? defaultMaskedError; - - /** MEM_LFIR[6] - * Local errors from Thermal (parity error) - */ - (MemLFir, bit(6)) ? defaultMaskedError; - - /** MEM_LFIR[7] - * Local errors from Thermal (PCB error) - */ - (MemLFir, bit(7)) ? defaultMaskedError; - - /** MEM_LFIR[8:10] - * Local errors from Thermal (Trip error) - */ - (MemLFir, bit(8|9|10)) ? defaultMaskedError; - - /** MEM_LFIR[11:12] - * Local errors from MBA01 Trace Array ( error) - */ - (MemLFir, bit(11|12)) ? defaultMaskedError; - - /** MEM_LFIR[13:14] - * Local errors from MBA23 Trace Array ( error) - */ - (MemLFir, bit(13|14)) ? defaultMaskedError; - - /** MEM_LFIR[40] - * Malfunction alert - */ - (MemLFir, bit(40)) ? defaultMaskedError; -}; - -################################################################################ -# Actions specific to MEM chiplet -################################################################################ - -/** Analyze connected MBA0 */ -actionclass analyzeMba0 -{ - try ( funccall("MBA1_Starvation"), - analyze(connected(TYPE_MBA, 0)) ); -}; - -/** Analyze connected MBA1 */ -# No need to address starvation issue here -# because MBA0 is not at attention -actionclass analyzeMba1 -{ - analyze(connected(TYPE_MBA, 1)); -}; - diff --git a/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_NEST.rule b/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_NEST.rule index 33c9fb1d3..920276ccd 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_NEST.rule +++ b/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_NEST.rule @@ -24,1254 +24,9 @@ # IBM_PROLOG_END_TAG ################################################################################ -# NEST Chiplet Registers -################################################################################ - -rule NestChipletFir -{ - CHECK_STOP: - (NEST_CHIPLET_CS_FIR & `17fe000000000000`) & ~NEST_CHIPLET_FIR_MASK; - UNIT_CS: - (NEST_CHIPLET_CS_FIR & `17fe000000000000`) & ~NEST_CHIPLET_FIR_MASK; - RECOVERABLE: - ((NEST_CHIPLET_RE_FIR >> 2) & `17fc000000000000`) & ~NEST_CHIPLET_FIR_MASK; -}; - -group gNestChipletFir filter priority( 3, 6, 5, 7 ) -{ - # NOTE: The MBIFIR must be analyzed before the DMIFIR and both the MBIFIR - # and DMIFIR must be analyzed before the MBSFIR. All other FIRs will be - # analyzed in order. - - /** NEST_CHIPLET_FIR[3] - * Attention from LFIR - */ - (NestChipletFir, bit(3)) ? analyze(gNestLFir); - - /** NEST_CHIPLET_FIR[5] - * Attention from DMIFIR - */ - (NestChipletFir, bit(5)) ? analyze(gDmiFir); - - /** NEST_CHIPLET_FIR[6] - * Attention from MBIFIR - */ - (NestChipletFir, bit(6)) ? analyze(gMbiFir); - - /** NEST_CHIPLET_FIR[7] - * Attention from MBSFIR - */ - (NestChipletFir, bit(7)) ? analyze(gMbsFir); - - /** NEST_CHIPLET_FIR[8|9] - * Attention from MCBISTFIRs - */ - (NestChipletFir, bit(8|9)) ? analyze(gMcbistFir); - - /** NEST_CHIPLET_FIR[10|11] - * Attention from MBSECCFIRs - */ - (NestChipletFir, bit(10|11)) ? analyze(gMbsEccFir); - - /** NEST_CHIPLET_FIR[12] - * Attention from NESTFBISTFIR - */ - (NestChipletFir, bit(12))? defaultMaskedError; - - /** NEST_CHIPLET_FIR[13] - * Attention from SCACFIR - */ - (NestChipletFir, bit(13)) ? analyze(gScacFir); - - /** NEST_CHIPLET_FIR[14] - * Attention from MBS secure FIR - */ - (NestChipletFir, bit(14))? analyze(gMbsSecureFir); # Checkstop only -}; - -################################################################################ -# NEST Chiplet LFIR -################################################################################ -# RAS spreadsheet: p8dd1_mss_FFDC_37_ reviewd.xls - -rule NestLFir -{ - CHECK_STOP: NEST_LFIR & ~NEST_LFIR_MASK & ~NEST_LFIR_ACT0 & ~NEST_LFIR_ACT1; - UNIT_CS: NEST_LFIR & ~NEST_LFIR_MASK & ~NEST_LFIR_ACT0 & ~NEST_LFIR_ACT1; - RECOVERABLE: NEST_LFIR & ~NEST_LFIR_MASK & ~NEST_LFIR_ACT0 & NEST_LFIR_ACT1; -}; - -group gNestLFir filter singlebit, - secondarybits(0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16, - 17,18,19,20,21,22,23,24,25,26,27,28,29,30, - 31,32,33,34,35,36,37,38,39,40) -{ - /** NEST_LFIR[0] - * CFIR internal parity error - */ - (NestLFir, bit(0)) ? thresholdAndMask_self; - - /** NEST_LFIR[1] - * Local errors from GPIO (PCB error) - */ - (NestLFir, bit(1)) ? defaultMaskedError; - - /** NEST_LFIR[2] - * Local errors from CC (PCB error) - */ - (NestLFir, bit(2)) ? defaultMaskedError; - - /** NEST_LFIR[3] - * Local errors from CC (OPCG, parity, scan collision, ...) - */ - (NestLFir, bit(3)) ? defaultMaskedError; - - /** NEST_LFIR[4] - * Local errors from PSC (PCB error) - */ - (NestLFir, bit(4)) ? defaultMaskedError; - - /** NEST_LFIR[5] - * Local errors from PSC (parity error) - */ - (NestLFir, bit(5)) ? defaultMaskedError; - - /** NEST_LFIR[6] - * Local errors from Thermal (parity error) - */ - (NestLFir, bit(6)) ? defaultMaskedError; - - /** NEST_LFIR[7] - * Local errors from Thermal (PCB error) - */ - (NestLFir, bit(7)) ? defaultMaskedError; - - /** NEST_LFIR[8:10] - * Local errors from Thermal (Trip error) - */ - (NestLFir, bit(8|9|10)) ? defaultMaskedError; - - /** NEST_LFIR[11:12] - * Local errors from Trace Array ( error) - */ - (NestLFir, bit(11|12)) ? defaultMaskedError; - - /** NEST_LFIR[40] - * Malfunction alert - */ - (NestLFir, bit(40)) ? defaultMaskedError; -}; - -################################################################################ -# NEST Chiplet DMIFIR -################################################################################ -# RAS spreadsheet: p8dd1_mss_FFDC_37_ reviewd.xls - -rule DmiFir -{ - CHECK_STOP: DMIFIR & ~DMIFIR_MASK & ~DMIFIR_ACT0 & ~DMIFIR_ACT1; - UNIT_CS: DMIFIR & ~DMIFIR_MASK & ~DMIFIR_ACT0 & ~DMIFIR_ACT1; - RECOVERABLE: DMIFIR & ~DMIFIR_MASK & ~DMIFIR_ACT0 & DMIFIR_ACT1; -}; - -group gDmiFir filter priority( 10, # Channel failure - 2, 11, 12, 9 ), # Recoverable - secondarybits(0,1,3,4,5,6,7,8,9,11,12,13,14,15,16,17,18,19, - 20,21,22,23,24,25,26,27,28,29,30,31,32,33,34, - 35,36,37,38,39,40,41,42,43,44,45,46,47,48,49) -{ - /** DMIFIR[0] - * FIR_RX_INVALID_STATE_OR_PARITY_ERROR - */ - (DmiFir, bit(0)) ? defaultMaskedError; - - /** DMIFIR[1] - * FIR_TX_INVALID_STATE_OR_PARITY_ERROR - */ - (DmiFir, bit(1)) ? defaultMaskedError; - - /** DMIFIR[2] - * FIR_GCR_HANG_ERROR - */ - (DmiFir, bit(2)) ? SelfHighThr1; - - /** DMIFIR[3:7] - * Reserved - */ - (DmiFir, bit(3|4|5|6|7)) ? defaultMaskedError; - - /** DMIFIR[8] - * Training Error - */ - (DmiFir, bit(8)) ? defaultMaskedError; - - /** DMIFIR[9] - * Spare Deployed - */ - (DmiFir, bit(9)) ? spareDeployed; - - /** DMIFIR[10] - * Max Spares Exceeded - */ - (DmiFir, bit(10)) ? maxSparesExceeded; - - /** DMIFIR[11] - * Recalibration or Dynamic Repair Error - */ - (DmiFir, bit(11)) ? calloutDmiBusTh1; - - /** DMIFIR[12] - * Too Many Bus Errors - */ - (DmiFir, bit(12)) ? calloutDmiBusTh1; - - /** DMIFIR[13:15] - * Reserved - */ - (DmiFir, bit(13|14|15)) ? defaultMaskedError; - - /** DMIFIR[16:23] - * FIR_RX_BUS1 unused - */ - (DmiFir, bit(16|17|18|19|20|21|22|23)) ? defaultMaskedError; - - /** DMIFIR[24:31] - * FIR_RX_BUS2 unused - */ - (DmiFir, bit(24|25|26|27|28|29|30|31)) ? defaultMaskedError; - - /** DMIFIR[32:39] - * FIR_RX_BUS3 unused - */ - (DmiFir, bit(32|33|34|35|36|37|38|39)) ? defaultMaskedError; - - /** DMIFIR[40:47] - * FIR_RX_BUS4 unused - */ - (DmiFir, bit(40|41|42|43|44|45|46|47)) ? defaultMaskedError; - - /** DMIFIR[48] - * FIR_SCOMFIR_ERROR - */ - (DmiFir, bit(48)) ? thresholdAndMask_self; - - /** DMIFIR[49] - * FIR_SCOMFIR_ERROR_CLONE - */ - (DmiFir, bit(49)) ? thresholdAndMask_self; -}; - -################################################################################ -# NEST Chiplet ScacFir -################################################################################ - -rule ScacFir -{ - CHECK_STOP: SCACFIR & ~SCACFIR_MASK & ~SCACFIR_ACT0 & ~SCACFIR_ACT1; - UNIT_CS: SCACFIR & ~SCACFIR_MASK & ~SCACFIR_ACT0 & ~SCACFIR_ACT1; - RECOVERABLE: SCACFIR & ~SCACFIR_MASK & ~SCACFIR_ACT0 & SCACFIR_ACT1; -}; - -group gScacFir filter singlebit, - secondarybits(0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17, - 18,19,20,21,22,23,24,27,28,29,30,31,32,33, - 34,35,36) -{ - /** SCACFIR[0] - * SCAC_LFIR_I2CMINVADDR - */ - (ScacFir, bit(0)) ? defaultMaskedError; - - /** SCACFIR[1] - * SCAC_LFIR_I2CMINVWRITE - */ - (ScacFir, bit(1)) ? defaultMaskedError; - - /** SCACFIR[2] - * SCAC_LFIR_I2CMINVREAD - */ - (ScacFir, bit(2)) ? defaultMaskedError; - - /** SCACFIR[3] - * SCAC_LFIR_I2CMAPAR - */ - (ScacFir, bit(3)) ? defaultMaskedError; - - /** SCACFIR[4] - * SCAC_LFIR_I2CMPAR - */ - (ScacFir, bit(4)) ? defaultMaskedError; - - /** SCACFIR[5] - * SCAC_LFIR_I2CMLBPAR - */ - (ScacFir, bit(5)) ? defaultMaskedError; - - /** SCACFIR[6:9] - * Expansion (Reserved at 0 for exernal macro expansion reporting) - */ - (ScacFir, bit(6|7|8|9)) ? defaultMaskedError; - - /** SCACFIR[10] - * SCAC_LFIR_I2CMINVCMD - */ - (ScacFir, bit(10)) ? defaultMaskedError; - - /** SCACFIR[11] - * SCAC_LFIR_I2CMPERR - */ - (ScacFir, bit(11)) ? defaultMaskedError; - - /** SCACFIR[12] - * SCAC_LFIR_I2CMOVERRUN - */ - (ScacFir, bit(12)) ? defaultMaskedError; - - /** SCACFIR[13] - * SCAC_LFIR_I2CMACCESS - */ - (ScacFir, bit(13)) ? defaultMaskedError; - - /** SCACFIR[14] - * SCAC_LFIR_I2CMARB - */ - (ScacFir, bit(14)) ? defaultMaskedError; - - /** SCACFIR[15] - * SCAC_LFIR_I2CMNACK - */ - (ScacFir, bit(15)) ? defaultMaskedError; - - /** SCACFIR[16] - * SCAC_LFIR_I2CMSTOP - */ - (ScacFir, bit(16)) ? defaultMaskedError; - - /** SCACFIR[17] - * SCAC_LFIR_LOCALPIB1 - */ - (ScacFir, bit(17)) ? defaultMaskedError; - - /** SCACFIR[18] - * SCAC_LFIR_LOCALPIB2 - */ - (ScacFir, bit(18)) ? defaultMaskedError; - - /** SCACFIR[19] - * SCAC_LFIR_LOCALPIB3 - */ - (ScacFir, bit(19)) ? defaultMaskedError; - - /** SCACFIR[20] - * SCAC_LFIR_LOCALPIB4 - */ - (ScacFir, bit(20)) ? defaultMaskedError; - - /** SCACFIR[21] - * SCAC_LFIR_LOCALPIB5 - */ - (ScacFir, bit(21)) ? defaultMaskedError; - - /** SCACFIR[22] - * SCAC_LFIR_LOCALPIB6 - */ - (ScacFir, bit(22)) ? defaultMaskedError; - - /** SCACFIR[23] - * SCAC_LFIR_LOCALPIB7 - */ - (ScacFir, bit(23)) ? defaultMaskedError; - - /** SCACFIR[24] - * SCAC_LFIR_STALLERROR - */ - (ScacFir, bit(24)) ? defaultMaskedError; - - /** SCACFIR[25] - * SCAC_LFIR_REGPARERR - */ - (ScacFir, bit(25)) ? SelfMedThr1UE; - - /** SCACFIR[26] - * SCAC_LFIR_REGPARERRX - */ - (ScacFir, bit(26)) ? SelfMedThr1UE; - - /** SCACFIR[32] - * SCAC_LFIR_SMERR - */ - (ScacFir, bit(32)) ? SelfMedThr1; - - /** SCACFIR[33] - * SCAC_LFIR_REGACCERR - */ - (ScacFir, bit(33)) ? callout2ndLvlMedThr1dumpSh; - - /** SCACFIR[34] - * SCAC_LFIR_RESETERR - */ - (ScacFir, bit(34)) ? defaultMaskedError; - - /** SCACFIR[35] - * SCAC_LFIR_INTERNAL_SCOM_ERROR - */ - (ScacFir, bit(35)) ? thresholdAndMask_self; - - /** SCACFIR[36] - * SCAC_LFIR_INTERNAL_SCOM_ERROR_CLONE - */ - (ScacFir, bit(36)) ? thresholdAndMask_self; -}; - -################################################################################ -# NEST Chiplet MBIFIR -################################################################################ -# RAS spreadsheet: p8dd1_mss_FFDC_37_ reviewd.xls - -rule MbiFir -{ - CHECK_STOP: MBIFIR & ~MBIFIR_MASK & ~MBIFIR_ACT0 & ~MBIFIR_ACT1; - UNIT_CS: MBIFIR & ~MBIFIR_MASK & ~MBIFIR_ACT0 & ~MBIFIR_ACT1; - RECOVERABLE: MBIFIR & ~MBIFIR_MASK & ~MBIFIR_ACT0 & MBIFIR_ACT1; -}; - -group gMbiFir filter priority( 8, 9, 19, 20, 6, 0, # Channel failure - 16, 5, 10 ), # Recoverable - secondarybits(1,2,3,4,5,7,10,11,12,13,14,15,16,17,18,21,22, - 23,24,25,26) -{ - /** MBIFIR[0] - * MBIFIRQ_REPLAY_TIMEOUT - */ - (MbiFir, bit(0)) ? replayTimeOutError; - - /** MBIFIR[1] - * MBIFIRQ_CHANNEL_FAIL - */ - (MbiFir, bit(1)) ? defaultMaskedError; - - /** MBIFIR[2] - * MBIFIRQ_CRC_ERROR - */ - (MbiFir, bit(2)) ? defaultMaskedError; - - /** MBIFIR[3] - * MBIFIRQ_FRAME_NOACK - */ - (MbiFir, bit(3)) ? defaultMaskedError; - - /** MBIFIR[4] - * MBIFIRQ_SEQID_OUT_OF_ORDER - */ - (MbiFir, bit(4)) ? defaultMaskedError; - - /** MBIFIR[5] - * MBIFIRQ_REPLAY_BUFFER_ECC_CE - */ - (MbiFir, bit(5)) ? SelfMedThr5PerHour; - - /** MBIFIR[6] - * MBIFIRQ_REPLAY_BUFFER_ECC_UE - */ - (MbiFir, bit(6)) ? SelfMedThr1UE; - - /** MBIFIR[7] - * MBIFIRQ_MBI_STATE_MACHINE_TIMEOUT - */ - (MbiFir, bit(7)) ? defaultMaskedError; - - /** MBIFIR[8] - * MBIFIRQ_MBI_INTERNAL_CONTROL_PARITY_ERROR - */ - (MbiFir, bit(8)) ? SelfMedThr1UE; - - /** MBIFIR[9] - * MBIFIRQ_MBI_DATA_FLOW_PARITY_ERROR - */ - (MbiFir, bit(9)) ? SelfMedThr1UE; - - /** MBIFIR[10] - * MBIFIRQ_CRC_PERFORMANCE_DEGRADATION - */ - (MbiFir, bit(10)) ? analyzeSpareBitAndThr; - - /** MBIFIR[11] - * MBIFIRQ_HOST_MC_GLOBAL_CHECKSTOP - */ - (MbiFir, bit(11)) ? defaultMaskedError; - - /** MBIFIR[12] - * MBIFIRQ_HOST_MC_TRACESTOP - */ - (MbiFir, bit(12)) ? defaultMaskedError; - - /** MBIFIR[13] - * MBIFIRQ_CHANNEL_INTERLOCK_FAIL - */ - (MbiFir, bit(13)) ? defaultMaskedError; - - /** MBIFIR[14] - * MBIFIRQ_HOST_MC_LOCAL_CHECKSTOP - */ - (MbiFir, bit(14)) ? defaultMaskedError; - - /** MBIFIR[15] - * MBIFIRQ_FRTL_CONTER_OVERFLOW - */ - (MbiFir, bit(15)) ? defaultMaskedError; - - /** MBIFIR[16] - * MBIFIRQ_SCOM_REGISTER_PARITY_ERROR - */ - (MbiFir, bit(16)) ? SelfMedThr1; - - /** MBIFIR[17] - * MBIFIRQ_IO_FAULT: IO to MBI - */ - (MbiFir, bit(17)) ? defaultMaskedError; - - /** MBIFIR[18] - * MBIFIRQ_MULTIPLE_REPLAY - */ - (MbiFir, bit(18)) ? defaultMaskedError; - - /** MBIFIR[19] - * MBIFIRQ_MBICFG_PARITY_SCOM_ERROR - */ - (MbiFir, bit(19)) ? SelfMedThr1UE; - - /** MBIFIR[20] - * MBIFIRQ_BUFFER_OVERRUN_ERROR - */ - (MbiFir, bit(20)) ? calloutDmiBusTh1UE; - - # This is for DD2 only - /** MBIFIR[21] - * MBIFIRQ_WAT_ERROR - */ - (MbiFir, bit(21)) ? defaultMaskedError; - - /** MBIFIR[22:24] - * Reserved - */ - (MbiFir, bit(22|23|24)) ? defaultMaskedError; - - /** MBIFIR[25] - * MBIFIRQ_INTERNAL_SCOM_ERROR_CLONE - */ - (MbiFir, bit(25)) ? thresholdAndMask_self; - - /** MBIFIR[26] - * MBIFIRQ_INTERNAL_SCOM_ERROR_CLONE_COPY - */ - (MbiFir, bit(26)) ? thresholdAndMask_self; -}; - -################################################################################ -# NEST Chiplet MBSFIR -################################################################################ -# RAS spreadsheet: p8dd1_mss_FFDC_37_ reviewd.xls -rule MbsFir -{ - CHECK_STOP: MBSFIR & ~MBSFIR_MASK & ~MBSFIR_ACT0 & ~MBSFIR_ACT1; - UNIT_CS: MBSFIR & ~MBSFIR_MASK & ~MBSFIR_ACT0 & ~MBSFIR_ACT1; - RECOVERABLE: MBSFIR & ~MBSFIR_MASK & ~MBSFIR_ACT0 & MBSFIR_ACT1; -}; - -group gMbsFir filter singlebit, - secondarybits(3,5,7,9,11,12,14,15,17,19,21,22,23,24,25,26, - 28,29,31,32,33,34) -{ - /** MBSFIR[0] - * MBS_FIR_REG_HOST_PROTOCOL_ERROR - */ - (MbsFir, bit(0)) ? calloutDmiBusTh1UE; - - /** MBSFIR[1] - * MBS_FIR_REG_INT_PROTOCOL_ERROR - */ - (MbsFir, bit(1)) ? SelfMedThr1UE; - - /** MBSFIR[2] - * MBS_FIR_REG_INVALID_ADDRESS_ERROR - */ - (MbsFir, bit(2)) ? calloutDmiBusTh1; - - /** MBSFIR[3] - * MBS_FIR_REG_EXTERNAL_TIMEOUT - */ - (MbsFir, bit(3)) ? callout2ndLvlMedThr1; - - /** MBSFIR[4] - * MBS_FIR_REG_INTERNAL_TIMEOUT - */ - (MbsFir, bit(4)) ? internalTimeout; - - /** MBSFIR[3,4] - * MBS_FIR_REG_EXTERNAL_TIMEOUT - */ - # NOTE: The signature will match the external timeout, but we will still - # call the internalTimeout plugin because there is extra processing - # done to handle parity errors and such. - (MbsFir, bit(3,4)) ? internalTimeout; - - /** MBSFIR[5] - * MBS_FIR_REG_INT_BUFFER_CE - */ - (MbsFir, bit(5)) ? SelfMedThr32PerDay; - - /** MBSFIR[6] - * MBS_FIR_REG_INT_BUFFER_UE - */ - (MbsFir, bit(6)) ? SelfMedThr1UE; - - /** MBSFIR[7] - * MBS_FIR_REG_INT_BUFFER_SUE - */ - (MbsFir, bit(7)) ? defaultMaskedError; - - /** MBSFIR[8] - * MBS_FIR_REG_INT_PARITY_ERROR - */ - (MbsFir, bit(8)) ? SelfMedThr1UE; - - /** MBSFIR[9] - * MBS_FIR_REG_CACHE_SRW_CE - */ - (MbsFir, bit(9)) ? l4_cache_srw_ce; - - /** MBSFIR[10] - * MBS_FIR_REG_CACHE_SRW_UE - */ - (MbsFir, bit(10)) ? l4_cache_srw_ue_UERE; - - /** MBSFIR[11] - * MBS_FIR_REG_CACHE_SRW_SUE - */ - (MbsFir, bit(11)) ? defaultMaskedError; - - /** MBSFIR[12] - * MBS_FIR_REG_CACHE_CO_CE - */ - (MbsFir, bit(12)) ? l4_cache_co_ce; - - /** MBSFIR[13] - * MBS_FIR_REG_CACHE_CO_UE - */ - (MbsFir, bit(13)) ? l4_cache_co_ue_UERE; - - /** MBSFIR[14] - * MBS_FIR_REG_CACHE_CO_SUE - */ - (MbsFir, bit(14)) ? defaultMaskedError; - - /** MBSFIR[15] - * MBS_FIR_REG_DIR_CE - */ - (MbsFir, bit(15)) ? L4CalloutMedThr32PerDay; - - /** MBSFIR[16] - * MBS_FIR_REG_DIR_UE - */ - (MbsFir, bit(16)) ? L4CalloutMedThr1UE; - - /** MBSFIR[17] - * MBS_FIR_REG_DIR_MEMBER_DELETED - */ - (MbsFir, bit(17)) ? defaultMaskedError; - - /** MBSFIR[18] - * MBS_FIR_REG_DIR_ALL_MEMBERS_DELETED - */ - (MbsFir, bit(18)) ? L4CalloutMedThr1UE; - - /** MBSFIR[19] - * MBS_FIR_REG_LRU_ERROR - */ - (MbsFir, bit(19)) ? L4CalloutMedThr32PerDay; - - /** MBSFIR[20] - * MBS_FIR_REG_EDRAM_ERROR - */ - (MbsFir, bit(20)) ? L4CalloutMedThr1UE; - - /** MBSFIR[21] - * MBS_FIR_REG_EMERGENCY_THROTTLE_SET - */ - (MbsFir, bit(21)) ? defaultMaskedError; - - /** MBSFIR[22] - * MBS_FIR_REG_HOST_INBAND_READ_ERROR - */ - (MbsFir, bit(22)) ? defaultMaskedError; - - /** MBSFIR[23] - * MBS_FIR_REG_HOST_INBAND_WRITE_ERROR - */ - (MbsFir, bit(23)) ? defaultMaskedError; - - /** MBSFIR[24] - * MBS_FIR_REG_OCC_INBAND_READ_ERROR - */ - (MbsFir, bit(24)) ? defaultMaskedError; - - /** MBSFIR[25] - * MBS_FIR_REG_OCC_INBAND_WRITE_ERROR - */ - (MbsFir, bit(25)) ? defaultMaskedError; - - /** MBSFIR[26] - * MBS_FIR_REG_SRB_BUFFER_CE - */ - (MbsFir, bit(26)) ? thresholdAndMask_self; - - /** MBSFIR[27] - * MBS_FIR_REG_SRB_BUFFER_UE - */ - (MbsFir, bit(27)) ? SelfMedThr1UE; - - /** MBSFIR[28] - * MBS_FIR_REG_SRB_BUFFER_SUE - */ - (MbsFir, bit(28)) ? defaultMaskedError; - - /** MBSFIR[29] - * DD1: MBS_FIR_REG_INTERNAL_SCOM_ERROR - */ - (MbsFir, bit(29)) ? thresholdAndMask_self; # DD1 action, masked for DD2+ - - /** MBSFIR[30] - * MBS_FIR_REG_PROXIMAL_CE_UE - */ - (MbsFir, bit(30)) ? mbsfirBit30; - - # This is for DD2 only - /** MBSFIR[31] - * MBS_FIR_REG_SPARE_FIR31 - */ - (MbsFir, bit(31)) ? defaultMaskedError; - - # This is for DD2 only - /** MBSFIR[32] - * MBS_FIR_REG_SPARE_FIR32 - */ - (MbsFir, bit(32)) ? defaultMaskedError; - - # This is for DD2 only - /** MBSFIR[33] - * MBS_FIR_REG_INTERNAL_SCOM_ERROR - */ - (MbsFir, bit(33)) ? thresholdAndMask_self; - - # This is for DD2 only - /** MBSFIR[34] - * MBS_FIR_REG_INTERNAL_SCOM_ERROR_COPY - */ - (MbsFir, bit(34)) ? thresholdAndMask_self; -}; - -################################################################################ -# NEST Chiplet MBSECCFIRs -################################################################################ -# RAS spreadsheet: p8dd1_mss_FFDC_37_ reviewd.xls - -rule Mba0_MbsEccFir -{ - CHECK_STOP: MBSECCFIR_0 & ~MBSECCFIR_0_MASK & - ~MBSECCFIR_0_ACT0 & ~MBSECCFIR_0_ACT1; - UNIT_CS: MBSECCFIR_0 & ~MBSECCFIR_0_MASK & - ~MBSECCFIR_0_ACT0 & ~MBSECCFIR_0_ACT1; - RECOVERABLE: MBSECCFIR_0 & ~MBSECCFIR_0_MASK & - ~MBSECCFIR_0_ACT0 & MBSECCFIR_0_ACT1; -}; - -rule Mba1_MbsEccFir -{ - CHECK_STOP: MBSECCFIR_1 & ~MBSECCFIR_1_MASK & - ~MBSECCFIR_1_ACT0 & ~MBSECCFIR_1_ACT1; - UNIT_CS: MBSECCFIR_1 & ~MBSECCFIR_1_MASK & - ~MBSECCFIR_1_ACT0 & ~MBSECCFIR_1_ACT1; - RECOVERABLE: MBSECCFIR_1 & ~MBSECCFIR_1_MASK & - ~MBSECCFIR_1_ACT0 & MBSECCFIR_1_ACT1; -}; - -group gMbsEccFir filter priority ( 19, 41 ), - secondarybits(0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16, - 17,18,20,21,22,23,24,25,26,27,28,29,30,31, - 32,33,34,35,36,37,38,39,40,41,42,43,44,45, - 48,50,51) -{ - /** MBSECCFIR_0[0] - * Memory chip mark on rank 0 - */ - (Mba0_MbsEccFir, bit(0)) ? analyzeFetchMpe0_0; - - /** MBSECCFIR_1[0] - * Memory chip mark on rank 0 - */ - (Mba1_MbsEccFir, bit(0)) ? analyzeFetchMpe1_0; - - /** MBSECCFIR_0[1] - * Memory chip mark on rank 1 - */ - (Mba0_MbsEccFir, bit(1)) ? analyzeFetchMpe0_1; - - /** MBSECCFIR_1[1] - * Memory chip mark on rank 1 - */ - (Mba1_MbsEccFir, bit(1)) ? analyzeFetchMpe1_1; - - /** MBSECCFIR_0[2] - * Memory chip mark on rank 2 - */ - (Mba0_MbsEccFir, bit(2)) ? analyzeFetchMpe0_2; - - /** MBSECCFIR_1[2] - * Memory chip mark on rank 2 - */ - (Mba1_MbsEccFir, bit(2)) ? analyzeFetchMpe1_2; - - /** MBSECCFIR_0[3] - * Memory chip mark on rank 3 - */ - (Mba0_MbsEccFir, bit(3)) ? analyzeFetchMpe0_3; - - /** MBSECCFIR_1[3] - * Memory chip mark on rank 3 - */ - (Mba1_MbsEccFir, bit(3)) ? analyzeFetchMpe1_3; - - /** MBSECCFIR_0[4] - * Memory chip mark on rank 4 - */ - (Mba0_MbsEccFir, bit(4)) ? analyzeFetchMpe0_4; - - /** MBSECCFIR_1[4] - * Memory chip mark on rank 4 - */ - (Mba1_MbsEccFir, bit(4)) ? analyzeFetchMpe1_4; - - /** MBSECCFIR_0[5] - * Memory chip mark on rank 5 - */ - (Mba0_MbsEccFir, bit(5)) ? analyzeFetchMpe0_5; - - /** MBSECCFIR_1[5] - * Memory chip mark on rank 5 - */ - (Mba1_MbsEccFir, bit(5)) ? analyzeFetchMpe1_5; - - /** MBSECCFIR_0[6] - * Memory chip mark on rank 6 - */ - (Mba0_MbsEccFir, bit(6)) ? analyzeFetchMpe0_6; - - /** MBSECCFIR_1[6] - * Memory chip mark on rank 6 - */ - (Mba1_MbsEccFir, bit(6)) ? analyzeFetchMpe1_6; - - /** MBSECCFIR_0[7] - * Memory chip mark on rank 7 - */ - (Mba0_MbsEccFir, bit(7)) ? analyzeFetchMpe0_7; - - /** MBSECCFIR_1[7] - * Memory chip mark on rank 7 - */ - (Mba1_MbsEccFir, bit(7)) ? analyzeFetchMpe1_7; - - /** MBSECCFIR_0[8:15] - * Reserved - */ - (Mba0_MbsEccFir, bit(8|9|10|11|12|13|14|15)) ? defaultMaskedError; - - /** MBSECCFIR_1[8:15] - * Reserved - */ - (Mba1_MbsEccFir, bit(8|9|10|11|12|13|14|15)) ? defaultMaskedError; - - /** MBSECCFIR_0[16] - * Memory NCE - */ - (Mba0_MbsEccFir, bit(16)) ? analyzeFetchNce0; - - /** MBSECCFIR_1[16] - * Memory NCE - */ - (Mba1_MbsEccFir, bit(16)) ? analyzeFetchNce1; - - /** MBSECCFIR_0[17] - * Memory RCE - */ - (Mba0_MbsEccFir, bit(17)) ? analyzeFetchRce0; - - /** MBSECCFIR_1[17] - * Memory RCE - */ - (Mba1_MbsEccFir, bit(17)) ? analyzeFetchRce1; - - /** MBSECCFIR_0[18] - * Memory SUE - */ - (Mba0_MbsEccFir, bit(18)) ? defaultMaskedError; - - /** MBSECCFIR_1[18] - * Memory SUE - */ - (Mba1_MbsEccFir, bit(18)) ? defaultMaskedError; - - /** MBSECCFIR_0[19] - * Memory UE - */ - (Mba0_MbsEccFir, bit(19)) ? mba0MemoryUe; - - /** MBSECCFIR_1[19] - * Memory UE - */ - (Mba1_MbsEccFir, bit(19)) ? mba1MemoryUe; - - /** MBSECCFIR_0[20:27] - * Maintenance chip mark - */ - (Mba0_MbsEccFir, bit(20|21|22|23|24|25|26|27)) ? defaultMaskedError; - - /** MBSECCFIR_1[20:27] - * Maintenance chip mark - */ - (Mba1_MbsEccFir, bit(20|21|22|23|24|25|26|27)) ? defaultMaskedError; - - /** MBSECCFIR_0[28:35] - * Reserved - */ - (Mba0_MbsEccFir, bit(28|29|30|31|32|33|34|35)) ? defaultMaskedError; - - /** MBSECCFIR_1[28:35] - * Reserved - */ - (Mba1_MbsEccFir, bit(28|29|30|31|32|33|34|35)) ? defaultMaskedError; - - /** MBSECCFIR_0[36] - * Maintenance NCE - */ - (Mba0_MbsEccFir, bit(36)) ? defaultMaskedError; - - /** MBSECCFIR_1[36] - * Maintenance NCE - */ - (Mba1_MbsEccFir, bit(36)) ? defaultMaskedError; - - /** MBSECCFIR_0[37] - * Maintenance SCE - */ - (Mba0_MbsEccFir, bit(37)) ? defaultMaskedError; - - /** MBSECCFIR_1[37] - * Maintenance SCE - */ - (Mba1_MbsEccFir, bit(37)) ? defaultMaskedError; - - /** MBSECCFIR_0[38] - * Maintenance MCE - */ - (Mba0_MbsEccFir, bit(38)) ? defaultMaskedError; - - /** MBSECCFIR_1[38] - * Maintenance MCE - */ - (Mba1_MbsEccFir, bit(38)) ? defaultMaskedError; - - /** MBSECCFIR_0[39] - * Maintenance RCE - */ - (Mba0_MbsEccFir, bit(39)) ? defaultMaskedError; - - /** MBSECCFIR_1[39] - * Maintenance RCE - */ - (Mba1_MbsEccFir, bit(39)) ? defaultMaskedError; - - /** MBSECCFIR_0[40] - * Maintenance SUE - */ - (Mba0_MbsEccFir, bit(40)) ? defaultMaskedError; - - /** MBSECCFIR_1[40] - * Maintenance SUE - */ - (Mba1_MbsEccFir, bit(40)) ? defaultMaskedError; - - /** MBSECCFIR_0[41] - * Maintenance UE - */ - (Mba0_MbsEccFir, bit(41)) ? defaultMaskedError; - - /** MBSECCFIR_1[41] - * Maintenance UE - */ - (Mba1_MbsEccFir, bit(41)) ? defaultMaskedError; - - /** MBSECCFIR_0[42] - * MBECCFIR_MPE_DURING_USE_MAINTENANCE_MARK_MODE - */ - (Mba0_MbsEccFir, bit(42)) ? defaultMaskedError; - - /** MBSECCFIR_1[42] - * MBECCFIR_MPE_DURING_USE_MAINTENANCE_MARK_MODE - */ - (Mba1_MbsEccFir, bit(42)) ? defaultMaskedError; - - /** MBSECCFIR_0[43] - * MBECCFIR_PREFETCH_MEMORY_UE - */ - (Mba0_MbsEccFir, bit(43)) ? analyzeFetchPreUe0; - - /** MBSECCFIR_1[43] - * MBECCFIR_PREFETCH_MEMORY_UE - */ - (Mba1_MbsEccFir, bit(43)) ? analyzeFetchPreUe1; - - /** MBSECCFIR_0[44] - * MBECCFIR_MEMORY_RCD_PARITY_ERROR - */ - (Mba0_MbsEccFir, bit(44)) ? defaultMaskedError; - - /** MBSECCFIR_1[44] - * MBECCFIR_MEMORY_RCD_PARITY_ERROR - */ - (Mba1_MbsEccFir, bit(44)) ? defaultMaskedError; - - /** MBSECCFIR_0[45] - * MBECCFIR_MAINTENANCE_RCD_PARITY_ERROR - */ - (Mba0_MbsEccFir, bit(45)) ? defaultMaskedError; - - /** MBSECCFIR_1[45] - * MBECCFIR_MAINTENANCE_RCD_PARITY_ERROR - */ - (Mba1_MbsEccFir, bit(45)) ? defaultMaskedError; - - /** MBSECCFIR_0[46] - * MBECCFIR_RECOVERABLE_CONFIGURATION_REGISTER_PARITY_ERROR - */ - (Mba0_MbsEccFir, bit(46)) ? MBA0CalloutMedThr1; - - /** MBSECCFIR_1[46] - * MBECCFIR_RECOVERABLE_CONFIGURATION_REGISTER_PARITY_ERROR - */ - (Mba1_MbsEccFir, bit(46)) ? MBA1CalloutMedThr1; - - /** MBSECCFIR_0[47] - * MBECCFIR_UNRECOVERABLE_CONFIGURATION_REGISTER_PARITY_ERROR - */ - (Mba0_MbsEccFir, bit(47)) ? MBA0CalloutMedThr1UE; - - /** MBSECCFIR_1[47] - * MBECCFIR_UNRECOVERABLE_CONFIGURATION_REGISTER_PARITY_ERROR - */ - (Mba1_MbsEccFir, bit(47)) ? MBA1CalloutMedThr1UE; - - /** MBSECCFIR_0[48] - * MBECCFIR_MASKABLE_CONFIGURATION_REGISTER_PARITY_ERROR - */ - (Mba0_MbsEccFir, bit(48)) ? thresholdAndMask_mba0; - - /** MBSECCFIR_1[48] - * MBECCFIR_MASKABLE_CONFIGURATION_REGISTER_PARITY_ERROR - */ - (Mba1_MbsEccFir, bit(48)) ? thresholdAndMask_mba1; - - /** MBSECCFIR_0[49] - * MBECCFIR_ECC_DATAPATH_PARITY_ERROR - */ - (Mba0_MbsEccFir, bit(49)) ? MBA0CalloutMedThr1UE; - - /** MBSECCFIR_1[49] - * MBECCFIR_ECC_DATAPATH_PARITY_ERROR - */ - (Mba1_MbsEccFir, bit(49)) ? MBA1CalloutMedThr1UE; - - /** MBSECCFIR_0[50] - * MBECCFIR_INTERNAL_SCOM_ERROR - */ - (Mba0_MbsEccFir, bit(50)) ? thresholdAndMask_mba0; - - /** MBSECCFIR_1[50] - * MBECCFIR_INTERNAL_SCOM_ERROR - */ - (Mba1_MbsEccFir, bit(50)) ? thresholdAndMask_mba1; - - /** MBSECCFIR_0[51] - * MBECCFIR_INTERNAL_SCOM_ERROR_COPY - */ - (Mba0_MbsEccFir, bit(51)) ? thresholdAndMask_mba0; - - /** MBSECCFIR_1[51] - * MBECCFIR_INTERNAL_SCOM_ERROR_COPY - */ - (Mba1_MbsEccFir, bit(51)) ? thresholdAndMask_mba1; -}; - -################################################################################ -# NEST Chiplet MCBISTFIRs -################################################################################ -# RAS spreadsheet: p8dd1_mss_FFDC_37_ reviewd.xls - -rule Mba0_McbistFir -{ - CHECK_STOP: MCBISTFIR_0 & ~MCBISTFIR_0_MASK & - ~MCBISTFIR_0_ACT0 & ~MCBISTFIR_0_ACT1; - UNIT_CS: MCBISTFIR_0 & ~MCBISTFIR_0_MASK & - ~MCBISTFIR_0_ACT0 & ~MCBISTFIR_0_ACT1; - RECOVERABLE: MCBISTFIR_0 & ~MCBISTFIR_0_MASK & - ~MCBISTFIR_0_ACT0 & MCBISTFIR_0_ACT1; -}; - -rule Mba1_McbistFir -{ - CHECK_STOP: MCBISTFIR_1 & ~MCBISTFIR_1_MASK & - ~MCBISTFIR_1_ACT0 & ~MCBISTFIR_1_ACT1; - UNIT_CS: MCBISTFIR_1 & ~MCBISTFIR_1_MASK & - ~MCBISTFIR_1_ACT0 & ~MCBISTFIR_1_ACT1; - RECOVERABLE: MCBISTFIR_1 & ~MCBISTFIR_1_MASK & - ~MCBISTFIR_1_ACT0 & MCBISTFIR_1_ACT1; -}; - -group gMcbistFir filter singlebit, - secondarybits(2,3,4,5,6,7,8,9,10,11,12,13,14,15,16) -{ - /** MCBISTFIR_0[0] - * MBSFIRQ_SCOM_PAR_ERRORS - */ - (Mba0_McbistFir, bit(0)) ? MBA0CalloutMedThr1; - - /** MCBISTFIR_1[0] - * MBSFIRQ_SCOM_PAR_ERRORS - */ - (Mba1_McbistFir, bit(0)) ? MBA1CalloutMedThr1; - - /** MCBISTFIR_0[1] - * MBSFIRQ_MBX_PAR_ERRORS - */ - (Mba0_McbistFir, bit(1)) ? MBA0CalloutMedThr1; - - /** MCBISTFIR_1[1] - * MBSFIRQ_MBX_PAR_ERRORS - */ - (Mba1_McbistFir, bit(1)) ? MBA1CalloutMedThr1; - - # This is for DD2 only - /** MCBISTFIR_0[2] - * MBSFIRQ_DRAM_EVENT_BIT0 - */ - (Mba0_McbistFir, bit(2)) ? defaultMaskedError; - - # This is for DD2 only - /** MCBISTFIR_1[2] - * MBSFIRQ_DRAM_EVENT_BIT0 - */ - (Mba1_McbistFir, bit(2)) ? defaultMaskedError; - - # This is for DD2 only - /** MCBISTFIR_0[3] - * MBSFIRQ_DRAM_EVENT_BIT1 - */ - (Mba0_McbistFir, bit(3)) ? defaultMaskedError; - - # This is for DD2 only - /** MCBISTFIR_1[3] - * MBSFIRQ_DRAM_EVENT_BIT1 - */ - (Mba1_McbistFir, bit(3)) ? defaultMaskedError; - - /** MCBISTFIR_0[4:14] - * Reserved - */ - (Mba0_McbistFir, bit(4|5|6|7|8|9|10|11|12|13|14)) ? defaultMaskedError; - - /** MCBISTFIR_1[4:14] - * Reserved - */ - (Mba1_McbistFir, bit(4|5|6|7|8|9|10|11|12|13|14)) ? defaultMaskedError; - - /** MCBISTFIR_0[15] - * MBSFIRQ_INTERNAL_SCOM_ERROR - */ - (Mba0_McbistFir, bit(15)) ? thresholdAndMask_mba0; - - /** MCBISTFIR_1[15] - * MBSFIRQ_INTERNAL_SCOM_ERROR - */ - (Mba1_McbistFir, bit(15)) ? thresholdAndMask_mba1; - - /** MCBISTFIR_0[16] - * MBSFIRQ_INTERNAL_SCOM_ERROR_CLONE - */ - (Mba0_McbistFir, bit(16)) ? thresholdAndMask_mba0; - - /** MCBISTFIR_1[16] - * MBSFIRQ_INTERNAL_SCOM_ERROR_CLONE - */ - (Mba1_McbistFir, bit(16)) ? thresholdAndMask_mba1; -}; - -################################################################################ -# NEST Chiplet MBSSECUREFIR -################################################################################ - -rule MbsSecureFir -{ - # NOTE: This secure FIR will only report checkstop attentions. - CHECK_STOP: MBSSECUREFIR; - UNIT_CS: MBSSECUREFIR; -}; - -group gMbsSecureFir filter singlebit -{ - /** MBSSECUREFIR[0] - * MBSSIRQ_INVALID_MBSXCR_ACCESS - */ - (MbsSecureFir, bit(0)) ? secureFirCallout; - - /** MBSSECUREFIR[1] - * MBSSIRQ_INVALID_MBAXCR01_ACCESS - */ - (MbsSecureFir, bit(1)) ? secureFirCallout; - - /** MBSSECUREFIR[2] - * MBSSIRQ_INVALID_MBAXCR23_ACCESS - */ - (MbsSecureFir, bit(2)) ? secureFirCallout; - - /** MBSSECUREFIR[3] - * MBSSIRQ_INVALID_MBAXCRMS_ACCRESS - */ - (MbsSecureFir, bit(3)) ? secureFirCallout; - - /** MBSSECUREFIR[4] - * MBSSIRQ_SPARE (Spare) - */ - (MbsSecureFir, bit(4)) ? secureFirCallout; - - /** MBSSECUREFIR[5] - * MBSSIRQ_INVALID_SIR_MASK_OR_ACTION_REGISTER_ACCESS - */ - (MbsSecureFir, bit(5)) ? secureFirCallout; -}; - -################################################################################ # Actions specific to NEST chiplet ################################################################################ -/** Callout the connected MBA 0 */ -actionclass calloutMba0 { callout(connected(TYPE_MBA, 0), MRU_MED); }; - -/** Callout the connected MBA 1 */ -actionclass calloutMba1 { callout(connected(TYPE_MBA, 1), MRU_MED); }; - -/** Callout the connected L4 */ -actionclass calloutL4 { callout(connected(TYPE_L4), MRU_MED); }; - /** Callout the DMI bus */ actionclass calloutDmiBus { @@ -1421,103 +176,3 @@ actionclass analyzeFetchUe1 SUEGenerationPoint; }; -/** Clear MBS SecondaryBits and Line Delete*/ -actionclass clearSecMbsBitsAndLineDelete -{ - calloutL4; - threshold( field(32 / day), mfg_file(ATTR_MNFG_TH_CEN_L4_CACHE_CES)); - funccall("CaptureL4CacheErr"); - funccall("ClearServiceCallFlag"); - funccall("ClearMbsSecondaryBits"); -}; - -/** Clear MBACAL SecondaryBits and Line Delete*/ -actionclass clearSecMbaCalBitsAndLineDelete -{ - calloutL4; - threshold( field(32 / day), mfg_file(ATTR_MNFG_TH_CEN_L4_CACHE_CES)); - funccall("CaptureL4CacheErr"); - funccall("ClearServiceCallFlag"); - funccall("ClearMbaCalSecondaryBits"); -}; - -/** Mask MBACAL SecondaryBits and callout Connected L4*/ -actionclass maskSecMbaCalBitsAndConnL4UE -{ - calloutL4; - threshold1; - funccall("CaptureL4CacheErr"); - funccall("MaskMbaCalSecondaryBits"); - SUEGenerationPoint; -}; - -/** Mask MBS SecondaryBits and callout Connected L4*/ -actionclass maskSecMbsBitsAndConnL4UE -{ - calloutL4; - threshold1; - funccall("CaptureL4CacheErr"); - funccall("MaskMbsSecondaryBits"); - SUEGenerationPoint; -}; - -/** Callout MBA0 with "Threshold and Mask" policy. */ -actionclass thresholdAndMask_mba0 { calloutMba0; thresholdAndMask; }; - -/** Callout MBA1 with "Threshold and Mask" policy. */ -actionclass thresholdAndMask_mba1 { calloutMba1; thresholdAndMask; }; - -actionclass L4CalloutMedThr32PerDay -{ - calloutL4; - threshold32pday; -}; - -actionclass L4CalloutMedThr1UE -{ - calloutL4; - threshold1; - SUEGenerationPoint; -}; - -actionclass MBA0CalloutMedThr1 -{ - calloutMba0; - threshold1; -}; - -actionclass MBA1CalloutMedThr1 -{ - calloutMba1; - threshold1; -}; - -actionclass MBA0CalloutMedThr1UE -{ - MBA0CalloutMedThr1; - SUEGenerationPoint; -}; - -actionclass MBA1CalloutMedThr1UE -{ - MBA1CalloutMedThr1; - SUEGenerationPoint; -}; - -/** The plugin checks if the membuf is at DD1. - If DD1, then callout thresholdAndMask_self and change signature - to DD1: MBS_FIR_REG_INTERNAL_SCOM_ERROR_COPY */ -actionclass mbsfirBit30 -{ - threshold32pday; - try( funccall("mbsfirBit30_dd1"), L4CalloutMedThr1UE); -}; - -/** Callouts specific to MBSSECUREFIR attentions. */ -actionclass secureFirCallout -{ - callout2ndLvlMed; - calloutSelfLow; - threshold1; -}; - diff --git a/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_TP.rule b/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_TP.rule deleted file mode 100755 index 1b2a18f85..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_TP.rule +++ /dev/null @@ -1,157 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_TP.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -################################################################################ -# TP Chiplet Registers -################################################################################ - -rule TpChipletFir -{ - CHECK_STOP: - (TP_CHIPLET_CS_FIR & `1000000000000000`) & ~TP_CHIPLET_FIR_MASK; - UNIT_CS: - (TP_CHIPLET_CS_FIR & `1000000000000000`) & ~TP_CHIPLET_FIR_MASK; - RECOVERABLE: - ((TP_CHIPLET_RE_FIR >> 2) & `1000000000000000`) & ~TP_CHIPLET_FIR_MASK; -}; - -group gTpChipletFir filter singlebit -{ - /** TP_CHIPLET_FIR[3] - * Attention from LFIR - */ - (TpChipletFir, bit(3)) ? analyze(gTpLFir); -}; - -################################################################################ -# TP Chiplet LFIR -################################################################################ -# RAS spreadsheet: p8dd1_mss_FFDC_37_ reviewd.xls - -rule TpLFir -{ - CHECK_STOP: TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 & ~TP_LFIR_ACT1; - UNIT_CS: TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 & ~TP_LFIR_ACT1; - RECOVERABLE: TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 & TP_LFIR_ACT1; -}; - -group gTpLFir filter singlebit, - secondarybits(0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17, - 18,21,22,23,24,25,26,27,28,29,30,31,32,33,34, - 35,36,37,38,39,40) -{ - /** TP_LFIR[0] - * CFIR internal parity error - */ - (TpLFir, bit(0)) ? thresholdAndMask_self; - - /** TP_LFIR[1] - * Local errors from GPIO (PCB error) - */ - (TpLFir, bit(1)) ? defaultMaskedError; - - /** TP_LFIR[2] - * Local errors from CC (PCB error) - */ - (TpLFir, bit(2)) ? defaultMaskedError; - - /** TP_LFIR[3] - * Local errors from CC (OPCG, parity, scan collision, ...) - */ - (TpLFir, bit(3)) ? defaultMaskedError; - - /** TP_LFIR[4] - * Local errors from PSC (PCB error) - */ - (TpLFir, bit(4)) ? defaultMaskedError; - - /** TP_LFIR[5] - * Local errors from PSC (parity error) - */ - (TpLFir, bit(5)) ? defaultMaskedError; - - /** TP_LFIR[6] - * Local errors from Thermal (parity error) - */ - (TpLFir, bit(6)) ? defaultMaskedError; - - /** TP_LFIR[7] - * Local errors from Thermal (PCB error) - */ - (TpLFir, bit(7)) ? defaultMaskedError; - - /** TP_LFIR[8:10] - * Local errors from Thermal (Trip error) - */ - (TpLFir, bit(8|9|10)) ? defaultMaskedError; - - /** TP_LFIR[11:12] - * Local errors from Trace Array ( error) - */ - (TpLFir, bit(11|12)) ? defaultMaskedError; - - /** TP_LFIR[13:14] - * Local errors from ITR - */ - (TpLFir, bit(13|14)) ? thresholdAndMask_self; - - /** TP_LFIR[15] - * Local errors from ITR ( itr_tc_pcbsl_slave_fir_err ) - */ - (TpLFir, bit(15)) ? defaultMaskedError; - - /** TP_LFIR[16:18] - * Local errors from PIB - */ - (TpLFir, bit(16|17|18)) ? defaultMaskedError; - - /** TP_LFIR[19] - * local errors from nest PLL - * - * These should never trigger directly themselves. - * Should be handled by global PRD PLL code. - */ - (TpLFir, bit(19)) ? threshold32pday; - - /** TP_LFIR[20] - * local errors from mem PLL - * - * These should never trigger directly themselves. - * Should be handled by global PRD PLL code. - */ - (TpLFir, bit(20)) ? threshold32pday; - - /** TP_LFIR[40] - * local errors from mem PLL - * - * Malfunction alert (local xstop in another chiplet) - */ - (TpLFir, bit(40)) ? defaultMaskedError; -}; - -################################################################################ -# Actions specific to TP chiplet -################################################################################ - diff --git a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_MEM.rule b/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_MEM.rule index 28d5e46eb..8bf48cd6d 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_MEM.rule +++ b/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_MEM.rule @@ -5,7 +5,9 @@ # # OpenPOWER HostBoot Project # -# COPYRIGHT International Business Machines Corp. 2012,2014 +# Contributors Listed Below - COPYRIGHT 2012,2018 +# [+] International Business Machines Corp. +# # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -22,110 +24,6 @@ # IBM_PROLOG_END_TAG ############################################################################ - # MEM Chiplet Registers - ############################################################################ - - register MEM_CHIPLET_CS_FIR - { - name "TCM.XFIR"; - scomaddr 0x03040000; - capture group FirRegs; - capture group MemChipletRegs; - }; - - register MEM_CHIPLET_RE_FIR - { - name "TCM.RFIR"; - scomaddr 0x03040001; - capture group FirRegs; - capture group MemChipletRegs; - }; - - register MEM_CHIPLET_FIR_MASK - { - name "TCM.FIR_MASK"; - scomaddr 0x03040002; - capture group FirRegs; - capture group MemChipletRegs; - }; - - register MEM_CHIPLET_SPA - { - name "TCM.EPS.FIR.SPATTN"; - scomaddr 0x03040004; - capture group FirRegs; - capture group MemChipletRegs; - }; - - register MEM_CHIPLET_SPA_MASK - { - name "TCM.EPS.FIR.SPA_MASK"; - scomaddr 0x03040007; - capture group FirRegs; - capture group MemChipletRegs; - }; - - ############################################################################ - # MEM Chiplet LFIR - ############################################################################ - - register MEM_LFIR - { - name "TCM.LOCAL_FIR"; - scomaddr 0x0304000a; - reset (&, 0x0304000b); - mask (|, 0x0304000f); - capture group FirRegs; - capture group MemChipletRegs; - }; - - register MEM_LFIR_MASK - { - name "TCM.EPS.FIR.LOCAL_FIR_MASK"; - scomaddr 0x0304000d; - capture group FirRegs; - capture group MemChipletRegs; - }; - - register MEM_LFIR_ACT0 - { - name "TCM.EPS.FIR.LOCAL_FIR_ACTION0"; - scomaddr 0x03040010; - capture type secondary; - capture group FirRegs; - capture group MemChipletRegs; - capture req nonzero("MEM_LFIR"); - }; - - register MEM_LFIR_ACT1 - { - name "TCM.EPS.FIR.LOCAL_FIR_ACTION1"; - scomaddr 0x03040011; - capture type secondary; - capture group FirRegs; - capture group MemChipletRegs; - capture req nonzero("MEM_LFIR"); - }; - - ############################################################################ - # MEM Chiplet MEMFBISTFIR - ############################################################################ - - # FIR not used. Capture for FFDC only. - # This register is on the same clock domain for both MBAs. So if one is - # powered down and we try to SCOM to the other, there will be SCOM failures. - # Since this register is for FFDC purposes only, we simply will not capture - # this register. - -# register MEMFBISTFIR -# { -# name "FBIST.FBM.FBM_FIR_REG"; -# scomaddr 0x03010480; -# capture group FirRegs; -# capture group MemChipletRegs; -# }; - - ############################################################################ # Error Report Registers ############################################################################ diff --git a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule b/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule index 090168456..f996d93af 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule +++ b/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule @@ -24,131 +24,9 @@ # IBM_PROLOG_END_TAG ############################################################################ - # NEST Chiplet Registers - ############################################################################ - - register NEST_CHIPLET_CS_FIR - { - name "TCN.XFIR"; - scomaddr 0x02040000; - capture group default; - capture group FirRegs; - }; - - register NEST_CHIPLET_RE_FIR - { - name "TCN.RFIR"; - scomaddr 0x02040001; - capture group default; - capture group FirRegs; - }; - - register NEST_CHIPLET_FIR_MASK - { - name "TCN.FIR_MASK"; - scomaddr 0x02040002; - capture group default; - capture group FirRegs; - }; - - ############################################################################ - # NEST Chiplet LFIR - ############################################################################ - - register NEST_LFIR - { - name "TCN.LOCAL_FIR"; - scomaddr 0x0204000a; - reset (&, 0x0204000b); - mask (|, 0x0204000f); - capture group default; - capture group FirRegs; - }; - - register NEST_LFIR_MASK - { - name "TCN.EPS.FIR.LOCAL_FIR_MASK"; - scomaddr 0x0204000d; - capture group default; - capture group FirRegs; - }; - - register NEST_LFIR_ACT0 - { - name "TCN.EPS.FIR.LOCAL_FIR_ACTION0"; - scomaddr 0x02040010; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("NEST_LFIR"); - }; - - register NEST_LFIR_ACT1 - { - name "TCN.EPS.FIR.LOCAL_FIR_ACTION1"; - scomaddr 0x02040011; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("NEST_LFIR"); - }; - - ############################################################################ - # NEST Chiplet DMIFIR - ############################################################################ - - register DMIFIR - { - name "DMI.BUSCTL.SCOM.FIR_REG"; - scomaddr 0x02010400; - reset (&, 0x02010401); - mask (|, 0x02010405); - capture group default; - capture group FirRegs; - }; - - register DMIFIR_MASK - { - name "DMI.BUSCTL.SCOM.FIR_MASK_REG"; - scomaddr 0x02010403; - capture group default; - capture group FirRegs; - }; - - register DMIFIR_ACT0 - { - name "DMI.BUSCTL.SCOM.FIR_ACTION0_REG"; - scomaddr 0x02010406; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("DMIFIR"); - }; - - register DMIFIR_ACT1 - { - name "DMI.BUSCTL.SCOM.FIR_ACTION1_REG"; - scomaddr 0x02010407; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("DMIFIR"); - }; - - ############################################################################ # NEST Chiplet MBIFIR ############################################################################ - register MBIFIR - { - name "MBU.MBI.MBI.SCOMFIR.MBIFIRQ"; - scomaddr 0x02010800; - reset (&, 0x02010801); - mask (|, 0x02010805); - capture group default; - capture group FirRegs; - }; - register MBIFIR_AND { name "MBU.MBI.MBI.SCOMFIR.MBIFIRQ AND"; @@ -157,91 +35,10 @@ access write_only; }; - register MBIFIR_MASK - { - name "MBU.MBI.MBI.SCOMFIR.MBIFIRMASK"; - scomaddr 0x02010803; - capture group default; - capture group FirRegs; - }; - - register MBIFIR_ACT0 - { - name "MBU.MBI.MBI.SCOMFIR.MBIFIRACT0"; - scomaddr 0x02010806; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("MBIFIR"); - }; - - register MBIFIR_ACT1 - { - name "MBU.MBI.MBI.SCOMFIR.MBIFIRACT1"; - scomaddr 0x02010807; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("MBIFIR"); - }; - - ############################################################################ - # NEST Chiplet MBSFIR - ############################################################################ - - register MBSFIR - { - name "MBU.MBS.MBS_FIR_REG"; - scomaddr 0x02011400; - reset (&, 0x02011401); - mask (|, 0x02011405); - capture group default; - capture group FirRegs; - }; - - register MBSFIR_MASK - { - name "MBU.MBS.MBS_FIR_MASK_REG"; - scomaddr 0x02011403; - capture group default; - capture group FirRegs; - }; - - register MBSFIR_ACT0 - { - name "MBU.MBS.MBS_FIR_ACTION0_REG"; - scomaddr 0x02011406; - capture type secondary; - capture req nonzero("MBSFIR"); - capture group default; - capture group FirRegs; - }; - - register MBSFIR_ACT1 - { - name "MBU.MBS.MBS_FIR_ACTION1_REG"; - scomaddr 0x02011407; - capture type secondary; - capture req nonzero("MBSFIR"); - capture group default; - capture group FirRegs; - }; - ############################################################################ # NEST Chiplet MBSECCFIR_0 ############################################################################ - register MBSECCFIR_0 - { - name "MBU.MBS.ECC01.MBECCFIR"; - scomaddr 0x02011440; - reset (&, 0x02011441); - mask (|, 0x02011445); - capture group default; - capture group FirRegs; - capture group MaintCmdRegs_mba0; - }; - register MBSECCFIR_0_AND { name "MBU.MBS.ECC01.MBECCFIR_AND"; @@ -250,15 +47,6 @@ access write_only; }; - register MBSECCFIR_0_MASK - { - name "MBU.MBS.ECC01.MBECCFIR_MASK"; - scomaddr 0x02011443; - capture group default; - capture group FirRegs; - capture group MaintCmdRegs_mba0; - }; - register MBSECCFIR_0_MASK_AND { name "MBU.MBS.ECC01.MBECCFIR_MASK_AND"; @@ -275,43 +63,10 @@ access write_only; }; - register MBSECCFIR_0_ACT0 - { - name "MBU.MBS.ECC01.MBECCFIR_ACTION0"; - scomaddr 0x02011446; - capture type secondary; - capture group default; - capture group FirRegs; - capture group MaintCmdRegs_mba0; - capture req nonzero("MBSECCFIR_0"); - }; - - register MBSECCFIR_0_ACT1 - { - name "MBU.MBS.ECC01.MBECCFIR_ACTION1"; - scomaddr 0x02011447; - capture type secondary; - capture group default; - capture group FirRegs; - capture group MaintCmdRegs_mba0; - capture req nonzero("MBSECCFIR_0"); - }; - ############################################################################ # NEST Chiplet MBSECCFIR_1 ############################################################################ - register MBSECCFIR_1 - { - name "MBU.MBS.ECC23.MBECCFIR"; - scomaddr 0x02011480; - reset (&, 0x02011481); - mask (|, 0x02011485); - capture group default; - capture group FirRegs; - capture group MaintCmdRegs_mba1; - }; - register MBSECCFIR_1_AND { name "MBU.MBS.ECC23.MBECCFIR_AND"; @@ -320,15 +75,6 @@ access write_only; }; - register MBSECCFIR_1_MASK - { - name "MBU.MBS.ECC23.MBECCFIR_MASK"; - scomaddr 0x02011483; - capture group default; - capture group FirRegs; - capture group MaintCmdRegs_mba1; - }; - register MBSECCFIR_1_MASK_AND { name "MBU.MBS.ECC23.MBECCFIR_MASK_AND"; @@ -345,112 +91,6 @@ access write_only; }; - register MBSECCFIR_1_ACT0 - { - name "MBU.MBS.ECC23.MBECCFIR_ACTION0"; - scomaddr 0x02011486; - capture type secondary; - capture group default; - capture group FirRegs; - capture group MaintCmdRegs_mba1; - capture req nonzero("MBSECCFIR_1"); - }; - - register MBSECCFIR_1_ACT1 - { - name "MBU.MBS.ECC23.MBECCFIR_ACTION0"; - scomaddr 0x02011487; - capture type secondary; - capture group default; - capture group FirRegs; - capture group MaintCmdRegs_mba1; - capture req nonzero("MBSECCFIR_1"); - }; - - ############################################################################ - # NEST Chiplet MCBISTFIR_0 - ############################################################################ - - register MCBISTFIR_0 - { - name "MBU.MBS.MCBISTS01.SCOMFIR.MBSFIRQ"; - scomaddr 0x02011600; - reset (&, 0x02011601); - mask (|, 0x02011605); - capture group default; - capture group FirRegs; - }; - - register MCBISTFIR_0_MASK - { - name "MBU.MBS.MCBISTS01.SCOMFIR.MBSFIRMASK"; - scomaddr 0x02011603; - capture group default; - capture group FirRegs; - }; - - register MCBISTFIR_0_ACT0 - { - name "MBU.MBS.MCBISTS01.SCOMFIR.MBSFIRACTION0"; - scomaddr 0x02011606; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("MCBISTFIR_0"); - }; - - register MCBISTFIR_0_ACT1 - { - name "MBU.MBS.MCBISTS01.SCOMFIR.MBSFIRACTION1"; - scomaddr 0x02011607; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("MCBISTFIR_0"); - }; - - ############################################################################ - # NEST Chiplet MCBISTFIR_1 - ############################################################################ - - register MCBISTFIR_1 - { - name "MBU.MBS.MCBISTS23.SCOMFIR.MBSFIRQ"; - scomaddr 0x02011700; - reset (&, 0x02011701); - mask (|, 0x02011705); - capture group default; - capture group FirRegs; - }; - - register MCBISTFIR_1_MASK - { - name "MBU.MBS.MCBISTS23.SCOMFIR.MBSFIRMASK"; - scomaddr 0x02011703; - capture group default; - capture group FirRegs; - }; - - register MCBISTFIR_1_ACT0 - { - name "MBU.MBS.MCBISTS23.SCOMFIR.MBSFIRACTION0"; - scomaddr 0x02011706; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("MCBISTFIR_1"); - }; - - register MCBISTFIR_1_ACT1 - { - name "MBU.MBS.MCBISTS23.SCOMFIR.MBSFIRACTION1"; - scomaddr 0x02011707; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("MCBISTFIR_1"); - }; - ############################################################################ # NEST Chiplet NESTFBISTFIR ############################################################################ @@ -466,63 +106,6 @@ }; ############################################################################ - # NEST Chiplet SCACFIR - ############################################################################ - - register SCACFIR - { - name "SCAC.SCAC_LFIR"; - scomaddr 0x020115c0; - reset (&, 0x020115c1); - mask (|, 0x020115c5); - capture group default; - capture group FirRegs; - }; - - register SCACFIR_MASK - { - name "SCAC.SCAC_FIRMASK"; - scomaddr 0x020115c3; - capture group default; - capture group FirRegs; - }; - - register SCACFIR_ACT0 - { - name "SCAC.SCAC_FIRACTION0"; - scomaddr 0x020115c6; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("SCACFIR"); - }; - - register SCACFIR_ACT1 - { - name "SCAC.SCAC_FIRACTION1"; - scomaddr 0x020115c7; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("SCACFIR"); - }; - - ############################################################################ - # NEST Chiplet MBSSECUREFIR - ############################################################################ - - # This register is hardwired to channel failure (checkstop) and we cannot - # mask or change the state of the action registers. - register MBSSECUREFIR - { - name "MBU.MBS.ARB.RXLT.MBSSIRQ"; - scomaddr 0x0201141e; - reset (&, 0x0201141f); - capture group default; - capture group FirRegs; - }; - - ############################################################################ # Error Report Registers ############################################################################ diff --git a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_TP.rule b/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_TP.rule index b2fb6c52e..37c20f67d 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_TP.rule +++ b/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_TP.rule @@ -5,7 +5,9 @@ # # OpenPOWER HostBoot Project # -# COPYRIGHT International Business Machines Corp. 2012,2014 +# Contributors Listed Below - COPYRIGHT 2012,2018 +# [+] International Business Machines Corp. +# # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -22,47 +24,9 @@ # IBM_PROLOG_END_TAG ############################################################################ - # TP Chiplet Registers - ############################################################################ - - register TP_CHIPLET_CS_FIR - { - name "TPTOP.TPC.XFIR"; - scomaddr 0x01040000; - capture group default; - capture group FirRegs; - }; - - register TP_CHIPLET_RE_FIR - { - name "TPTOP.TPC.RFIR"; - scomaddr 0x01040001; - capture group default; - capture group FirRegs; - }; - - register TP_CHIPLET_FIR_MASK - { - name "TPTOP.TPC.FIR_MASK"; - scomaddr 0x01040002; - capture group default; - capture group FirRegs; - }; - - ############################################################################ # TP Chiplet LFIR ############################################################################ - register TP_LFIR - { - name "TPTOP.TPC.LOCAL_FIR"; - scomaddr 0x0104000a; - reset (&, 0x0104000b); - mask (|, 0x0104000f); - capture group default; - capture group FirRegs; - }; - register TP_LFIR_AND { name "TPTOP.TPC.LOCAL_FIR_AND"; @@ -71,14 +35,6 @@ access write_only; }; - register TP_LFIR_MASK - { - name "TPTOP.TPC.EPS.FIR.LOCAL_FIR_MASK"; - scomaddr 0x0104000d; - capture group default; - capture group FirRegs; - }; - register TP_LFIR_MASK_OR { name "TPTOP.TPC.EPS.FIR.LOCAL_FIR_MASK_OR"; @@ -87,26 +43,6 @@ access write_only; }; - register TP_LFIR_ACT0 - { - name "TPTOP.TPC.EPS.FIR.LOCAL_FIR_ACTION0"; - scomaddr 0x01040010; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("TP_LFIR"); - }; - - register TP_LFIR_ACT1 - { - name "TPTOP.TPC.EPS.FIR.LOCAL_FIR_ACTION1"; - scomaddr 0x01040011; - capture type secondary; - capture group default; - capture group FirRegs; - capture req nonzero("TP_LFIR"); - }; - ############################################################################ # Error Report Registers ############################################################################ diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaCaptureData.C b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaCaptureData.C index d934ab780..f6aa5b50a 100644 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaCaptureData.C +++ b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaCaptureData.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2017 */ +/* Contributors Listed Below - COPYRIGHT 2013,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -81,7 +81,7 @@ void addMemChipletFirRegs( ExtensibleChip * i_membChip, CaptureData & io_cd ) SCAN_COMM_REGISTER_CLASS * cs_global, * re_global, * spa_global; cs_global = i_membChip->getRegister("GLOBAL_CS_FIR"); re_global = i_membChip->getRegister("GLOBAL_RE_FIR"); - spa_global = i_membChip->getRegister("GLOBAL_SPA"); + spa_global = i_membChip->getRegister("GLOBAL_SPA_FIR"); l_rc = cs_global->Read() | re_global->Read() | spa_global->Read(); if ( SUCCESS != l_rc ) { diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMembuf.C b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMembuf.C index 97e63249e..4053a5414 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMembuf.C +++ b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMembuf.C @@ -121,90 +121,6 @@ int32_t CheckForRecovered(ExtensibleChip * i_chip, //------------------------------------------------------------------------------ /** - * @brief MBA0 is always analyzed before MBA1 in the rule code. - * This plugin will help prevent starvation of MBA1. - * @param i_membChip The Centaur Membuf chip. - * @param i_sc The step code data struct. - * @return FAIL if MBA1 is not analyzed. - */ -int32_t MBA1_Starvation( ExtensibleChip * i_membChip, - STEP_CODE_DATA_STRUCT & i_sc ) -{ - using namespace TARGETING; - CenMembufDataBundle * l_membdb = getMembufDataBundle(i_membChip); - - do - { - ExtensibleChip * mba1Chip = l_membdb->getMbaChip(1); - if ( NULL == mba1Chip ) break; // No MBA1 target, exit early - - if ( l_membdb->iv_analyzeMba1Starvation ) - { - // Get the mem chiplet register - SCAN_COMM_REGISTER_CLASS * l_memcFir = NULL; - uint32_t l_checkBits = 0; - switch ( i_sc.service_data->getSecondaryAttnType() ) - { - case CHECK_STOP: - l_memcFir = i_membChip->getRegister("MEM_CHIPLET_CS_FIR"); - // mba1 CS: bits 7, 8, 10, 13 - l_checkBits = 0x01A40000; - break; - case RECOVERABLE: - l_memcFir = i_membChip->getRegister("MEM_CHIPLET_RE_FIR"); - // mba1 RE: bits 5, 6, 8, 11 - l_checkBits = 0x06900000; - break; - case SPECIAL: - l_memcFir = i_membChip->getRegister("MEM_CHIPLET_SPA"); - // mba1 SA: bit 1 - l_checkBits = 0x40000000; - break; - default: ; - } - - if( NULL == l_memcFir ) - { - break; - } - - // Check if MBA1 from Mem Chiplet is reporting an attention - int32_t l_rc = l_memcFir->Read(); - if ( SUCCESS != l_rc ) - { - PRDF_ERR("[MBA1_Starvation] SCOM fail on 0x%08x", - i_membChip->GetId()); - break; - } - - uint32_t l_val = l_memcFir->GetBitFieldJustified(0,32); - if ( 0 == ( l_val & l_checkBits ) ) - { - break; // No MBA1 attentions - } - - // MBA0 takes priority next - l_membdb->iv_analyzeMba1Starvation = false; - - // Analyze MBA1 - return mba1Chip->Analyze( i_sc, - i_sc.service_data->getSecondaryAttnType() ); - } - else - { - // MBA1 takes priority next - l_membdb->iv_analyzeMba1Starvation = true; - } - - } while (0); - - return FAIL; -} -PRDF_PLUGIN_DEFINE( Membuf, MBA1_Starvation ); - -//------------------------------------------------------------------------------ - -/** * @brief Analysis code that is called before the main analyze() function. * @param i_mbChip A MEMBUF chip. * @param i_sc Step Code Data structure @@ -942,32 +858,6 @@ int32_t internalTimeout( ExtensibleChip * i_mbChip, //------------------------------------------------------------------------------ -/** - * @brief Checks DD level. If DD1, implements the DD1 callout actions for - * MBSFIR bit 30. - * @param i_membChip Centaur chip - * @param i_sc Step code data struct - * @returns SUCCESS if DD1, FAIL otherwise - */ -int32_t mbsfirBit30_dd1( ExtensibleChip * i_membChip, - STEP_CODE_DATA_STRUCT & i_sc ) -{ - int32_t l_rc = FAIL; - TargetHandle_t l_membTrgt = i_membChip->GetChipHandle(); - if(0x20 > getChipLevel(l_membTrgt)) - { - i_sc.service_data->SetCallout(l_membTrgt, MRU_MED); - ClearServiceCallFlag(i_membChip, i_sc); - i_sc.service_data->SetErrorSig( PRDFSIG_MbsFir_30_DD1Signature ); - l_rc = SUCCESS; - } - - return l_rc; -} -PRDF_PLUGIN_DEFINE( Membuf, mbsfirBit30_dd1 ); - -//------------------------------------------------------------------------------ - // Define the plugins for memory ECC errors. #define PLUGIN_FETCH_ECC_ERROR( TYPE, MBA ) \ int32_t AnalyzeFetch##TYPE##MBA( ExtensibleChip * i_membChip, \ |
