PRD: renamed MBSECCFIR, MCBISTFIR, and MBSTR registers for MBA

Change-Id: I05909a55b10148338e27aa7ce6af2279b77941b5
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57563
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57590
CI-Ready: Zane C. Shelley <zshelle@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>

12 files changed, 220 insertions, 198 deletions

diff --git a/src/usr/diag/prdf/common/plat/cen/cen_centaur_regs.rule b/src/usr/diag/prdf/common/plat/cen/cen_centaur_regs.rule
index c78b46296..bef16d5a2 100644
--- a/src/usr/diag/prdf/common/plat/cen/cen_centaur_regs.rule
+++ b/src/usr/diag/prdf/common/plat/cen/cen_centaur_regs.rule
@@ -39,27 +39,59 @@
     # Additional regs for CEN target MBSECCFIR
     ############################################################################
 
-    register MBA0_MBSECCFIR_AND
+    register MBSECCFIR_0_AND
     {
-        name        "CEN target MBA0_MBSECCFIR atomic AND";
+        name        "Centaur chip MBSECCFIR_0 atomic AND";
         scomaddr    0x02011441;
         capture     group never;
         access      write_only;
     };
 
-    register MBA1_MBSECCFIR_AND
+    register MBSECCFIR_0_MASK_AND
     {
-        name        "CEN target MBA1_MBSECCFIR atomic AND";
+        name        "MBU.MBS.ECC01.MBECCFIR_MASK_AND";
+        scomaddr    0x02011444;
+        capture     group never;
+        access      write_only;
+    };
+
+    register MBSECCFIR_0_MASK_OR
+    {
+        name        "MBU.MBS.ECC01.MBECCFIR_MASK_OR";
+        scomaddr    0x02011445;
+        capture     group never;
+        access      write_only;
+    };
+
+    register MBSECCFIR_1_AND
+    {
+        name        "Centaur chip MBSECCFIR_1 atomic AND";
         scomaddr    0x02011481;
         capture     group never;
         access      write_only;
     };
 
+    register MBSECCFIR_1_MASK_AND
+    {
+        name        "MBU.MBS.ECC23.MBECCFIR_MASK_AND";
+        scomaddr    0x02011484;
+        capture     group never;
+        access      write_only;
+    };
+
+    register MBSECCFIR_1_MASK_OR
+    {
+        name        "MBU.MBS.ECC23.MBECCFIR_MASK_OR";
+        scomaddr    0x02011485;
+        capture     group never;
+        access      write_only;
+    };
+
     ############################################################################
     # Memory maintenance threshold control registers
     ############################################################################
 
-    register MBA0_MBSTR
+    register MBSTR_0
     {
         name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSTRQ";
         scomaddr    0x02011655;
@@ -67,7 +99,7 @@
         capture     group MaintCmdRegs_mba0;
     };
 
-    register MBA1_MBSTR
+    register MBSTR_1
     {
         name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSTRQ";
         scomaddr    0x02011755;
diff --git a/src/usr/diag/prdf/common/plat/mem/prdfMemMark.C b/src/usr/diag/prdf/common/plat/mem/prdfMemMark.C
index 9af88d2b2..84e7c09b5 100644
--- a/src/usr/diag/prdf/common/plat/mem/prdfMemMark.C
+++ b/src/usr/diag/prdf/common/plat/mem/prdfMemMark.C
@@ -395,8 +395,8 @@ uint32_t __clearFetchAttn<TYPE_MBA>( ExtensibleChip * i_chip,
 
     // Clear the fetch MPE attention.
     ExtensibleChip * l_membChip = getConnectedParent( i_chip, TYPE_MEMBUF );
-    const char * reg_str = ( 0 == i_chip->getPos() ) ? "MBA0_MBSECCFIR_AND"
-                                                     : "MBA1_MBSECCFIR_AND";
+    const char * reg_str = ( 0 == i_chip->getPos() ) ? "MBSECCFIR_0_AND"
+                                                     : "MBSECCFIR_1_AND";
     SCAN_COMM_REGISTER_CLASS * firand = l_membChip->getRegister( reg_str );
 
     firand->setAllBits();
diff --git a/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_NEST.rule b/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_NEST.rule
index daf355e2a..e9a24513f 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_NEST.rule
+++ b/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_NEST.rule
@@ -5,7 +5,7 @@
 #
 # OpenPOWER HostBoot Project
 #
-# Contributors Listed Below - COPYRIGHT 2012,2016
+# Contributors Listed Below - COPYRIGHT 2012,2018
 # [+] International Business Machines Corp.
 #
 #
@@ -777,22 +777,22 @@ group gMbsFir filter singlebit,
 
 rule Mba0_MbsEccFir
 {
-  CHECK_STOP:   MBA0_MBSECCFIR      & ~MBA0_MBSECCFIR_MASK &
-               ~MBA0_MBSECCFIR_ACT0 & ~MBA0_MBSECCFIR_ACT1;
-  UNIT_CS:      MBA0_MBSECCFIR      & ~MBA0_MBSECCFIR_MASK &
-               ~MBA0_MBSECCFIR_ACT0 & ~MBA0_MBSECCFIR_ACT1;
-  RECOVERABLE:  MBA0_MBSECCFIR      & ~MBA0_MBSECCFIR_MASK &
-               ~MBA0_MBSECCFIR_ACT0 &  MBA0_MBSECCFIR_ACT1;
+  CHECK_STOP:   MBSECCFIR_0      & ~MBSECCFIR_0_MASK &
+               ~MBSECCFIR_0_ACT0 & ~MBSECCFIR_0_ACT1;
+  UNIT_CS:      MBSECCFIR_0      & ~MBSECCFIR_0_MASK &
+               ~MBSECCFIR_0_ACT0 & ~MBSECCFIR_0_ACT1;
+  RECOVERABLE:  MBSECCFIR_0      & ~MBSECCFIR_0_MASK &
+               ~MBSECCFIR_0_ACT0 &  MBSECCFIR_0_ACT1;
 };
 
 rule Mba1_MbsEccFir
 {
-  CHECK_STOP:   MBA1_MBSECCFIR      & ~MBA1_MBSECCFIR_MASK &
-               ~MBA1_MBSECCFIR_ACT0 & ~MBA1_MBSECCFIR_ACT1;
-  UNIT_CS:      MBA1_MBSECCFIR      & ~MBA1_MBSECCFIR_MASK &
-               ~MBA1_MBSECCFIR_ACT0 & ~MBA1_MBSECCFIR_ACT1;
-  RECOVERABLE:  MBA1_MBSECCFIR      & ~MBA1_MBSECCFIR_MASK &
-               ~MBA1_MBSECCFIR_ACT0 &  MBA1_MBSECCFIR_ACT1;
+  CHECK_STOP:   MBSECCFIR_1      & ~MBSECCFIR_1_MASK &
+               ~MBSECCFIR_1_ACT0 & ~MBSECCFIR_1_ACT1;
+  UNIT_CS:      MBSECCFIR_1      & ~MBSECCFIR_1_MASK &
+               ~MBSECCFIR_1_ACT0 & ~MBSECCFIR_1_ACT1;
+  RECOVERABLE:  MBSECCFIR_1      & ~MBSECCFIR_1_MASK &
+               ~MBSECCFIR_1_ACT0 &  MBSECCFIR_1_ACT1;
 };
 
 group gMbsEccFir filter priority ( 19, 41 ),
@@ -801,312 +801,312 @@ group gMbsEccFir filter priority ( 19, 41 ),
                                       32,33,34,35,36,37,38,39,40,41,42,43,44,45,
                                       48,50,51)
 {
-    /** MBA0_MBSECCFIR[0]
+    /** MBSECCFIR_0[0]
      *  Memory chip mark on rank 0
      */
     (Mba0_MbsEccFir, bit(0)) ? analyzeFetchMpe0_0;
 
-    /** MBA1_MBSECCFIR[0]
+    /** MBSECCFIR_1[0]
      *  Memory chip mark on rank 0
      */
     (Mba1_MbsEccFir, bit(0)) ? analyzeFetchMpe1_0;
 
-    /** MBA0_MBSECCFIR[1]
+    /** MBSECCFIR_0[1]
      *  Memory chip mark on rank 1
      */
     (Mba0_MbsEccFir, bit(1)) ? analyzeFetchMpe0_1;
 
-    /** MBA1_MBSECCFIR[1]
+    /** MBSECCFIR_1[1]
      *  Memory chip mark on rank 1
      */
     (Mba1_MbsEccFir, bit(1)) ? analyzeFetchMpe1_1;
 
-    /** MBA0_MBSECCFIR[2]
+    /** MBSECCFIR_0[2]
      *  Memory chip mark on rank 2
      */
     (Mba0_MbsEccFir, bit(2)) ? analyzeFetchMpe0_2;
 
-    /** MBA1_MBSECCFIR[2]
+    /** MBSECCFIR_1[2]
      *  Memory chip mark on rank 2
      */
     (Mba1_MbsEccFir, bit(2)) ? analyzeFetchMpe1_2;
 
-    /** MBA0_MBSECCFIR[3]
+    /** MBSECCFIR_0[3]
      *  Memory chip mark on rank 3
      */
     (Mba0_MbsEccFir, bit(3)) ? analyzeFetchMpe0_3;
 
-    /** MBA1_MBSECCFIR[3]
+    /** MBSECCFIR_1[3]
      *  Memory chip mark on rank 3
      */
     (Mba1_MbsEccFir, bit(3)) ? analyzeFetchMpe1_3;
 
-    /** MBA0_MBSECCFIR[4]
+    /** MBSECCFIR_0[4]
      *  Memory chip mark on rank 4
      */
     (Mba0_MbsEccFir, bit(4)) ? analyzeFetchMpe0_4;
 
-    /** MBA1_MBSECCFIR[4]
+    /** MBSECCFIR_1[4]
      *  Memory chip mark on rank 4
      */
     (Mba1_MbsEccFir, bit(4)) ? analyzeFetchMpe1_4;
 
-    /** MBA0_MBSECCFIR[5]
+    /** MBSECCFIR_0[5]
      *  Memory chip mark on rank 5
      */
     (Mba0_MbsEccFir, bit(5)) ? analyzeFetchMpe0_5;
 
-    /** MBA1_MBSECCFIR[5]
+    /** MBSECCFIR_1[5]
      *  Memory chip mark on rank 5
      */
     (Mba1_MbsEccFir, bit(5)) ? analyzeFetchMpe1_5;
 
-    /** MBA0_MBSECCFIR[6]
+    /** MBSECCFIR_0[6]
      *  Memory chip mark on rank 6
      */
     (Mba0_MbsEccFir, bit(6)) ? analyzeFetchMpe0_6;
 
-    /** MBA1_MBSECCFIR[6]
+    /** MBSECCFIR_1[6]
      *  Memory chip mark on rank 6
      */
     (Mba1_MbsEccFir, bit(6)) ? analyzeFetchMpe1_6;
 
-    /** MBA0_MBSECCFIR[7]
+    /** MBSECCFIR_0[7]
      *  Memory chip mark on rank 7
      */
     (Mba0_MbsEccFir, bit(7)) ? analyzeFetchMpe0_7;
 
-    /** MBA1_MBSECCFIR[7]
+    /** MBSECCFIR_1[7]
      *  Memory chip mark on rank 7
      */
     (Mba1_MbsEccFir, bit(7)) ? analyzeFetchMpe1_7;
 
-    /** MBA0_MBSECCFIR[8:15]
+    /** MBSECCFIR_0[8:15]
      *  Reserved
      */
     (Mba0_MbsEccFir, bit(8|9|10|11|12|13|14|15)) ? defaultMaskedError;
 
-    /** MBA1_MBSECCFIR[8:15]
+    /** MBSECCFIR_1[8:15]
      *  Reserved
      */
     (Mba1_MbsEccFir, bit(8|9|10|11|12|13|14|15)) ? defaultMaskedError;
 
-    /** MBA0_MBSECCFIR[16]
+    /** MBSECCFIR_0[16]
      *  Memory NCE
      */
     (Mba0_MbsEccFir, bit(16)) ? analyzeFetchNce0;
 
-    /** MBA1_MBSECCFIR[16]
+    /** MBSECCFIR_1[16]
      *  Memory NCE
      */
     (Mba1_MbsEccFir, bit(16)) ? analyzeFetchNce1;
 
-    /** MBA0_MBSECCFIR[17]
+    /** MBSECCFIR_0[17]
      *  Memory RCE
      */
     (Mba0_MbsEccFir, bit(17)) ? analyzeFetchRce0;
 
-    /** MBA1_MBSECCFIR[17]
+    /** MBSECCFIR_1[17]
      *  Memory RCE
      */
     (Mba1_MbsEccFir, bit(17)) ? analyzeFetchRce1;
 
-    /** MBA0_MBSECCFIR[18]
+    /** MBSECCFIR_0[18]
      *  Memory SUE
      */
     (Mba0_MbsEccFir, bit(18)) ? defaultMaskedError;
 
-    /** MBA1_MBSECCFIR[18]
+    /** MBSECCFIR_1[18]
      *  Memory SUE
      */
     (Mba1_MbsEccFir, bit(18)) ? defaultMaskedError;
 
-    /** MBA0_MBSECCFIR[19]
+    /** MBSECCFIR_0[19]
      *  Memory UE
      */
     (Mba0_MbsEccFir, bit(19)) ? mba0MemoryUe;
 
-    /** MBA1_MBSECCFIR[19]
+    /** MBSECCFIR_1[19]
      *  Memory UE
      */
     (Mba1_MbsEccFir, bit(19)) ? mba1MemoryUe;
 
-    /** MBA0_MBSECCFIR[20:27]
+    /** MBSECCFIR_0[20:27]
      *  Maintenance chip mark
      */
     (Mba0_MbsEccFir, bit(20|21|22|23|24|25|26|27)) ? defaultMaskedError;
 
-    /** MBA1_MBSECCFIR[20:27]
+    /** MBSECCFIR_1[20:27]
      *  Maintenance chip mark
      */
     (Mba1_MbsEccFir, bit(20|21|22|23|24|25|26|27)) ? defaultMaskedError;
 
-    /** MBA0_MBSECCFIR[28:35]
+    /** MBSECCFIR_0[28:35]
      *  Reserved
      */
     (Mba0_MbsEccFir, bit(28|29|30|31|32|33|34|35)) ? defaultMaskedError;
 
-    /** MBA1_MBSECCFIR[28:35]
+    /** MBSECCFIR_1[28:35]
      *  Reserved
      */
     (Mba1_MbsEccFir, bit(28|29|30|31|32|33|34|35)) ? defaultMaskedError;
 
-    /** MBA0_MBSECCFIR[36]
+    /** MBSECCFIR_0[36]
      *  Maintenance NCE
      */
     (Mba0_MbsEccFir, bit(36)) ? defaultMaskedError;
 
-    /** MBA1_MBSECCFIR[36]
+    /** MBSECCFIR_1[36]
      *  Maintenance NCE
      */
     (Mba1_MbsEccFir, bit(36)) ? defaultMaskedError;
 
-    /** MBA0_MBSECCFIR[37]
+    /** MBSECCFIR_0[37]
      *  Maintenance SCE
      */
     (Mba0_MbsEccFir, bit(37)) ? defaultMaskedError;
 
-    /** MBA1_MBSECCFIR[37]
+    /** MBSECCFIR_1[37]
      *  Maintenance SCE
      */
     (Mba1_MbsEccFir, bit(37)) ? defaultMaskedError;
 
-    /** MBA0_MBSECCFIR[38]
+    /** MBSECCFIR_0[38]
      *  Maintenance MCE
      */
     (Mba0_MbsEccFir, bit(38)) ? defaultMaskedError;
 
-    /** MBA1_MBSECCFIR[38]
+    /** MBSECCFIR_1[38]
      *  Maintenance MCE
      */
     (Mba1_MbsEccFir, bit(38)) ? defaultMaskedError;
 
-    /** MBA0_MBSECCFIR[39]
+    /** MBSECCFIR_0[39]
      *  Maintenance RCE
      */
     (Mba0_MbsEccFir, bit(39)) ? defaultMaskedError;
 
-    /** MBA1_MBSECCFIR[39]
+    /** MBSECCFIR_1[39]
      *  Maintenance RCE
      */
     (Mba1_MbsEccFir, bit(39)) ? defaultMaskedError;
 
-    /** MBA0_MBSECCFIR[40]
+    /** MBSECCFIR_0[40]
      *  Maintenance SUE
      */
     (Mba0_MbsEccFir, bit(40)) ? defaultMaskedError;
 
-    /** MBA1_MBSECCFIR[40]
+    /** MBSECCFIR_1[40]
      *  Maintenance SUE
      */
     (Mba1_MbsEccFir, bit(40)) ? defaultMaskedError;
 
-    /** MBA0_MBSECCFIR[41]
+    /** MBSECCFIR_0[41]
      *  Maintenance UE
      */
     (Mba0_MbsEccFir, bit(41)) ? defaultMaskedError;
 
-    /** MBA1_MBSECCFIR[41]
+    /** MBSECCFIR_1[41]
      *  Maintenance UE
      */
     (Mba1_MbsEccFir, bit(41)) ? defaultMaskedError;
 
-    /** MBA0_MBSECCFIR[42]
+    /** MBSECCFIR_0[42]
      *  MBECCFIR_MPE_DURING_USE_MAINTENANCE_MARK_MODE
      */
     (Mba0_MbsEccFir, bit(42)) ? defaultMaskedError;
 
-    /** MBA1_MBSECCFIR[42]
+    /** MBSECCFIR_1[42]
      *  MBECCFIR_MPE_DURING_USE_MAINTENANCE_MARK_MODE
      */
     (Mba1_MbsEccFir, bit(42)) ? defaultMaskedError;
 
-    /** MBA0_MBSECCFIR[43]
+    /** MBSECCFIR_0[43]
      *  MBECCFIR_PREFETCH_MEMORY_UE
      */
     (Mba0_MbsEccFir, bit(43)) ? analyzeFetchPreUe0;
 
-    /** MBA1_MBSECCFIR[43]
+    /** MBSECCFIR_1[43]
      *  MBECCFIR_PREFETCH_MEMORY_UE
      */
     (Mba1_MbsEccFir, bit(43)) ? analyzeFetchPreUe1;
 
-    /** MBA0_MBSECCFIR[44]
+    /** MBSECCFIR_0[44]
      *  MBECCFIR_MEMORY_RCD_PARITY_ERROR
      */
     (Mba0_MbsEccFir, bit(44)) ? defaultMaskedError;
 
-    /** MBA1_MBSECCFIR[44]
+    /** MBSECCFIR_1[44]
      *  MBECCFIR_MEMORY_RCD_PARITY_ERROR
      */
     (Mba1_MbsEccFir, bit(44)) ? defaultMaskedError;
 
-    /** MBA0_MBSECCFIR[45]
+    /** MBSECCFIR_0[45]
      *  MBECCFIR_MAINTENANCE_RCD_PARITY_ERROR
      */
     (Mba0_MbsEccFir, bit(45)) ? defaultMaskedError;
 
-    /** MBA1_MBSECCFIR[45]
+    /** MBSECCFIR_1[45]
      *  MBECCFIR_MAINTENANCE_RCD_PARITY_ERROR
      */
     (Mba1_MbsEccFir, bit(45)) ? defaultMaskedError;
 
-    /** MBA0_MBSECCFIR[46]
+    /** MBSECCFIR_0[46]
      *  MBECCFIR_RECOVERABLE_CONFIGURATION_REGISTER_PARITY_ERROR
      */
     (Mba0_MbsEccFir, bit(46)) ? MBA0CalloutMedThr1;
 
-    /** MBA1_MBSECCFIR[46]
+    /** MBSECCFIR_1[46]
      *  MBECCFIR_RECOVERABLE_CONFIGURATION_REGISTER_PARITY_ERROR
      */
     (Mba1_MbsEccFir, bit(46)) ? MBA1CalloutMedThr1;
 
-    /** MBA0_MBSECCFIR[47]
+    /** MBSECCFIR_0[47]
      *  MBECCFIR_UNRECOVERABLE_CONFIGURATION_REGISTER_PARITY_ERROR
      */
     (Mba0_MbsEccFir, bit(47)) ? MBA0CalloutMedThr1UE;
 
-    /** MBA1_MBSECCFIR[47]
+    /** MBSECCFIR_1[47]
      *  MBECCFIR_UNRECOVERABLE_CONFIGURATION_REGISTER_PARITY_ERROR
      */
     (Mba1_MbsEccFir, bit(47)) ? MBA1CalloutMedThr1UE;
 
-    /** MBA0_MBSECCFIR[48]
+    /** MBSECCFIR_0[48]
      *  MBECCFIR_MASKABLE_CONFIGURATION_REGISTER_PARITY_ERROR
      */
     (Mba0_MbsEccFir, bit(48)) ? thresholdAndMask_mba0;
 
-    /** MBA1_MBSECCFIR[48]
+    /** MBSECCFIR_1[48]
      *  MBECCFIR_MASKABLE_CONFIGURATION_REGISTER_PARITY_ERROR
      */
     (Mba1_MbsEccFir, bit(48)) ? thresholdAndMask_mba1;
 
-    /** MBA0_MBSECCFIR[49]
+    /** MBSECCFIR_0[49]
      *  MBECCFIR_ECC_DATAPATH_PARITY_ERROR
      */
     (Mba0_MbsEccFir, bit(49)) ? MBA0CalloutMedThr1UE;
 
-    /** MBA1_MBSECCFIR[49]
+    /** MBSECCFIR_1[49]
      *  MBECCFIR_ECC_DATAPATH_PARITY_ERROR
      */
     (Mba1_MbsEccFir, bit(49)) ? MBA1CalloutMedThr1UE;
 
-    /** MBA0_MBSECCFIR[50]
+    /** MBSECCFIR_0[50]
      *  MBECCFIR_INTERNAL_SCOM_ERROR
      */
     (Mba0_MbsEccFir, bit(50)) ? thresholdAndMask_mba0;
 
-    /** MBA1_MBSECCFIR[50]
+    /** MBSECCFIR_1[50]
      *  MBECCFIR_INTERNAL_SCOM_ERROR
      */
     (Mba1_MbsEccFir, bit(50)) ? thresholdAndMask_mba1;
 
-    /** MBA0_MBSECCFIR[51]
+    /** MBSECCFIR_0[51]
      *  MBECCFIR_INTERNAL_SCOM_ERROR_COPY
      */
     (Mba0_MbsEccFir, bit(51)) ? thresholdAndMask_mba0;
 
-    /** MBA1_MBSECCFIR[51]
+    /** MBSECCFIR_1[51]
      *  MBECCFIR_INTERNAL_SCOM_ERROR_COPY
      */
     (Mba1_MbsEccFir, bit(51)) ? thresholdAndMask_mba1;
@@ -1119,97 +1119,97 @@ group gMbsEccFir filter priority ( 19, 41 ),
 
 rule Mba0_McbistFir
 {
-  CHECK_STOP:   MBA0_MCBISTFIR      & ~MBA0_MCBISTFIR_MASK &
-               ~MBA0_MCBISTFIR_ACT0 & ~MBA0_MCBISTFIR_ACT1;
-  UNIT_CS:      MBA0_MCBISTFIR      & ~MBA0_MCBISTFIR_MASK &
-               ~MBA0_MCBISTFIR_ACT0 & ~MBA0_MCBISTFIR_ACT1;
-  RECOVERABLE:  MBA0_MCBISTFIR      & ~MBA0_MCBISTFIR_MASK &
-               ~MBA0_MCBISTFIR_ACT0 &  MBA0_MCBISTFIR_ACT1;
+  CHECK_STOP:   MCBISTFIR_0      & ~MCBISTFIR_0_MASK &
+               ~MCBISTFIR_0_ACT0 & ~MCBISTFIR_0_ACT1;
+  UNIT_CS:      MCBISTFIR_0      & ~MCBISTFIR_0_MASK &
+               ~MCBISTFIR_0_ACT0 & ~MCBISTFIR_0_ACT1;
+  RECOVERABLE:  MCBISTFIR_0      & ~MCBISTFIR_0_MASK &
+               ~MCBISTFIR_0_ACT0 &  MCBISTFIR_0_ACT1;
 };
 
 rule Mba1_McbistFir
 {
-  CHECK_STOP:   MBA1_MCBISTFIR      & ~MBA1_MCBISTFIR_MASK &
-               ~MBA1_MCBISTFIR_ACT0 & ~MBA1_MCBISTFIR_ACT1;
-  UNIT_CS:      MBA1_MCBISTFIR      & ~MBA1_MCBISTFIR_MASK &
-               ~MBA1_MCBISTFIR_ACT0 & ~MBA1_MCBISTFIR_ACT1;
-  RECOVERABLE:  MBA1_MCBISTFIR      & ~MBA1_MCBISTFIR_MASK &
-               ~MBA1_MCBISTFIR_ACT0 &  MBA1_MCBISTFIR_ACT1;
+  CHECK_STOP:   MCBISTFIR_1      & ~MCBISTFIR_1_MASK &
+               ~MCBISTFIR_1_ACT0 & ~MCBISTFIR_1_ACT1;
+  UNIT_CS:      MCBISTFIR_1      & ~MCBISTFIR_1_MASK &
+               ~MCBISTFIR_1_ACT0 & ~MCBISTFIR_1_ACT1;
+  RECOVERABLE:  MCBISTFIR_1      & ~MCBISTFIR_1_MASK &
+               ~MCBISTFIR_1_ACT0 &  MCBISTFIR_1_ACT1;
 };
 
 group gMcbistFir filter singlebit,
                         secondarybits(2,3,4,5,6,7,8,9,10,11,12,13,14,15,16)
 {
-    /** MBA0_MCBISTFIR[0]
+    /** MCBISTFIR_0[0]
      *  MBSFIRQ_SCOM_PAR_ERRORS
      */
     (Mba0_McbistFir, bit(0)) ? MBA0CalloutMedThr1;
 
-    /** MBA1_MCBISTFIR[0]
+    /** MCBISTFIR_1[0]
      *  MBSFIRQ_SCOM_PAR_ERRORS
      */
     (Mba1_McbistFir, bit(0)) ? MBA1CalloutMedThr1;
 
-    /** MBA0_MCBISTFIR[1]
+    /** MCBISTFIR_0[1]
      *  MBSFIRQ_MBX_PAR_ERRORS
      */
     (Mba0_McbistFir, bit(1)) ? MBA0CalloutMedThr1;
 
-    /** MBA1_MCBISTFIR[1]
+    /** MCBISTFIR_1[1]
      *  MBSFIRQ_MBX_PAR_ERRORS
      */
     (Mba1_McbistFir, bit(1)) ? MBA1CalloutMedThr1;
 
     # This is for DD2 only
-    /** MBA0_MCBISTFIR[2]
+    /** MCBISTFIR_0[2]
      *  MBSFIRQ_DRAM_EVENT_BIT0
      */
     (Mba0_McbistFir, bit(2)) ? defaultMaskedError;
 
     # This is for DD2 only
-    /** MBA1_MCBISTFIR[2]
+    /** MCBISTFIR_1[2]
      *  MBSFIRQ_DRAM_EVENT_BIT0
      */
     (Mba1_McbistFir, bit(2)) ? defaultMaskedError;
 
     # This is for DD2 only
-    /** MBA0_MCBISTFIR[3]
+    /** MCBISTFIR_0[3]
      *  MBSFIRQ_DRAM_EVENT_BIT1
      */
     (Mba0_McbistFir, bit(3)) ? defaultMaskedError;
 
     # This is for DD2 only
-    /** MBA1_MCBISTFIR[3]
+    /** MCBISTFIR_1[3]
      *  MBSFIRQ_DRAM_EVENT_BIT1
      */
     (Mba1_McbistFir, bit(3)) ? defaultMaskedError;
 
-    /** MBA0_MCBISTFIR[4:14]
+    /** MCBISTFIR_0[4:14]
      *  Reserved
      */
     (Mba0_McbistFir, bit(4|5|6|7|8|9|10|11|12|13|14)) ? defaultMaskedError;
 
-    /** MBA1_MCBISTFIR[4:14]
+    /** MCBISTFIR_1[4:14]
      *  Reserved
      */
     (Mba1_McbistFir, bit(4|5|6|7|8|9|10|11|12|13|14)) ? defaultMaskedError;
 
-    /** MBA0_MCBISTFIR[15]
+    /** MCBISTFIR_0[15]
      *  MBSFIRQ_INTERNAL_SCOM_ERROR
      */
     (Mba0_McbistFir, bit(15)) ? thresholdAndMask_mba0;
 
-    /** MBA1_MCBISTFIR[15]
+    /** MCBISTFIR_1[15]
      *  MBSFIRQ_INTERNAL_SCOM_ERROR
      */
     (Mba1_McbistFir, bit(15)) ? thresholdAndMask_mba1;
 
-    /** MBA0_MCBISTFIR[16]
+    /** MCBISTFIR_0[16]
      *  MBSFIRQ_INTERNAL_SCOM_ERROR_CLONE
      */
     (Mba0_McbistFir, bit(16)) ? thresholdAndMask_mba0;
 
-    /** MBA1_MCBISTFIR[16]
+    /** MCBISTFIR_1[16]
      *  MBSFIRQ_INTERNAL_SCOM_ERROR_CLONE
      */
     (Mba1_McbistFir, bit(16)) ? thresholdAndMask_mba1;
diff --git a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule b/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule
index cefff3c11..d53d22120 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule
+++ b/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule
@@ -5,7 +5,7 @@
 #
 # OpenPOWER HostBoot Project
 #
-# Contributors Listed Below - COPYRIGHT 2012,2016
+# Contributors Listed Below - COPYRIGHT 2012,2018
 # [+] International Business Machines Corp.
 #
 #
@@ -244,10 +244,10 @@
     };
 
     ############################################################################
-    # NEST Chiplet MBA0_MBSECCFIR
+    # NEST Chiplet MBSECCFIR_0
     ############################################################################
 
-    register MBA0_MBSECCFIR
+    register MBSECCFIR_0
     {
         name        "MBU.MBS.ECC01.MBECCFIR";
         scomaddr    0x02011440;
@@ -258,7 +258,7 @@
         capture     group MaintCmdRegs_mba0;
     };
 
-    register MBA0_MBSECCFIR_AND
+    register MBSECCFIR_0_AND
     {
         name        "MBU.MBS.ECC01.MBECCFIR_AND";
         scomaddr    0x02011441;
@@ -266,7 +266,7 @@
         access      write_only;
     };
 
-    register MBA0_MBSECCFIR_MASK
+    register MBSECCFIR_0_MASK
     {
         name        "MBU.MBS.ECC01.MBECCFIR_MASK";
         scomaddr    0x02011443;
@@ -275,7 +275,7 @@
         capture     group MaintCmdRegs_mba0;
     };
 
-    register MBA0_MBSECCFIR_MASK_AND
+    register MBSECCFIR_0_MASK_AND
     {
         name        "MBU.MBS.ECC01.MBECCFIR_MASK_AND";
         scomaddr    0x02011444;
@@ -283,7 +283,7 @@
         access      write_only;
     };
 
-    register MBA0_MBSECCFIR_MASK_OR
+    register MBSECCFIR_0_MASK_OR
     {
         name        "MBU.MBS.ECC01.MBECCFIR_MASK_OR";
         scomaddr    0x02011445;
@@ -291,7 +291,7 @@
         access      write_only;
     };
 
-    register MBA0_MBSECCFIR_ACT0
+    register MBSECCFIR_0_ACT0
     {
         name        "MBU.MBS.ECC01.MBECCFIR_ACTION0";
         scomaddr    0x02011446;
@@ -299,10 +299,10 @@
         capture     group default;
         capture     group FirRegs;
         capture     group MaintCmdRegs_mba0;
-        capture     req nonzero("MBA0_MBSECCFIR");
+        capture     req nonzero("MBSECCFIR_0");
     };
 
-    register MBA0_MBSECCFIR_ACT1
+    register MBSECCFIR_0_ACT1
     {
         name        "MBU.MBS.ECC01.MBECCFIR_ACTION1";
         scomaddr    0x02011447;
@@ -310,14 +310,14 @@
         capture     group default;
         capture     group FirRegs;
         capture     group MaintCmdRegs_mba0;
-        capture     req nonzero("MBA0_MBSECCFIR");
+        capture     req nonzero("MBSECCFIR_0");
     };
 
     ############################################################################
-    # NEST Chiplet MBA1_MBSECCFIR
+    # NEST Chiplet MBSECCFIR_1
     ############################################################################
 
-    register MBA1_MBSECCFIR
+    register MBSECCFIR_1
     {
         name        "MBU.MBS.ECC23.MBECCFIR";
         scomaddr    0x02011480;
@@ -328,7 +328,7 @@
         capture     group MaintCmdRegs_mba1;
     };
 
-    register MBA1_MBSECCFIR_AND
+    register MBSECCFIR_1_AND
     {
         name        "MBU.MBS.ECC23.MBECCFIR_AND";
         scomaddr    0x02011481;
@@ -336,7 +336,7 @@
         access      write_only;
     };
 
-    register MBA1_MBSECCFIR_MASK
+    register MBSECCFIR_1_MASK
     {
         name        "MBU.MBS.ECC23.MBECCFIR_MASK";
         scomaddr    0x02011483;
@@ -345,7 +345,7 @@
         capture     group MaintCmdRegs_mba1;
     };
 
-    register MBA1_MBSECCFIR_MASK_AND
+    register MBSECCFIR_1_MASK_AND
     {
         name        "MBU.MBS.ECC23.MBECCFIR_MASK_AND";
         scomaddr    0x02011484;
@@ -353,7 +353,7 @@
         access      write_only;
     };
 
-    register MBA1_MBSECCFIR_MASK_OR
+    register MBSECCFIR_1_MASK_OR
     {
         name        "MBU.MBS.ECC23.MBECCFIR_MASK_OR";
         scomaddr    0x02011485;
@@ -361,7 +361,7 @@
         access      write_only;
     };
 
-    register MBA1_MBSECCFIR_ACT0
+    register MBSECCFIR_1_ACT0
     {
         name        "MBU.MBS.ECC23.MBECCFIR_ACTION0";
         scomaddr    0x02011486;
@@ -369,10 +369,10 @@
         capture     group default;
         capture     group FirRegs;
         capture     group MaintCmdRegs_mba1;
-        capture     req nonzero("MBA1_MBSECCFIR");
+        capture     req nonzero("MBSECCFIR_1");
     };
 
-    register MBA1_MBSECCFIR_ACT1
+    register MBSECCFIR_1_ACT1
     {
         name        "MBU.MBS.ECC23.MBECCFIR_ACTION0";
         scomaddr    0x02011487;
@@ -380,14 +380,14 @@
         capture     group default;
         capture     group FirRegs;
         capture     group MaintCmdRegs_mba1;
-        capture     req nonzero("MBA1_MBSECCFIR");
+        capture     req nonzero("MBSECCFIR_1");
     };
 
     ############################################################################
-    # NEST Chiplet MBA0_MCBISTFIR
+    # NEST Chiplet MCBISTFIR_0
     ############################################################################
 
-    register MBA0_MCBISTFIR
+    register MCBISTFIR_0
     {
         name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSFIRQ";
         scomaddr    0x02011600;
@@ -397,7 +397,7 @@
         capture     group FirRegs;
     };
 
-    register MBA0_MCBISTFIR_MASK
+    register MCBISTFIR_0_MASK
     {
         name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSFIRMASK";
         scomaddr    0x02011603;
@@ -405,31 +405,31 @@
         capture     group FirRegs;
     };
 
-    register MBA0_MCBISTFIR_ACT0
+    register MCBISTFIR_0_ACT0
     {
         name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSFIRACTION0";
         scomaddr    0x02011606;
         capture     type secondary;
         capture     group default;
         capture     group FirRegs;
-        capture     req nonzero("MBA0_MCBISTFIR");
+        capture     req nonzero("MCBISTFIR_0");
     };
 
-    register MBA0_MCBISTFIR_ACT1
+    register MCBISTFIR_0_ACT1
     {
         name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSFIRACTION1";
         scomaddr    0x02011607;
         capture     type secondary;
         capture     group default;
         capture     group FirRegs;
-        capture     req nonzero("MBA0_MCBISTFIR");
+        capture     req nonzero("MCBISTFIR_0");
     };
 
     ############################################################################
-    # NEST Chiplet MBA1_MCBISTFIR
+    # NEST Chiplet MCBISTFIR_1
     ############################################################################
 
-    register MBA1_MCBISTFIR
+    register MCBISTFIR_1
     {
         name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSFIRQ";
         scomaddr    0x02011700;
@@ -439,7 +439,7 @@
         capture     group FirRegs;
     };
 
-    register MBA1_MCBISTFIR_MASK
+    register MCBISTFIR_1_MASK
     {
         name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSFIRMASK";
         scomaddr    0x02011703;
@@ -447,24 +447,24 @@
         capture     group FirRegs;
     };
 
-    register MBA1_MCBISTFIR_ACT0
+    register MCBISTFIR_1_ACT0
     {
         name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSFIRACTION0";
         scomaddr    0x02011706;
         capture     type secondary;
         capture     group default;
         capture     group FirRegs;
-        capture     req nonzero("MBA1_MCBISTFIR");
+        capture     req nonzero("MCBISTFIR_1");
     };
 
-    register MBA1_MCBISTFIR_ACT1
+    register MCBISTFIR_1_ACT1
     {
         name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSFIRACTION1";
         scomaddr    0x02011707;
         capture     type secondary;
         capture     group default;
         capture     group FirRegs;
-        capture     req nonzero("MBA1_MCBISTFIR");
+        capture     req nonzero("MCBISTFIR_1");
     };
 
     ############################################################################
@@ -734,7 +734,7 @@
     # NEST Chiplet memory maintenance threshold control registers
     ############################################################################
 
-    register MBA0_MBSTR
+    register MBSTR_0
     {
         name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSTRQ";
         scomaddr    0x02011655;
@@ -742,7 +742,7 @@
         capture     group MaintCmdRegs_mba0;
     };
 
-    register MBA1_MBSTR
+    register MBSTR_1
     {
         name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSTRQ";
         scomaddr    0x02011755;
diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaTdCtlr_common.C b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaTdCtlr_common.C
index 02e6c0fd9..0a30244e0 100644
--- a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaTdCtlr_common.C
+++ b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaTdCtlr_common.C
@@ -162,7 +162,7 @@ int32_t CenMbaTdCtlrCommon::prepareNextCmd( bool i_clearStats )
 
         if ( i_clearStats )
         {
-            reg_str = (0 == iv_mbaPos) ? "MBA0_MBSTR" : "MBA1_MBSTR";
+            reg_str = (0 == iv_mbaPos) ? "MBSTR_0" : "MBSTR_1";
             SCAN_COMM_REGISTER_CLASS * mbstr =
                                     iv_membChip->getRegister( reg_str );
 
@@ -195,8 +195,7 @@ int32_t CenMbaTdCtlrCommon::prepareNextCmd( bool i_clearStats )
         // Clear ECC FIRs
         //----------------------------------------------------------------------
 
-        reg_str = (0 == iv_mbaPos) ? "MBA0_MBSECCFIR_AND"
-                                   : "MBA1_MBSECCFIR_AND";
+        reg_str = (0 == iv_mbaPos) ? "MBSECCFIR_0_AND" : "MBSECCFIR_1_AND";
         SCAN_COMM_REGISTER_CLASS * firand = iv_membChip->getRegister( reg_str );
         firand->setAllBits();
 
@@ -283,8 +282,7 @@ int32_t CenMbaTdCtlrCommon::checkEccErrors( uint16_t & o_eccErrorMask,
 
     do
     {
-        const char * reg_str = (0 == iv_mbaPos) ? "MBA0_MBSECCFIR"
-                                                : "MBA1_MBSECCFIR";
+        const char * reg_str = (0 == iv_mbaPos) ? "MBSECCFIR_0" : "MBSECCFIR_1";
         SCAN_COMM_REGISTER_CLASS * mbsEccFir
                                         = iv_membChip->getRegister( reg_str );
         o_rc = mbsEccFir->Read();
diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaTdCtlr_rt.C b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaTdCtlr_rt.C
index b1b6aa194..501fc4fe5 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaTdCtlr_rt.C
+++ b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaTdCtlr_rt.C
@@ -228,17 +228,17 @@ int32_t CenMbaTdCtlr::handleTdEvent( STEP_CODE_DATA_STRUCT & io_sc,
 
         const char * membRegs[2][18] =
         {
-            { "MBA0_MBSECCFIR", "MBA0_MBSECCFIR_MASK",
-              "MBA0_MBSECCFIR_ACT0", "MBA0_MBSECCFIR_ACT1",
+            { "MBSECCFIR_0", "MBSECCFIR_0_MASK",
+              "MBSECCFIR_0_ACT0", "MBSECCFIR_0_ACT1",
               "MBA0_MBSECCERRPT_0","MBA0_MBSECCERRPT_1",
-              "MBA0_MBSEC0", "MBA0_MBSEC1", "MBA0_MBSTR",
+              "MBA0_MBSEC0", "MBA0_MBSEC1", "MBSTR_0",
               "MBA0_MBSSYMEC0", "MBA0_MBSSYMEC1", "MBA0_MBSSYMEC2",
               "MBA0_MBSSYMEC3", "MBA0_MBSSYMEC4", "MBA0_MBSSYMEC5",
               "MBA0_MBSSYMEC6", "MBA0_MBSSYMEC7", "MBA0_MBSSYMEC8", },
-            { "MBA1_MBSECCFIR", "MBA1_MBSECCFIR_MASK",
-              "MBA1_MBSECCFIR_ACT0", "MBA1_MBSECCFIR_ACT1",
+            { "MBSECCFIR_1", "MBSECCFIR_1_MASK",
+              "MBSECCFIR_1_ACT0", "MBSECCFIR_1_ACT1",
               "MBA1_MBSECCERRPT_0","MBA1_MBSECCERRPT_1",
-              "MBA1_MBSEC0", "MBA1_MBSEC1", "MBA1_MBSTR",
+              "MBA1_MBSEC0", "MBA1_MBSEC1", "MBSTR_1",
               "MBA1_MBSSYMEC0", "MBA1_MBSSYMEC1", "MBA1_MBSSYMEC2",
               "MBA1_MBSSYMEC3", "MBA1_MBSSYMEC4", "MBA1_MBSSYMEC5",
               "MBA1_MBSSYMEC6", "MBA1_MBSSYMEC7", "MBA1_MBSSYMEC8", },
@@ -458,8 +458,8 @@ int32_t CenMbaTdCtlr::initialize()
         // already in the queue. This is reset/reload safe because initialize()
         // will be called again and we can redetect the unverified chip marks.
 
-        const char * reg_str = (0 == iv_mbaPos) ? "MBA0_MBSECCFIR_AND"
-                                                : "MBA1_MBSECCFIR_AND";
+        const char * reg_str = (0 == iv_mbaPos) ? "MBSECCFIR_0_AND"
+                                                : "MBSECCFIR_1_AND";
         SCAN_COMM_REGISTER_CLASS * firand = iv_membChip->getRegister( reg_str );
         firand->setAllBits();
 
@@ -1874,8 +1874,8 @@ int32_t CenMbaTdCtlr::handleMpe_Tps( STEP_CODE_DATA_STRUCT & io_sc )
 
         // Clear the scrub attention. This is needed later if we need to write
         // markstore for a symbol mark.
-        const char * fir_str = (0 == iv_mbaPos) ? "MBA0_MBSECCFIR_AND"
-                                                : "MBA1_MBSECCFIR_AND";
+        const char * fir_str = (0 == iv_mbaPos) ? "MBSECCFIR_0_AND"
+                                                : "MBSECCFIR_1_AND";
 
         SCAN_COMM_REGISTER_CLASS * fir = iv_membChip->getRegister( fir_str );
 
@@ -2566,8 +2566,8 @@ int32_t CenMbaTdCtlr::tpsSymbolMark( STEP_CODE_DATA_STRUCT & io_sc )
         }
 
         // Clear the fetch attention before attempting the rewrite.
-        const char * reg_str = (0 == iv_mbaPos) ? "MBA0_MBSECCFIR_AND"
-                                                : "MBA1_MBSECCFIR_AND";
+        const char * reg_str = (0 == iv_mbaPos) ? "MBSECCFIR_0_AND"
+                                                : "MBSECCFIR_1_AND";
         SCAN_COMM_REGISTER_CLASS * firand = iv_membChip->getRegister( reg_str );
         firand->setAllBits();
         firand->ClearBit( 0 + iv_rank.getMaster() ); // fetch
@@ -2608,8 +2608,8 @@ int32_t CenMbaTdCtlr::maskFetchAttns()
         // Don't want to handle memory CEs during any TD procedures, so
         // mask them.
 
-        const char * reg_str = (0 == iv_mbaPos) ? "MBA0_MBSECCFIR_MASK_OR"
-                                                : "MBA1_MBSECCFIR_MASK_OR";
+        const char * reg_str = (0 == iv_mbaPos) ? "MBSECCFIR_0_MASK_OR"
+                                                : "MBSECCFIR_1_MASK_OR";
         SCAN_COMM_REGISTER_CLASS * reg = iv_membChip->getRegister(reg_str);
 
         reg->clearAllBits();
@@ -2647,10 +2647,10 @@ int32_t CenMbaTdCtlr::unmaskFetchAttns()
         // clear and unmask them. Also, it is possible that memory UEs have
         // thresholded so clear and unmask them as well.
 
-        const char * fir_str = (0 == iv_mbaPos) ? "MBA0_MBSECCFIR_AND"
-                                                : "MBA1_MBSECCFIR_AND";
-        const char * msk_str = (0 == iv_mbaPos) ? "MBA0_MBSECCFIR_MASK_AND"
-                                                : "MBA1_MBSECCFIR_MASK_AND";
+        const char * fir_str = (0 == iv_mbaPos) ? "MBSECCFIR_0_AND"
+                                                : "MBSECCFIR_1_AND";
+        const char * msk_str = (0 == iv_mbaPos) ? "MBSECCFIR_0_MASK_AND"
+                                                : "MBSECCFIR_1_MASK_AND";
 
         SCAN_COMM_REGISTER_CLASS * fir = iv_membChip->getRegister( fir_str );
         SCAN_COMM_REGISTER_CLASS * msk = iv_membChip->getRegister( msk_str );
diff --git a/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C b/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C
index cbadf5011..6e64eebc9 100644
--- a/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C
+++ b/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C
@@ -544,11 +544,11 @@ void getAddresses( TrgtMap_t & io_targMap )
         0x02010400, // DMIFIR
         0x02010800, // MBIFIR
         0x02011400, // MBSFIR
-        0x02011440, // MBA0_MBSECCFIR
-        0x02011480, // MBA1_MBSECCFIR
+        0x02011440, // MBSECCFIR_0
+        0x02011480, // MBSECCFIR_1
         0x020115c0, // SCACFIR
-        0x02011600, // MBA0_MCBISTFIR
-        0x02011700, // MBA1_MCBISTFIR
+        0x02011600, // MCBISTFIR_0
+        0x02011700, // MCBISTFIR_1
         0x0204000a, // NEST_LFIR
         0x0304000a, // MEM_LFIR
     };
@@ -611,7 +611,7 @@ void getAddresses( TrgtMap_t & io_targMap )
         // Other ECC regs (won't be used in analysis, but could be useful FFDC)
         0x02011653, // MBA0_MBSEC0
         0x02011654, // MBA0_MBSEC1
-        0x02011655, // MBA0_MBSTR
+        0x02011655, // MBSTR_0
         0x02011656, // MBA0_MBSSYMEC0
         0x02011657, // MBA0_MBSSYMEC1
         0x02011658, // MBA0_MBSSYMEC2
@@ -623,7 +623,7 @@ void getAddresses( TrgtMap_t & io_targMap )
         0x0201165e, // MBA0_MBSSYMEC8
         0x02011753, // MBA1_MBSEC0
         0x02011754, // MBA1_MBSEC1
-        0x02011755, // MBA1_MBSTR
+        0x02011755, // MBSTR_1
         0x02011756, // MBA1_MBSSYMEC0
         0x02011757, // MBA1_MBSSYMEC1
         0x02011758, // MBA1_MBSSYMEC2
diff --git a/src/usr/diag/prdf/plat/mem/prdfMemIplCeStats.C b/src/usr/diag/prdf/plat/mem/prdfMemIplCeStats.C
index 12517c857..0ae5cec80 100755
--- a/src/usr/diag/prdf/plat/mem/prdfMemIplCeStats.C
+++ b/src/usr/diag/prdf/plat/mem/prdfMemIplCeStats.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2013,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -156,10 +156,6 @@ int32_t MemIplCeStats<T>::collectStats( const MemRank & i_stopRank )
 
     } while (0);
 
-    // We have to clear all stats before giving control back to MDIA..
-    // This is done by setting up MBSTRQ[53] bit
-    // We are doing cleanup in TdController code,
-    // So not clearing up stats here.
     return o_rc;
 
     #undef PRDF_FUNC
diff --git a/src/usr/diag/prdf/plat/mem/prdfMemScrubUtils.C b/src/usr/diag/prdf/plat/mem/prdfMemScrubUtils.C
index 3b6700922..38cbcc8bd 100644
--- a/src/usr/diag/prdf/plat/mem/prdfMemScrubUtils.C
+++ b/src/usr/diag/prdf/plat/mem/prdfMemScrubUtils.C
@@ -173,7 +173,7 @@ uint32_t clearEccCounters<TYPE_MBA>( ExtensibleChip * i_chip )
 
     ExtensibleChip * membChip = getConnectedParent( i_chip, TYPE_MEMBUF );
 
-    const char * reg = (0 == i_chip->getPos()) ? "MBA0_MBSTR" : "MBA1_MBSTR";
+    const char * reg = (0 == i_chip->getPos()) ? "MBSTR_0" : "MBSTR_1";
 
     return __clearEccCounters<TYPE_MEMBUF>( membChip, reg, 53 );
 }
@@ -239,8 +239,8 @@ uint32_t clearEccFirs<TYPE_MBA>( ExtensibleChip * i_chip )
     {
         ExtensibleChip * membChip = getConnectedParent( i_chip, TYPE_MEMBUF );
 
-        const char * reg = (0 == i_chip->getPos()) ? "MBA0_MBSECCFIR_AND"
-                                                   : "MBA1_MBSECCFIR_AND";
+        const char * reg = (0 == i_chip->getPos()) ? "MBSECCFIR_0_AND"
+                                                   : "MBSECCFIR_1_AND";
 
         // Clear MBSECCFIR[20:27,36:41]
         o_rc = __clearFir<TYPE_MEMBUF>( membChip, reg, 0xfffff00ff03fffffull );
@@ -337,8 +337,7 @@ uint32_t checkEccFirs<TYPE_MBA>( ExtensibleChip * i_chip,
 
     ExtensibleChip * membChip = getConnectedParent( i_chip, TYPE_MEMBUF );
 
-    const char * reg = (0 == i_chip->getPos()) ? "MBA0_MBSECCFIR"
-                                               : "MBA1_MBSECCFIR";
+    const char * reg = (0 == i_chip->getPos()) ? "MBSECCFIR_0" : "MBSECCFIR_1";
 
     SCAN_COMM_REGISTER_CLASS * mbseccfir = membChip->getRegister( reg );
     SCAN_COMM_REGISTER_CLASS * mbspa     = i_chip->getRegister( "MBASPA" );
@@ -490,8 +489,7 @@ uint32_t setBgScrubThresholds<TYPE_MBA>( ExtensibleChip * i_chip,
     do
     {
         ExtensibleChip * membChip = getConnectedParent( i_chip, TYPE_MEMBUF );
-        const char * reg_str = (0 == i_chip->getPos()) ? "MBA0_MBSTR"
-                                                       : "MBA1_MBSTR";
+        const char * reg_str = (0 == i_chip->getPos()) ? "MBSTR_0" : "MBSTR_1";
         SCAN_COMM_REGISTER_CLASS * mbstr = membChip->getRegister( reg_str );
         o_rc = mbstr->Read();
         if ( SUCCESS != o_rc )
diff --git a/src/usr/diag/prdf/plat/mem/prdfMemTdCtlr_rt.C b/src/usr/diag/prdf/plat/mem/prdfMemTdCtlr_rt.C
index d64335d37..af4acc15b 100644
--- a/src/usr/diag/prdf/plat/mem/prdfMemTdCtlr_rt.C
+++ b/src/usr/diag/prdf/plat/mem/prdfMemTdCtlr_rt.C
@@ -117,13 +117,13 @@ void __recaptureRegs<TYPE_MBA>( STEP_CODE_DATA_STRUCT & io_sc,
 
     const char * membRegs[2][15] =
     {
-        { "MBA0_MBSECCFIR", "MBA0_MBSECCERRPT_0","MBA0_MBSECCERRPT_1",
-          "MBA0_MBSEC0", "MBA0_MBSEC1", "MBA0_MBSTR",
+        { "MBSECCFIR_0", "MBA0_MBSECCERRPT_0","MBA0_MBSECCERRPT_1",
+          "MBA0_MBSEC0", "MBA0_MBSEC1", "MBSTR_0",
           "MBA0_MBSSYMEC0", "MBA0_MBSSYMEC1", "MBA0_MBSSYMEC2",
           "MBA0_MBSSYMEC3", "MBA0_MBSSYMEC4", "MBA0_MBSSYMEC5",
           "MBA0_MBSSYMEC6", "MBA0_MBSSYMEC7", "MBA0_MBSSYMEC8", },
-        { "MBA1_MBSECCFIR", "MBA1_MBSECCERRPT_0","MBA1_MBSECCERRPT_1",
-          "MBA1_MBSEC0", "MBA1_MBSEC1", "MBA1_MBSTR",
+        { "MBSECCFIR_1", "MBA1_MBSECCERRPT_0","MBA1_MBSECCERRPT_1",
+          "MBA1_MBSEC0", "MBA1_MBSEC1", "MBSTR_1",
           "MBA1_MBSSYMEC0", "MBA1_MBSSYMEC1", "MBA1_MBSSYMEC2",
           "MBA1_MBSSYMEC3", "MBA1_MBSSYMEC4", "MBA1_MBSSYMEC5",
           "MBA1_MBSSYMEC6", "MBA1_MBSSYMEC7", "MBA1_MBSSYMEC8", },
@@ -831,7 +831,7 @@ uint32_t MemTdCtlr<TYPE_MBA>::maskEccAttns()
         // mask them.
 
         const char * reg_str = (0 == iv_chip->getPos())
-            ? "MBA0_MBSECCFIR_MASK_OR" : "MBA1_MBSECCFIR_MASK_OR";
+            ? "MBSECCFIR_0_MASK_OR" : "MBSECCFIR_1_MASK_OR";
 
         ExtensibleChip * membChip = getConnectedParent( iv_chip, TYPE_MEMBUF );
 
@@ -874,9 +874,9 @@ uint32_t MemTdCtlr<TYPE_MBA>::unmaskEccAttns()
         // thresholded so clear and unmask them as well.
 
         const char * fir_str = (0 == iv_chip->getPos())
-            ? "MBA0_MBSECCFIR_AND" : "MBA1_MBSECCFIR_AND";
+            ? "MBSECCFIR_0_AND" : "MBSECCFIR_1_AND";
         const char * msk_str = (0 == iv_chip->getPos())
-            ? "MBA0_MBSECCFIR_MASK_AND" : "MBA1_MBSECCFIR_MASK_AND";
+            ? "MBSECCFIR_0_MASK_AND" : "MBSECCFIR_1_MASK_AND";
 
         ExtensibleChip * membChip = getConnectedParent( iv_chip, TYPE_MEMBUF );
 
diff --git a/src/usr/diag/prdf/plat/mem/prdfMemTps_ipl.C b/src/usr/diag/prdf/plat/mem/prdfMemTps_ipl.C
index 085381965..dcb4e703d 100644
--- a/src/usr/diag/prdf/plat/mem/prdfMemTps_ipl.C
+++ b/src/usr/diag/prdf/plat/mem/prdfMemTps_ipl.C
@@ -363,8 +363,7 @@ uint32_t TpsEvent<TYPE_MBA>::startCmd()
     do
     {
         ExtensibleChip * membChip = getConnectedParent( iv_chip, TYPE_MEMBUF );
-        const char * reg_str = (0 == iv_chip->getPos()) ? "MBA0_MBSTR"
-                                                        : "MBA1_MBSTR";
+        const char * reg_str = (0 == iv_chip->getPos()) ? "MBSTR_0" : "MBSTR_1";
         SCAN_COMM_REGISTER_CLASS * mbstr = membChip->getRegister( reg_str );
         o_rc = mbstr->Read();
         if ( SUCCESS != o_rc )
diff --git a/src/usr/diag/prdf/plat/mem/prdfMemTps_rt.C b/src/usr/diag/prdf/plat/mem/prdfMemTps_rt.C
index 5d5c65c4b..f3e13c6f8 100644
--- a/src/usr/diag/prdf/plat/mem/prdfMemTps_rt.C
+++ b/src/usr/diag/prdf/plat/mem/prdfMemTps_rt.C
@@ -1328,8 +1328,7 @@ uint32_t TpsEvent<TYPE_MBA>::startCmd()
     do
     {
         ExtensibleChip * membChip = getConnectedParent( iv_chip, TYPE_MEMBUF );
-        const char * reg_str = (0 == iv_chip->getPos()) ? "MBA0_MBSTR"
-                                                        : "MBA1_MBSTR";
+        const char * reg_str = (0 == iv_chip->getPos()) ? "MBSTR_0" : "MBSTR_1";
         SCAN_COMM_REGISTER_CLASS * mbstr = membChip->getRegister( reg_str );
         o_rc = mbstr->Read();
         if ( SUCCESS != o_rc )