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| author | Bill Hoffa <wghoffa@us.ibm.com> | 2018-04-19 15:35:17 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-04-25 09:34:17 -0400 |
| commit | 850cd71cc035699660db1f72273c0f6317f3a2db (patch) | |
| tree | a5838ce5bc122645a879c30e82634a958dfa507e | |
| parent | 97e097980a58296145b05914230f01d47b269e95 (diff) | |
| download | talos-hostboot-850cd71cc035699660db1f72273c0f6317f3a2db.tar.gz talos-hostboot-850cd71cc035699660db1f72273c0f6317f3a2db.zip | |
Modify Continuous Trace Address Calculation for Simulation
- In Multi-Node simulation the address calculated after
exiting cache-contained mode was negative which resulted
in errors in simulation
Change-Id: I84fa9e0b40be00d046bba5dbf766aa98ea50092f
CQ: SW425380
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57499
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
CI-Ready: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
CI-Ready: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
| -rw-r--r-- | src/build/debug/simics-debug-framework.py | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/build/debug/simics-debug-framework.py b/src/build/debug/simics-debug-framework.py index 93a84ad89..097210198 100644 --- a/src/build/debug/simics-debug-framework.py +++ b/src/build/debug/simics-debug-framework.py @@ -623,6 +623,10 @@ def magic_instruction_callback(user_arg, cpu, arg): chip_num = hb_hrmor//per_chip mem_object = None #print ">> hrmor=%X" % hb_hrmor + #print ">> hb_tracBinaryBuffer=%X" % hb_tracBinaryBuffer + #print ">> hb_tracBinaryBufferSz=%X" % hb_tracBinaryBufferSz + #print ">> node_num=%d" % node_num + #print ">> chip_num=%d" % chip_num # Find the entry in the memory map that includes our # base memory region. Can't assume object is "ram" @@ -649,14 +653,12 @@ def magic_instruction_callback(user_arg, cpu, arg): if ((smm_entry[0] == (node_num*per_node)) or (entry[0] == hb_hrmor)): mem_object = simics.SIM_object_name(smm_entry[1]) - base_addr = smm_entry[0] #print "Found entry %s for hrmor %x" % (mem_object, hb_hrmor) low_priority = priority #break break elif priority < low_priority: mem_object = simics.SIM_object_name(entry[1]) - base_addr = entry[0] #print "Found entry %s for hrmor %d" % (mem_object, hb_hrmor) low_priority = priority #break @@ -671,8 +673,7 @@ def magic_instruction_callback(user_arg, cpu, arg): if 'cache' not in mem_object: hb_tracBinaryBuffer = (hb_tracBinaryBuffer + hb_hrmor - - per_node*node_num - - base_addr) + (per_node*node_num)) tracbin = ["hbTracBINARY","hbTracBINARY1","hbTracBINARY2","hbTracBINARY3"] tracmerg = ["hbTracMERG","hbTracMERG1","hbTracMERG2","hbTracMERG3"] |
