Add support for ATTR_MSS_VPD_MT_WINDAGE_RD_CTR

  Update ps_to_cycles conversion for negative numbers
  Update fake_vpd to have correct value for windgage

Change-Id: Idbb2a3b661ae06d7643f5d838a2a65b2d12248ba
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30732
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30748
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

5 files changed, 110 insertions, 10 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
index 8c2a338e8..9b468e1ce 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
@@ -650,6 +650,9 @@ fapi2::ReturnCode phy_scominit(const fapi2::Target<TARGET_TYPE_MCBIST>& i_target
         // Resets all WR VREF related registers
         FAPI_TRY( mss::dp16::reset_wr_vref_registers(p));
 
+        // Reset the windage registers
+        FAPI_TRY( mss::dp16::reset_read_delay_offset_registers(p) );
+
         //
         // Workarounds
         //
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
index 02c90dd7f..ddf1e0a03 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
@@ -339,6 +339,7 @@ const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::
     { MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3 },
     { MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4 },
 };
+
 // Definition of the VREF value registers for RP3 element is DP16 number, first is value 0 second is value 1
 const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_VALUE_RP3_REG =
 {
@@ -349,6 +350,51 @@ const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::
     { MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4 },
 };
 
+// Definition of the windage value registers per MCA. These are per rank pair, per DP16 and there are 2.
+const std::vector<uint64_t> dp16Traits<TARGET_TYPE_MCA>::READ_DELAY_OFFSET_REG =
+{
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3,
+    MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4,
+};
+
 ///
 /// @brief Given a RD_VREF value, create a PHY 'standard' bit field for that percentage.
 /// @tparam T fapi2 Target Type - derived
@@ -1645,5 +1691,35 @@ fapi_try_exit:
     return fapi2::current_err;
 }
 
+///
+/// @brief Resets all read delay offset registers
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template<>
+fapi2::ReturnCode reset_read_delay_offset_registers( const fapi2::Target<TARGET_TYPE_MCA>& i_target )
+{
+    typedef dp16Traits<TARGET_TYPE_MCA> TT;
+
+    // We grab the information from the VPD and blast it in to all the registers. Note the
+    // VPD is picoseconds but the register wants clocks - so we convert. Likewise, the VPD
+    // is per port so we can easily cram the data in to the port using the blastah.
+    fapi2::buffer<uint64_t> l_data;
+    int64_t l_clocks = 0;
+    int16_t l_windage = 0;
+
+    FAPI_TRY( mss::vpd_mt_windage_rd_ctr(i_target, l_windage) );
+    l_clocks = mss::ps_to_cycles(i_target, l_windage);
+
+    l_data
+    .insertFromRight<TT::READ_OFFSET_LOWER, TT::READ_OFFSET_LOWER_LEN>(l_clocks)
+    .insertFromRight<TT::READ_OFFSET_UPPER, TT::READ_OFFSET_UPPER_LEN>(l_clocks);
+
+    FAPI_TRY( mss::scom_blastah(i_target, TT::READ_DELAY_OFFSET_REG, l_data) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
 } // close namespace dp16
 } // close namespace mss
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
index 7485232bc..bbd2e1f73 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
@@ -156,6 +156,7 @@ class dp16Traits<fapi2::TARGET_TYPE_MCA>
         static const std::vector< uint64_t > PR_STATIC_OFFSET_REG;
         static const std::vector< uint64_t > IO_TX_FET_SLICE_REG;
         static const std::vector< uint64_t > IO_TX_PFET_TERM_REG;
+        static const std::vector< uint64_t > READ_DELAY_OFFSET_REG;
 
         //WR VREF registers
         static const std::vector< uint64_t > WR_VREF_CONFIG0_REG;
@@ -291,6 +292,12 @@ class dp16Traits<fapi2::TARGET_TYPE_MCA>
             WR_VREF_VALUE_RANGE_DRAM_ODD      = MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_RANGE_DRAM1 ,
             WR_VREF_VALUE_VALUE_DRAM_ODD      = MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM1 ,
             WR_VREF_VALUE_VALUE_DRAM_ODD_LEN  = MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM1_LEN ,
+
+            // Read Delay fields.
+            READ_OFFSET_LOWER = MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01,
+            READ_OFFSET_LOWER_LEN = MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_LEN,
+            READ_OFFSET_UPPER = MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_OFFSET1,
+            READ_OFFSET_UPPER_LEN = MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_OFFSET1_LEN,
         };
 };
 
@@ -1666,6 +1673,17 @@ fapi2::ReturnCode reset_wr_vref_value_rp3( const fapi2::Target<T>& i_target );
 template< fapi2::TargetType T, typename TT = dp16Traits<T> >
 fapi2::ReturnCode reset_wr_vref_registers( const fapi2::Target<T>& i_target );
 
+///
+/// @brief Resets all read delay offset registers
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+// TODO RTC:162136 implement read, write, set and get for the read delay offset registers
+template< fapi2::TargetType T, typename TT = dp16Traits<T> >
+fapi2::ReturnCode reset_read_delay_offset_registers( const fapi2::Target<T>& i_target );
+
 } // close namespace dp16
 } // close namespace mss
 
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/conversions.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/conversions.H
index c7a3589b7..9de5b3e8c 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/conversions.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/conversions.H
@@ -171,18 +171,21 @@ inline uint64_t cycles_to_simcycles( const uint64_t i_cycles )
 
 ///
 /// @brief Return the number of cycles contained in a count of picoseconds
+/// @tparam T the target type from which to get the mt/s
+/// @tparam OT the output type, derrived from the parameters
 /// @param[in] i_target target for the frequency attribute
 /// @param[in] i_ps the number of picoseconds to convert
 /// @return uint64_t, the number of cycles
 ///
-template< fapi2::TargetType T >
-inline uint64_t ps_to_cycles(const fapi2::Target<T>& i_target, const uint64_t i_ps)
+template< fapi2::TargetType T, typename OT >
+inline OT ps_to_cycles(const fapi2::Target<T>& i_target, const OT i_ps)
 {
-    // The frequency in mHZ
+    // The frequency in MT/s
     uint64_t l_freq = 0;
-    uint64_t l_divisor = 0;
-    uint64_t l_quotient = 0;
-    uint64_t l_remainder = 0;
+    OT l_divisor = 0;
+    OT l_quotient = 0;
+    OT l_remainder = 0;
+    OT l_rounder = (i_ps < 0) ? -1 : 1;
 
     FAPI_TRY( mss::freq( find_target<fapi2::TARGET_TYPE_MCBIST>(i_target), l_freq) );
 
@@ -194,13 +197,13 @@ inline uint64_t ps_to_cycles(const fapi2::Target<T>& i_target, const uint64_t i_
 
     // Hoping the compiler figures out how to do these together.
     FAPI_TRY( freq_to_ps(l_freq, l_divisor) );
-    l_quotient = i_ps / ((l_divisor == 0) ? 1 : l_divisor);
+    l_quotient = i_ps / ((l_divisor == 0) ? l_rounder : l_divisor);
     l_remainder = i_ps % l_divisor;
 
     // Make sure we add a cycle if there wasn't an even number of cycles in the input
-    FAPI_INF("converting %llups to %llu cycles", i_ps, l_quotient + (l_remainder == 0 ? 0 : 1));
+    FAPI_INF("converting %dps to %d cycles", i_ps, l_quotient + (l_remainder == 0 ? 0 : l_rounder));
 
-    return l_quotient + (l_remainder == 0 ? 0 : 1);
+    return l_quotient + (l_remainder == 0 ? 0 : l_rounder);
 
 fapi_try_exit:
     // We simply can't work if we can't get the frequency or
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C
index 3c1c24732..76bb24014 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C
@@ -59,7 +59,7 @@ static constexpr uint8_t raw_mt[raw_mt_size] =
     0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
     0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0x16, 0x00, 0x01,
-    0x31, 0xfd, 0x00, 0x01, 0x31, 0xfd, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x31, 0xfd, 0x00, 0x01, 0x31, 0xfd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 };