mss_get_ecid code for 11/15 SOA chkpt

Change-Id: I6f09310ed5a162b047ea0dabf383ef0a4f5e8cca Original-Change-Id: I1c61f1f20fcdd16d014d13833f3a8eef92559175 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32617 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Johannes Koesters <koesters@de.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44102 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
author: Luke Mulkey <lwmulkey@us.ibm.com> 2016-11-14 16:33:46 -0600
committer: Daniel M. Crowell <dcrowell@us.ibm.com> 2017-08-04 09:10:53 -0400
commit: c999985603ebc509c3c64210c5332635e85e98af (patch)
tree: e475130fc1d642070e6b5b32d2365ca6047ad19d
parent: 7302a891f6709ebdd7f5a65d29417f6b372e6e69 (diff)
download: talos-hostboot-c999985603ebc509c3c64210c5332635e85e98af.tar.gz
talos-hostboot-c999985603ebc509c3c64210c5332635e85e98af.zip
1 files changed, 3568 insertions, 0 deletions
diff --git a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml
new file mode 100644
index 000000000..0152db194
--- /dev/null
+++ b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml
@@ -0,0 +1,3568 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER HostBoot Project                                             -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2012,2017                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<attributes>
+<!-- $Id: memory_attributes.xml,v 1.173 2016/08/04 14:06:38 pardeik Exp $ -->
+<!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB -->
+<!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP -->
+<!-- *********************************************************************** --> 
+<attribute>
+    <id>ATTR_CEN_ZMODE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>
+        Set to activate System Z mode, used to mask opposite port on Mcbist and Schmoos.
+    </description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+</attribute>
+<attribute>
+    <id>ATTR_CEN_ZMODE_PORT</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>
+          Used to set the port under test for System Z.  Opposite port will be masked from MCBIST/Schmoo
+    </description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_ADDRESS_MIRRORING</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>
+        Ranks that have address mirroring.
+        This data is derived from SPD and C-DIMM VPD.
+        Bit wise map bit4=RANK0_MIRRORED, bit5=RANK1_MIRRORED, bit6=RANK2_MIRRORED, bit7=RANK3_MIRRORED
+    Note: Muliple ranks can be mirrored.
+    </description>
+    <valueType>uint8</valueType>
+    <array> 2 2</array>
+    <writeable/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VOLT</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>DRAM Voltage, each voltage rail would need to have a value.  Computed in mss_volt C code - in millivolts
+creator: mss_volt
+consumer: mss_eff_cnfg, others
+firmware notes: none</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VOLT_VPP</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>DRAM VPP Voltage, each voltage rail would need to have a value.  Computed in mss_volt C code - in millivolts.  0V - DDR3, 2.5V - DDR4
+creator: mss_volt
+consumer: mss_eff_cnfg, others
+firmware notes: none</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_FREQ_OVERRIDE</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>FOR LAB USE ONLY: Frequency override of this memory channel in MHz, comprising of up to three DIMMs.  Set by config file or an attribute writing program.  Consumed by mss_freq.  The default of AUTO means mss_freq will find the best frequencies given the DIMMs plugged in and other rules.  Otherwise, this is the system frequency.
+firmware notes: Platforms should initialize this attribute to AUTO (0)</description>
+    <valueType>uint32</valueType>
+    <enum>AUTO = 0</enum>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_FREQ</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Frequency of this memory channel in MHz, comprising of three DIMMs.  Computed in mss_freq
+creator: mss_freq
+consumer: mss_eff_cnfg, others
+firmware notes: none</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_FREQ_BIAS_PERCENTAGE</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Percentage to increase/decrease MEM frequency - two's complement number.  Measured in 100's.  So the value of 100 is one percent increase.
+This frequency change comes from changing multipliers and dividers to  get the desired frequency.  The supported frequencies come from Tim Diemoz.
+Creator: platform set this to 0.  Users can set this to a valid value.
+VALID Values: (TBD % to TBD %) (Tuleta) (TBD % to TBD %) (Glacier)
+Set by: PLL settings written by Dave Cadigan</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+<id>ATTR_CEN_MSS_VREF_CAL_CNTL</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Training Control over IPL - ENUM - 0x00=DISABLE /Skip V-ref Train; 0x01=DRAM - Enable V-Ref Train DRAM Level; 0x02=RANK Level Training; 0x03=PORT Level Training; 0x04=MBA Level; 0x05=CENTAUR level;
+	Default Value = 0x03 for OpenPower platforms
+                      = 0x01 for others (TULETA, BRAZOS, ALPINE).
+</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+	
+<attribute>
+    <id>ATTR_CEN_MSS_DIMM_MFG_ID_CODE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Manufacturer ID Code RCD: bits(31:16), Module: bits(15:0)</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_RANKS_CONFIGED</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Bit wise representation of master ranks in each DIMM that are used for reads and writes. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+Dimensions are [port][dimm]  A/B=Mba_0 C/D=Mba_1 There are only two DIMM ranks: DIMM0 and DIMM1 where DIMM0 is the furthest from the centaur.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_NUM_RANKS_PER_DIMM</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Number of ranks in each DIMM. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+values are 0,1,2, 4 up to 32
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_TYPE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Type of DIMM: RDIMM, UDIMM, LRDIMM as specified by the JEDIC standard. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none
+NOTE: Do not use the enum type of CDIMM.  Use the attribute EFF_DIMM_CUSTOM to test for a CUSTOM DIMM or CDIMM.</description>
+    <valueType>uint8</valueType>
+    <enum>CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CUSTOM_DIMM</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DIMM is a custom DIMM. This is commonly known as a CDIMM, but technically, we could support Custom DIMMs of different types than an UDIMM, such as RDIMM and LRDIMM.  Created in mss_eff_cnfg
+Use this attribute if you need to know if the Centaur is on the DIMM instead of on a planar.</description>
+    <valueType>uint8</valueType>
+    <enum>NO = 0, YES = 1</enum>
+    <platActionWrite/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_WIDTH</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DRAM Device Width: X4, X8, X16, X32. Used in various locations and is computed in mss_eff_cnfg.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>X4 = 4, X8 = 8, X16 = 16, X32 = 32</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_GEN</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Generation of memory: DDR3, DDR4. Used in various locations and is computed in mss_eff_cnfg.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>EMPTY = 0, DDR3 = 1, DDR4 = 2</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_PRIMARY_RANK_GROUP0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_rank_group
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>INVALID = 255</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_PRIMARY_RANK_GROUP1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_rank_group
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>INVALID = 255</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_PRIMARY_RANK_GROUP2</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_rank_group
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>INVALID = 255</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_PRIMARY_RANK_GROUP3</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_rank_group
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>INVALID = 255</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_SECONDARY_RANK_GROUP0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_rank_group
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>INVALID = 255</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_SECONDARY_RANK_GROUP1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_rank_group
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>INVALID = 255</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_SECONDARY_RANK_GROUP2</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_rank_group
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>INVALID = 255</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_SECONDARY_RANK_GROUP3</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_rank_group
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>INVALID = 255</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_TERTIARY_RANK_GROUP0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_rank_group
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>INVALID = 255</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_TERTIARY_RANK_GROUP1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_rank_group
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>INVALID = 255</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_TERTIARY_RANK_GROUP2</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_rank_group
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>INVALID = 255</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_TERTIARY_RANK_GROUP3</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_rank_group
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>INVALID = 255</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_QUATERNARY_RANK_GROUP0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_rank_group
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>INVALID = 255</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_QUATERNARY_RANK_GROUP1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_rank_group
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>INVALID = 255</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_QUATERNARY_RANK_GROUP2</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_rank_group
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>INVALID = 255</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_QUATERNARY_RANK_GROUP3</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_rank_group
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>INVALID = 255</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_SPARE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Spare DRAM availability. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.   creator: mss_eff_cnfg consumer: various firmware notes: load from spd
+OBSOLETE: Use ATTR_CEN_VPD_DIMM_SPARE
+</description>
+    <valueType>uint8</valueType>
+    <enum>NO_SPARE = 0, LOW_NIBBLE = 1, HIGH_NIBBLE = 2, FULL_BYTE = 3</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2 4</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_WR_VREF</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DRAM Write Vref. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: VPD(MT) or mss_eff_cnfg_termination
+consumer: various.C and initfile
+firmware notes: none
+This is the nominal value
+This is for DDR3</description>
+    <valueType>uint32</valueType>
+    <enum>VDD420 = 420, VDD425 = 425, VDD430 = 430, VDD435 = 435, VDD440 = 440, VDD445 = 445, VDD450 = 450, VDD455 = 455, VDD460 = 460, VDD465 = 465, VDD470 = 470, VDD475 = 475, VDD480 = 480, VDD485 = 485, VDD490 = 490, VDD495 = 495, VDD500 = 500, VDD505 = 505, VDD510 = 510, VDD515 = 515, VDD520 = 520, VDD525 = 525, VDD530 = 530, VDD535 = 535, VDD540 = 540, VDD545 = 545, VDD550 = 550, VDD555 = 555, VDD560 = 560, VDD565 = 565, VDD570 = 570, VDD575 = 575</enum>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_WR_VREF_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Enables for which VREF to use on the WR Schmoo.  The LSB corresponds to the highest WR Vref</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_WRDDR4_VREF_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Enables for which VREF to use on the WR Schmoo.  The LSB corresponds to the highest WR Vref</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CEN_DRV_IMP_DQ_DQS</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Centaur DQ and DQS Drive Impedance Used in various locations and comes from the MT Keyword of the VPD or  is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: VPD(MT)/mss_eff_cnfg_termination
+consumer: initfile,various.C files
+firmware notes: none
+This is the nominal value</description>
+    <valueType>uint8</valueType>
+    <enum>OHM24_FFE0 = 0x0A, OHM30_FFE0 = 0x08,
+OHM30_FFE480 = 0x48, OHM30_FFE240 = 0x38, OHM30_FFE160 = 0x28, OHM30_FFE120 = 0x18, OHM34_FFE0 = 0x07, OHM34_FFE480 = 0x47, OHM34_FFE240 = 0x37, OHM34_FFE160 = 0x27, OHM34_FFE120 = 0x17, OHM40_FFE0 = 0x06, OHM40_FFE480 = 0x46, OHM40_FFE240 = 0x36, OHM40_FFE160 = 0x26, OHM40_FFE120 = 0x16</enum>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Enables for which impedance values can be used and tested in a timing test.  The bits have a one to one correspondence to the possible driver strengths and start with the first value down to the last (largest) impedance as the LSB of the 8 bit field.</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CEN_DRV_IMP_CLK_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Enables for which impedance values can be used and tested in a timing test.  The bits have a one to one correspondence to the possible driver strengths and start with the first value down to the last (largest) impedance as the LSB of the 8 bit field.</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CEN_DRV_IMP_SPCKE_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Enables for which impedance values can be used and tested in a timing test.  The bits have a one to one correspondence to the possible driver strengths and start with the first value down to the last (largest) impedance as the LSB of the 8 bit field.</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CEN_DRV_IMP_CNTL_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Enables for which impedance values can be used and tested in a timing test.  The bits have a one to one correspondence to the possible driver strengths and start with the first value down to the last (largest) impedance as the LSB of the 8 bit field.
+This is the nominal value</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CEN_RCV_IMP_DQ_DQS</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Centaur DQ and DQS Receiver Impedance Used in various locations and it comes from the VPD MT keyword for custom DIMMs or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: VPD, mss_eff_cnfg_termination
+Consumer: initfile + C code
+firmware notes: none
+This is the nominal value</description>
+    <valueType>uint8</valueType>
+    <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40, OHM48 = 48, OHM60 = 60,  OHM80 = 80, OHM120 = 120, OHM160 = 160, OHM240 = 240</enum>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Enables for which impedance values can be used and tested in a timing test.  The bits have a one to one correspondence to the possible receiver termination and start with the first value down to the last (largest) impedance as the LSB of the 32 bit field.</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CEN_SLEW_RATE_DQ_DQS</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Centaur DQ and DQS Slew Rate Used in various locations and comes from the MT keyword of the VPD or  is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: VPD(MT), mss_eff_cnfg_termination
+consumer: initfiles,various.C
+firmware notes: none
+This is the nominal value</description>
+    <valueType>uint8</valueType>
+    <enum>SLEW_3V_NS = 3,
+SLEW_4V_NS = 4,
+SLEW_5V_NS = 5,
+SLEW_6V_NS = 6,
+SLEW_MAXV_NS = 7</enum>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Slew Rates that can be selected during timing adjustments.  The fastest rate is the LSB</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CEN_SLEW_RATE_CLK_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Slew Rates that can be selected during timing adjustments.  The fastest rate is the LSB</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CEN_SLEW_RATE_SPCKE_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Slew Rates that can be selected during timing adjustments.  The fastest rate is the LSB</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CEN_SLEW_RATE_ADDR_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Slew Rates that can be selected during timing adjustments.  The fastest rate is the LSB</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CEN_SLEW_RATE_CNTL_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Slew Rates that can be selected during timing adjustments.  The fastest rate is the LSB</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CEN_RD_VREF</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Centaur Read Vref. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+Creator: VPD(MT) or mss_eff_cnfg_termination
+consumer: various.C and initfiles
+firmware notes: none
+This is the nominal value</description>
+    <valueType>uint32</valueType>
+    <enum>VDD40375 = 40375, VDD41750 = 41750, VDD43125 = 43125, VDD44500 = 44500, VDD45875 = 45875, VDD47250 = 47250, VDD48625 = 48625, VDD50000 = 50000, VDD51375 = 51375, VDD52750 = 52750, VDD54125 = 54125, VDD55500 = 55500, VDD56875 = 56875, VDD58250 = 58250, VDD59625 = 59625, VDD61000 = 61000, VDD60375 = 60375, VDD61750 = 61750, VDD63125 = 63125, VDD64500 = 64500, VDD65875 = 65875, VDD67250 = 67250, VDD68625 = 68625, VDD70000 = 70000, VDD71375 = 71375, VDD72750 = 72750, VDD74125 = 74125, VDD75500 = 75500, VDD76875 = 76875, VDD78250 = 78250, VDD79625 = 79625, VDD81000 = 81000</enum>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CEN_RD_VREF_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Enables for which VREF value can be used in timing adjustments.  The highest voltage corresponds to the LSB</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_SIZE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DIMM Size.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_BANKS</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Number of DRAM banks.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_ROWS</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Number of DRAM rows.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_COLS</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Number of DRAM columns.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_DENSITY</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DRAM Density.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_TRCD</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RAS to CAS Delay.  Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg_timing
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_TRRD</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Row ACT to Row ACT Delay.  Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg_timing
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_TRRD_L</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DDR4 - Row to Row:Long timings tRRD_L : bank accesses within the same bank group
+creator: mss_eff_cnfg_timing
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_TRP</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Row Precharge Delay.  Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg_timing
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_TRAS</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>ACT to Precharge Delay.  Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg_timing
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_TRC</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>ACT to ACT/Refresh Delay.  Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg_timing
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_TRFI</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Refresh Interval. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  In unit clock.
+creator: mss_eff_cnfg_timing
+consumer: various
+firmware notes: none</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_TRFC</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Refresh Recovery Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  In unit clock.
+creator: mss_eff_cnfg_timing
+consumer: various
+firmware notes: none</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_TWTR</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Internal Write to Read Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg_timing
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_TWTR_L</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DDR4 - Long timings (tCCD_L, tRRD_L, and tWTR_L): bank accesses within the same bank group
+creator: mss_eff_cnfg_timing
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_TRTP</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Internal Read to Precharge Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg_timing
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_TFAW</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Four ACT Window Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg_timing
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_BL</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Burst Length.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>BL8 = 0, OTF = 1, BC4 = 2</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_CL</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>CAS Latency.  Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg_timing
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_AL</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Additive Latency.  Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg_timing
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, CL_MINUS_1 = 1, CL_MINUS_2 = 2, CL_MINUS_3 = 3</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_CWL</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>CAS Write Latency.  Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg_timing
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_RBT</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Read Burst Type.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>SEQUENTIAL = 0, INTERLEAVE = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_TM</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Test Mode.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>NORMAL= 0, TEST = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_DLL_RESET</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DLL Reset.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>NO = 0, YES = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_WR</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Write Recovery.  Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg_timing
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_DLL_PPD</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DLL Precharge PD.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>SLOWEXIT = 0, FASTEXIT = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_DLL_ENABLE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DLL Enable.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>ENABLE = 0, DISABLE = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_TDQS</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>TDQS. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, ENABLE = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_WR_LVL_ENABLE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Write Level Enable. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, ENABLE = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_OUTPUT_BUFFER</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DRAM Qoff. Enables or disables DRAM output. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>ENABLE = 0, DISABLE = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_PASR</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Partial Array Self-Refresh. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>FULL = 0, FIRST_HALF = 1, FIRST_QUARTER = 2, FIRST_EIGHTH = 3, LAST_THREE_FOURTH = 4, LAST_HALF = 5, LAST_QUARTER = 6, LAST_EIGHTH = 7</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_ASR</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Auto Self-Refresh. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>SRT = 0, ASR = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_SRT</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Self-Refresh Temperature Range. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>NORMAL = 0, EXTEND = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_MPR_LOC</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Multi Purpose Register Location. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_MPR_MODE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Multi Purpose Register Mode. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, ENABLE = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_RCD_CNTL_WORD_0_15</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RCD Control Word. Used in mss_dram_init and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint64</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_RCD_CNTL_WORD_X</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Additional RCD Control Word for DDR4. Used in mss_dram_init and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint64</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC00</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC00: Global Features Control Word.For normal operation, output inversion is always enabled. For DIMM vendor test purpose, output inversion can be disabled. 
+When disabled, register tPDM is not guaranteed to be met. NOTE: creator: mss_eff_cnfg will set Default value - 0x00. Values Range from 0-8.
+00 - Normal Operation; 01 - Output Inversion Disabled; 02 - Weak Drive Enabled; 04 - A outputs disabled; 08 - B outputs disabled; So on.
+No need to calculate; User can override with desired experimental value.
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC01</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC01 - Clock Driver Enable Control Word.1. Output clocks may be individually turned on or off to conserve power. The system must read the module SPD to determine which clock outputs are used by the module. The PLL remains locked on CK_t/CK_c unless the system stops the clock inputs to the DDR4RCD02 to enter the lowest power mode.
+	creator: mss_eff_cnfg will set Default value - 0x00. Values Range from 0-8. No need to calculate; User can override with desired experimental value.
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC02</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC02: Timing and IBT Control Word; mss_eff_cnfg will set Default value - 0x00. Values Range from 0-8. No need to calculate; User can override with desired experimental value.
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC03</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC03 - CA and CS Signals Driver Characteristics Control Word;  mss_eff_cnfg will set Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 1st Nibble for CS and CA.
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC04</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; mss_eff_cnfg will set Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 2nd Nibble for ODT and CKE.
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC05</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC05 - Clock Driver Characteristics Control Word; mss_eff_cnfg will set Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble for CK.
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC06_07</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC06: Command Space Control Word definition; mss_eff_cnfg will set Default value - 0xF0 (NOP). Values Range from 00 to F0. F0RC07 not used. RDIMM
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC08</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC08: Input/Output Configuration Control Word; mss_eff_cnfg will set Default value - 0x03. Values Range from 00 to 08 decimal. Check the stack height and calculate dynamically; 00 = Stack height_8; 01 = Stack height_4;
+        02 = Stack height_2;
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC09</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC06: Command Space Control Word definition;mss_eff_cnfg will set  Default value - 0xF0 (NOP). Values Range from 00 to F0. No need to calculate; User can override with desired experimental value.
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC10</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RDIMM Operating Speed;  Read from ATTR_CEN_MSS_FREQ; mss_eff_cnfg will set Default value - 00. Values Range from 00 to 09. No need to calculate; User can override with desired experimental value.
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC11</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_CEN_MSS_VOLT.mss_eff_cnfg will set Default value - 14. Values Range from 00 to 15 decimal.  No need to calculate; User can override with desired experimental value.
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC12</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC0C - Training Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to 07 decimal.No need to calculate; User can override with desired experimental value. 
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC13</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC0D - DIMM Configuration Control Word; mss_eff_cnfg will set Default value - 0B. Values Range from 00 to 15 decimal. Dynamically calculated using 4 bits[0:3] Bit 0 - Address Mirroring; Bit 1 - Rdimm(1)/Lrdimm (0) ; Bit 2 - N/A ; Bit 3 - CS Mode (Direct / Quad CS mode etc); 
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC14</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC0E - Parity Control Word; mss_eff_cnfg will set Default value - 00. Check from ATTR_CEN_EFF_CA_PARITY and assign; Values Range from 00 to 0F. 
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC15</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC0F - Command Latency Adder Control Word; mss_eff_cnfg will set  Default value - 04. Values Range from 00 to 04. No need to calculate; User can override with desired experimental value.
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC_1x</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC1x - Internal VrefCA Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to 3F.No need to calculate; User can override with desired experimental value. 
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC_2x</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC2x: I2C Bus Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. 
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC_3x</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC3x - Fine Granularity RDIMM Operating Speed; mss_eff_cnfg will set Default value = (Operating Freq - 1250)/20. Values Range from 00 to 61 Hex. 
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC_4x</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC4x: CW Source Selection Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value.
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC_5x</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC5x: CW Destination Selection and Write/Read Additional QxODT[1:0] Signal High; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value.
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC_6x</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC6x: CW Data Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. 
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC_7x</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC7x: IBT Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value.
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC_8x</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC8x: ODT Input Buffer/IBT, QxODT Output Buffer and Timing Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value.
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC_9x</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RC9x1: QxODT[1:0] Write Pattern Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. 
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC_Ax</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RCAx1: QxODT[1:0] Read Pattern Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. 
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_DDR4_RC_Bx</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>F0RCBx: IBT and MRS Snoop Control Word; mss_eff_cnfg will set Default value - 07. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. 
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+	<writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_RCD_IBT</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RCD IBT. Used in mss_dram_init and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint32</valueType>
+    <enum>IBT_OFF = 0, IBT_100 = 100, IBT_150 = 150, IBT_200 = 200, IBT_300 = 300</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DIMM_RCD_MIRROR_MODE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RCD IBT. Used in mss_dram_init and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: mss_dram_init
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>IBT_BACK_OFF = 0, IBT_BACK_ON = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_SCHMOO_MODE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Specifies the schmoo mode to use during draminit_train_adv.</description>
+    <valueType>uint8</valueType>
+    <enum>FAST = 0, ONE_SLOW = 1, QUARTER_SLOW = 2, HALF_SLOW = 3, FULL_SLOW = 4, ONE_CHAR = 5, QUARTER_CHAR = 6, HALF_CHAR = 7, FULL_CHAR = 8</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_SCHMOO_ADDR_MODE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Specifies the schmoo mode to use during draminit_train_adv</description>
+    <valueType>uint8</valueType>
+    <enum>FEW_ADDR= 0, QUARTER_ADDR = 1, HALF_ADDR = 2, FULL_ADDR = 3</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_SCHMOO_TEST_VALID</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Specifies the schmoo test to run during draminit_train_adv. Bit wise.</description>
+    <valueType>uint8</valueType>
+    <enum> NONE = 0x00,
+ MCBIST = 0x01,
+ WR_EYE = 0x02,
+ RD_EYE = 0x04,
+ WR_DQS = 0x08,
+ RD_DQS = 0x10</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_SCHMOO_PARAM_VALID</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Specifies the schmoo parameters to use during draminit_train_adv. Bit wise.</description>
+    <valueType>uint8</valueType>
+    <enum> PARAM_NONE = 0x00,
+ DELAY_REG = 0x01,
+ DRV_IMP = 0x02,
+ SLEW_RATE = 0x04,
+ WR_VREF = 0x08,
+ RD_VREF = 0x10,
+ RCV_IMP = 0x20</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_SCHMOO_WR_EYE_MIN_MARGIN</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_SCHMOO_RD_EYE_MIN_MARGIN</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_SCHMOO_DQS_CLK_MIN_MARGIN</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_SCHMOO_RD_GATE_MIN_MARGIN</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_SCHMOO_ADDR_CMD_MIN_MARGIN</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_MEMCAL_INTERVAL</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Specifies the memcal interval in clocks.</description>
+    <valueType>uint32</valueType>
+    <enum>DISABLE = 0</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_ZQCAL_INTERVAL</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Specifies the zqcal interval in clocks.</description>
+    <valueType>uint32</valueType>
+    <enum>DISABLE = 0</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_IBM_TYPE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Specifies the memory topology type. See centaur workbook.</description>
+    <valueType>uint8</valueType>
+    <enum>UNDEFINED = 0, TYPE_1A = 1, TYPE_1B = 2, TYPE_1C = 3, TYPE_1D = 4, TYPE_2A = 5, TYPE_2B = 6, TYPE_2C = 7, TYPE_3A = 8, TYPE_3B = 9, TYPE_3C = 10, TYPE_4A = 11, TYPE_4B = 12, TYPE_4C = 13, TYPE_5A = 14, TYPE_5B = 15, TYPE_5C = 16, TYPE_5D = 17, TYPE_6A = 18, TYPE_6B = 19, TYPE_6C = 20, TYPE_7A = 21, TYPE_7B = 22, TYPE_7C = 23, TYPE_8A = 24, TYPE_8B = 25, TYPE_8C = 26</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_NUM_DROPS_PER_PORT</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Specifies the number of DIMM dimensions that are valid per port. </description>
+    <valueType>uint8</valueType>
+    <enum>EMPTY = 0, SINGLE = 1, DUAL = 2</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_STACK_TYPE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Specifies the DRAM package type.</description>
+    <valueType>uint8</valueType>
+    <enum>NONE = 0, DDP_QDP = 1, STACK_3DS = 2</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_NUM_MASTER_RANKS_PER_DIMM</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Specifies the number of master ranks per DIMM.</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_NUM_PACKAGES_PER_RANK</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Specifies the number of DRAM packages per rank.</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_NUM_DIES_PER_PACKAGE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Specifies the number of DRAM dies per package.</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>This is the throttle numerator setting for cfg_nm_n_per_mba creator: mss_eff_cnfg consumer: mc_config firmware notes: none</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_MEM_THROTTLE_DENOMINATOR</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>This is the throttle denominator setting for cfg_nm_m creator: mss_eff_cnfg consumer: mc_config  firmware notes: none</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>This is the throttle numerator setting for cfg_nm_n_per_chip creator: mss_eff_cnfg consumer: mc_config firmware notes: none</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_MEM_WATT_TARGET</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Total memory power limit in cW for the dimms on the memory channel pair. Used to compute the throttles on the channel and/or dimms creator: unknown consumer: mss_eff_config firmware notes: none</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_POWER_SLOPE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Master Power slope value for dimm</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_POWER_SLOPE2</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Supplier Power slope value for dimm</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_POWER_INT</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Master Power intercept value for dimm</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_POWER_INT2</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Supplier Power intercept value for dimm</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_TOTAL_POWER_SLOPE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Master Total Power slope value for dimm</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_TOTAL_POWER_SLOPE2</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Supplier Total Power slope value for dimm</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_TOTAL_POWER_INT</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Master Total Power intercept value for dimm</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_TOTAL_POWER_INT2</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Supplier Total Power intercept value for dimm</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_DIMM_MAXBANDWIDTH_GBS</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DIMM Max Bandwidth in GBs output from thermal procedures</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_DIMM_MAXBANDWIDTH_MRS</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DIMM Max Bandwidth in MRs output from thermal procedures</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_CHANNEL_PAIR_MAXBANDWIDTH_GBS</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Channel Pair Max Bandwidth in GBs output from thermal procedures</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_CHANNEL_PAIR_MAXBANDWIDTH_MRS</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Channel Pair Max Bandwidth MRs output from thermal procedures</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_DIMM_MAXPOWER</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DIMM Max Power output from thermal procedures</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_CHANNEL_PAIR_MAXPOWER</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Channel Pair Max Power output from thermal procedures</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Runtime throttle numerator setting for cfg_nm_n_per_mba</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Runtime throttle denominator setting for cfg_nm_m</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Runtime throttle numerator setting for cfg_nm_n_per_chip</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook safe mode throttle value for numerator cfg_nm_n_per_mba</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook safe mode throttle value for numerator cfg_nm_n_per_chip</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MRW_THERMAL_MEMORY_POWER_LIMIT</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook Thermal Memory Power Limit</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_INTERLEAVE_ENABLE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>Used in the setting of groups.  It is a bit vector.  If the value  BITWISE_AND  1 = 1 then groups of 1 are enabled with special checkerboard modes needed, if the value  BITWISE_AND  2 = 2, then groups of 2 are possible; if value  BITWISE_AND  4, the groups of 4 are possible; if value  BITWISE_AND  8, the groups of 8 are possible.  If no groups can formed according to this input, then an error will be thrown.</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_MBA_ADDR_INTERLEAVE_BIT</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>This dial sets the Centaur address bits used to interleave addresses between MBA01 and MBA23.  Valid values are 23 through 32.  See Centaur Spec Chapter 5 for details.   Used in the intifile. Will be obsolete when the MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT is set
+This attribute will only be found in a Tuelta system.
+</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>This dial sets the Centaur address bits used to interleave addresses between MBA01 and MBA23.  Valid values are 23 through 32.  See Centaur Spec Chapter 5 for details.   Used in the intifile </description>
+    <valueType>uint8</valueType>
+    <odmVisable/>
+    <odmChangeable/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_MBA_CACHELINE_INTERLEAVE_MODE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Value of on or off.  On is 256 bit interleave.  Off, the translation is on 128  bit interleave mode.  See centaur workbook chapter 5.  Will be obsolete when MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE is set.
+This attribute will only be alive in the Tuelta system.
+</description>
+    <valueType>uint8</valueType>
+    <enum>OFF = 0, ON = 1</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Value of on or off.  On is 256 bit interleave.  Off, the translation is on 128  bit interleave mode.  See centaur workbook chapter 5.</description>
+    <valueType>uint8</valueType>
+    <enum>OFF = 0, ON = 1</enum>
+    <odmVisable/>
+    <odmChangeable/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>At a system level, this attribute controls if interleaving is required, requested or never.  The MRW.</description>
+    <valueType>uint8</valueType>
+    <enum>NEVER = 0, REQUIRED = 1, REQUESTED = 2</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_CACHE_ENABLE</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Reflects the functionality of the L4 Cache.  Determines if the L4 is enabled or not. See chapter 6 of the Centaur Workbook.  On means the full cache is enabled.  HALF_A (EVEN) means only A is enabled and HALF_B (ODD) means only B is enabled. For DD1X, the values of UNK_OFF, UNK_ON, UNK_HALF_A and UNK_HALFB were added because early parts did not have the fuses blown correctly, so the cache repairs may not have worked. This value is set by the platform which can get the chips value by running the mss_cen_get_ecid function.
+Note: Cronus and Firmware plus our initfiles do not really support any of the UNK values.  It is the responsibility of the platform to map the UNK values to the appropriate value of OFF/ON/HALF_A/HALF_B</description>
+    <valueType>uint8</valueType>
+    <enum>OFF = 0, ON = 1, HALF_A = 3, HALF_B = 5, UNK_OFF = 8, UNK_ON = 9, UNK_HALF_A = 0xB, UNK_HALF_B = 0xD</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_PREFETCH_ENABLE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Value of on or off.  Determines if prefetching enabled or not. See chapter 7 of the Centaur Workbook.</description>
+    <valueType>uint8</valueType>
+    <enum>OFF = 0, ON = 1</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_CLEANER_ENABLE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Value of on or off.  Determines if the cleaner of the L4 cache (write modified entries to memory on idle cycles)  enabled or not. See chapter 7 of the Centaur Workbook.</description>
+    <valueType>uint8</valueType>
+    <enum>OFF = 0, ON = 1</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_MEM_MC_IN_GROUP</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>A 8 bit vector that would be a designation of which MC are involved in the group. So the bits would represent MC0,MC1,MC2,MC3,MC4,MC5,MC6,MC7-what is grouped into the first would go into [0], the 2nd group into entry [1] and so on. set in the mss_setup_bars</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array>8</array>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_MCS_GROUP_32</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>Data Structure from eff grouping to setup bars to help determine different groups
+   Non- Mirroring [0-7] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
+ //  Mirroring      [8-15] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
+Measured in GB</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array>16 16</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_EFF_DIMM_FUNCTIONAL_VECTOR</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>A bit vector (per Dean's request) specifying if a DIMM is functional.  DIMM attributes, such as SIZE, are qualified by this bit vector.  The attribute ANDed 0x80 means port 0, DIMM 0 is functional, 0x40 means port 0, DIMM 1 is functional.  0x08 means port 1, DIMM 0 is functional and 0x04 means port 1 DIMM 1 is functional.  A fully populated system would have the value of 0xCC. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none
+This factors in functionality</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_LPASR</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description> Low Power Auto Self-Refresh. This is for DDR4 MRS2.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>MANUAL_NORMAL =0, MANUAL_REDUCED = 1, MANUAL_EXTENDED = 2, ASR = 3</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_MPR_PAGE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>MPR Page Selection This is for DDR4 MRS3.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>PG0 = 0, PG1 = 1, PG2 = 2, PG3 = 3</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_GEARDOWN_MODE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Gear Down Mode. This is for DDR4 MRS3.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>HALF =0, QUARTER=1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_PER_DRAM_ACCESS</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Per DRAM accessibility.  This is for DDR4 MRS3.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, ENABLE = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_TEMP_READOUT</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Temperature sensor readout. This is for DDR4 MRS3.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, ENABLE = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_FINE_REFRESH_MODE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Fine refresh mode. This is for DDR4 MRS3.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>NORMAL = 0, FIXED_2X = 1, FIXED_4X = 2, FLY_2X = 5, FLY_4X = 6</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CRC_WR_LATENCY</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>write latency for CRC and DM. This is for DDR4 MRS3.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>4NCK = 4, 5NCK = 5, 6NCK = 6</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_MPR_RD_FORMAT</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>MPR READ FORMAT. This is for DDR4 MRS3.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>SERIAL = 0, PARALLEL = 1, STAGGERED = 2, RESERVED_TEMP= 3</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_MAX_POWERDOWN_MODE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Max Power down mode. This is for DDR4 MRS4.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, ENABLE = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_TEMP_REF_RANGE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Temp ref range. This is for DDR4 MRS4.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>NORMAL = 0, EXTEND = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_TEMP_REF_MODE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Temp controlled ref mode. This is for DDR4 MRS4.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, ENABLE = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_INT_VREF_MON</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Internal Vref Monitor.. This is for DDR4 MRS4.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, ENABLE = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CS_CMD_LATENCY</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>CS to CMD/ADDR Latency. This is for DDR4 MRS4.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, 3CYC = 3, 4CYC = 4, 5CYC = 5, 6CYC = 6, 8CYC = 8</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_SELF_REF_ABORT</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Self Refresh Abort. This is for DDR4 MRS4.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, ENABLE = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_RD_PREAMBLE_TRAIN</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Read Pre amble Training Mode. This is for DDR4 MRS4.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, ENABLE = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_RD_PREAMBLE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Read Pre amble. This is for DDR4 MRS4.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>1NCLK = 1, 2NCLK = 2</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_WR_PREAMBLE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Write Pre amble. This is for DDR4 MRS4.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>1NCLK = 1, 2NCLK = 2</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CA_PARITY_LATENCY</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>C/A Parity Latency Mode. This is for DDR4 MRS5.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, PL4 = 4, PL5 = 5, PL6 = 6, PL8 = 8</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CRC_ERROR_CLEAR</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>CRC Error Clear. This is for DDR4 MRS5.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>CLEAR = 0, ERROR = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CA_PARITY_ERROR_STATUS</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>C/A Parity Error Status. This is for DDR4 MRS5.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>CLEAR = 0, ERROR = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_ODT_INPUT_BUFF</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>ODT Input Buffer during power down. This is for DDR4 MRS5.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>ACTIVATED = 0, DEACTIVATED = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_RTT_PARK</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RTT_Park value. This is for DDR4 MRS5.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, 60OHM = 60, 120OHM = 120, 40OHM = 40, 240OHM = 240, 48OHM = 48, 80OHM = 80, 34OHM = 34</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2 4</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_CA_PARITY</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>CA Parity Persistance Error. This is for DDR4 MRS5.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, ENABLE = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DATA_MASK</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Data Mask. This is for DDR4 MRS5.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, ENABLE = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_WRITE_DBI</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Write DBI. This is for DDR4 MRS5.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, ENABLE = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_READ_DBI</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Read DBI. This is for DDR4 MRS5.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+creator: mss_eff_cnfg
+consumer: various
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, ENABLE = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_VREF_DQ_TRAIN_VALUE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>vrefdq_train value. This is for DDR4 MRS6.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+Creator: mss_eff_cnfg
+Consumer:various
+Firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2 4</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_VREF_DQ_TRAIN_RANGE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>vrefdq_train range. This is for DDR4 MRS6.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+Creator: mss_eff_cnfg
+Consumer:various
+Firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>RANGE1 = 0, RANGE2 = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2 4</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_VREF_DQ_TRAIN_ENABLE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>vrefdq_train enable. This is for DDR4 MRS6.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+Creator: mss_eff_cnfg
+Consumer:various
+Firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, ENABLE = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2 4</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_TCCD_L</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>tccd_l. This is for DDR4 MRS6.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+Creator: mss_eff_cnfg
+Consumer:various
+Firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>4NCK = 4, 5NCK = 5, 6NCK = 6, 7NCK = 7, 8NCK = 8</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_DRAM_TCCD_S</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>tccd_S. This is for DDR4 MRS6.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+Creator: mss_eff_cnfg
+Consumer:various
+Firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>4NCK = 4, 5NCK = 5, 6NCK = 6, 7NCK = 7, 8NCK = 8</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_TCCD_L</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>tccd_l. This is for DDR4 MRS6.  Computed in mss_eff_cnfg. Each memory channel will have a value.
+Creator: mss_eff_cnfg
+Consumer:various
+Firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>4NCK = 4, 5NCK = 5, 6NCK = 6, 7NCK = 7, 8NCK = 8</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_WRITE_CRC</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Write CRC control for DDR4 in MRS2.  Set in mss_eff_cnfg.  Each memory channel will have a value.
+Creator: mss_eff_cnfg
+Consumer:various
+Firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, ENABLE = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_CAL_STEP_ENABLE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>A bit vector denoting valid cal steps to run during dram_init_train. [0] EXT_ZQCAL
+[1] WR_LEVEL
+[2] DQS_ALIGN
+[3] RDCLK_ALIGN
+[4] READ_CTR
+[5] WRITE_CTR
+[6] COARSE_WR
+[7] COARSE_RD
+bits6:7  will be consumed together to form COARSE_LVL. </description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_DRAMINIT_RESET_DISABLE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>A disable switch for resetting the phy delay values at the beginning of calling mss_draminit_training.</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 1, ENABLE = 0</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_MEM_IPL_COMPLETE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>A numerical number indicating if the memory procedures are complete.  written by mss_setup_bars when the bars are now functional in the processor.  </description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_SLEW_RATE_DATA</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>The 4 bit result of running the slew calibration algorithm at various rates and impedances.  The first dimension is port, the second is the impedance of 24,30,34, and 40 Ohms.  The 3rd dimension is the rate: 3,4,5 or 6 V/ns.  Computed and sent to the correct data blocks in phy_reset.  Also used in advanced training</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 4 4</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_SLEW_RATE_ADR</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>The 4 bit result of running the slew calibration algorithm at various rates and impedances.  The first dimension is the port.  The second is the impedance of 15, 20, 30 and 40 Ohms.  The 3rd dimension is the rate:3, 4,5 or 6 V/ns.  Computed and sent to the correct data blocks in phy_reset.  Also used in advanced training</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 4 4</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_ECID</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Bits 0 to 63 of the ECID in array entry 0 and bits 64 to 127 in ECID array entry 1
+Created from running the mss_get_cen_ecid.C
+Firmware shares some code with the processor, so the attribute is named so they can point at a target and have common function.</description>
+    <valueType>uint64</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_ALLOW_SINGLE_PORT</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>When this value is true, then mss_eff config will allow a single port to have one dimm and will allow ports to have different sizes.  Used in eff_config</description>
+    <valueType>uint8</valueType>
+    <enum>FALSE = 0, TRUE = 1</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_DQS_SWIZZLE_TYPE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DQS Swizzle type is set by the platform to describe what kind of DQS connection is being used for register acceses. Type 0 is normal, type 1 is for systems with wiring like glacier 1, type 2 is for Pallmeto.  Additional types maybe defined if new boards have even different DQS swizzle features</description>
+    <valueType>uint8</valueType>
+    <enum>NORMAL_TYPE_0 = 0, GLACIER_TYPE_1 = 1, ISDIMM_TYPE_2 = 2</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_PSRO</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Set by the centaur mss_get_cen_ecid function used diagnostic and chip characterization reporting</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_NWELL_MISPLACEMENT</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Set by the platform depending on DD1 vs DD1.01.  If true, then SI settings affected by the NWELL problem are adjusted.  Used in eff_config</description>
+    <valueType>uint8</valueType>
+    <enum>FALSE = 0, TRUE = 1</enum>
+    <writeable/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_BLUEWATERFALL_BROKEN</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Set by the platform depending on DD1.0X vs DD1.03 or newer.  If true, then draminit_train will modify dqs_clk_ps and gate to work around the issue. Set in get ecid which determines if we are at 1.03</description>
+    <valueType>uint8</valueType>
+    <enum>FALSE = 0, TRUE = 1</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MCBIST_PATTERN</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Enables mcbist data pattern selection.</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MCBIST_TEST_TYPE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Enables mcbist test type selection.</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MCBIST_PRINTING_DISABLE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>MCBIST support for printing</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MCBIST_DATA_ENABLE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>MCBIST support for enabling data</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MCBIST_USER_RANK</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>MCBIST support for rank selection</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MCBIST_USER_BANK</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>MCBIST support for bank selection</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_SCHMOO_MULTIPLE_SETUP_CALL</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>MCBIST for multiple setup</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_BUFFER_LATENCY</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Additional buffer latency in the case of RDIMMs and LRDIMMs.    It is expected that this value will come from the VPD</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_LRDIMM_WORD_X</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Additional buffer control word for LRDIMM building of the BCW</description>
+    <valueType>uint64</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+        <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_LRDIMM_MR12_REG</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>LRDIMM MR1,2 register.
+DRAM Rtt_WR for all ranks, DRAM Rtt_Nom for ranks 0 and 1, DRAM driver impedance for all ranks.  Eff config should set this up.</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_EFF_LRDIMM_ADDITIONAL_CNTL_WORDS</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>LRDIMM additional RCD control words as set by DIMM SPD:
+F[3,4]RC10, F[3,4]RC11, F[5,6]RC10, F[5,6]RC11, F[7,8]RC10, F[7,8]RC11, F[9,10]RC10, F[9,10]RC11,
+F[1]RC8, F[3]RC9, F[3]RC8, F[1]RC11, F[1]RC12, F[1]RC13, F[1]RC14, F[1]RC15.
+Eff config should set this up</description>
+    <valueType>uint64</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_LRDIMM_ADDITIONAL_CNTL_WORDS</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>LRDIMM additional RCD control words as set by DIMM SPD:
+F[3,4]RC10, F[3,4]RC11, F[5,6]RC10, F[5,6]RC11, F[7,8]RC10, F[7,8]RC11, F[9,10]RC10, F[9,10]RC11,
+F[1]RC8, F[3]RC9, F[3]RC8, F[1]RC11, F[1]RC12, F[1]RC13, F[1]RC14, F[1]RC15.
+Eff config should set this up</description>
+    <valueType>uint64</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_LRDIMM_RANK_MULT_MODE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>LRDIMM rank multiplication mode.
+Will be set at an MBA level with one policy to be used</description>
+    <valueType>uint8</valueType>
+    <enum>NORMAL = 0, 2X_MULT = 2, 4X_MULT = 4</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_THROTTLE_CONTROL_RAS_WEIGHT</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RAS weight to use for memory throttle control - set in thermal procedures</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_THROTTLE_CONTROL_CAS_WEIGHT</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>CAS weight to use for memory throttle control - set in thermal procedures</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MCBIST_RANDOM_SEED_VALUE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Controls the MCBIST engine in the centaur chip.  The value will be set in mss_eff_config_shmoo.</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MCBIST_RANDOM_SEED_TYPE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Controls the MCBIST engine in the centaur chip.  The value will be set in mss_eff_config_shmoo.</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MCBIST_DDR4_PDA_ENABLE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Controls PDA train enable or PBA. 00 - Disable; 01 - PDA; 02 - PBA(Lrdimm)</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook DIMM power curve percent uplift for this system at max utilization.</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook DIMM power curve percent uplift for this system at idle utilization.</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MRW_MEM_THROTTLE_DENOMINATOR</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook throttle value for denominator cfg_nm_m</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_INIT_STATE</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>How far into the ipl istep the centaur has been brought up</description>
+    <enum>COLD = 0, CLOCKS_ON = 1, DMI_ACTIVE = 2</enum>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MRW_MAX_DRAM_DATABUS_UTIL</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook value for maximum dram data bus utilization in centi percent (c%).  Used to determine memory throttle values.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_EFF_VPD_VERSION</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>
+        The lowest VPD Version of the DIMMs attached to the MBA. Comes directly (in ASCII) of the VINI VZ keyword
+    </description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_NEST_CAPABLE_FREQUENCIES</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        The NEST frequencies the memory chip can run at computed by the mss_freq.  The possibilities are ORed together.  The platform uses these value and the MRW to determine what frequency to boot the fabric (nest) if it can. There are two values: 8G and 9.6G
+    </description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <enum>NONE = 0, 8_0G = 1, 9_6G = 2, 8_0G_OR_9_6G = 3</enum>
+</attribute> 
+
+<attribute>
+    <id>ATTR_CEN_MRW_STRICT_MBA_PLUG_RULE_CHECKING</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+       The MRW for a system should set this to TRUE for systems that must obey plug rules.  Lab environments should default this to off and allow the user to override using normal methods to test.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <enum>FALSE = 0, TRUE = 1</enum>
+</attribute> 
+
+<attribute>
+    <id>ATTR_CEN_MRW_MCS_GROUP_ALLOW_ONLY_ADJ_PAIR</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+       The MRW for a system should be set to TRUE unless adjacent MCS pairs are not accessable for grouping of 2. IBM systems, such as Tuleta, Brazos, Alpine, Firestone, ... should set this attribute to TRUE. A FALSE setting would instruct the grouping code to attempt grouping of non-adjacent MCS into a pair.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <enum>FALSE = 0, TRUE = 1</enum>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MRW_ENHANCED_GROUPING_NO_MIRRORING</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+       The MRW for a system should set this to TRUE for systems that do not want to suport MCS groupings larget than 2.  Mirroring  also must be disabled and is unusable. IBM systems, such as Tuleta, should set this attribute to FALSE.  Stradale based systems should set this to TRUE.  This instructs the grouping code to group contiguous memory controllers of the same size together.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <enum>FALSE = 0, TRUE = 1</enum>
+</attribute> 
+
+<attribute>
+    <id>ATTR_CEN_MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Used for Custom DIMMs to not enable the reading of the dimm temperature sensor on the master i2c bus</description>
+    <valueType>uint8</valueType>
+    <enum>OFF = 0, ON = 1</enum>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MRW_CDIMM_SPARE_I2C_TEMP_SENSOR_ENABLE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Used for Custom DIMMs to not enable the reading of the dimm temperature sensor on the spare i2c bus</description>
+    <valueType>uint8</valueType>
+    <enum>OFF = 0, ON = 1</enum>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_AVDD_OFFSET_DISABLE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Used for to determine whether to apply an offset to AVDD. Supplied by MRW.</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 1, ENABLE = 0</enum>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VDD_OFFSET_DISABLE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Used for to determine whether to apply an offset to VDD. Supplied by MRW.</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 1, ENABLE = 0</enum>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VCS_OFFSET_DISABLE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Used for to determine whether to apply an offset to VCS. Supplied by MRW.</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 1, ENABLE = 0</enum>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VPP_OFFSET_DISABLE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Used for to determine whether to apply an offset to VCS. Supplied by MRW.</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 1, ENABLE = 0</enum>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VDDR_OFFSET_DISABLE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Used for to determine whether to apply an offset to VDDR. Supplied by MRW.</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 1, ENABLE = 0</enum>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_AVDD_SLOPE_ACTIVE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Slope value used to determine the dynamic VID AVDD adjustment for ACTIVE parts. In uV/Centaur.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_AVDD_SLOPE_INACTIVE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Slope value used to determine the dynamic VID AVDD adjustment for INACTIVE parts. In uV/Centaur.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_AVDD_SLOPE_INTERCEPT</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Intercept value used to determine the dynamic VID AVDD adjustment for all parts. In mV.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VDD_SLOPE_ACTIVE</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Slope value used to determine the dynamic VID VDD adjustment for ACTIVE parts. In uV/Centaur.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VDD_SLOPE_INACTIVE</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Slope value used to determine the dynamic VID VDD adjustment for INACTIVE parts. In uV/Centaur.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VDD_SLOPE_INTERCEPT</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Intercept value used to determine the dynamic VID VDD adjustment for all parts. In mV.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VCS_SLOPE_ACTIVE</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Slope value used to determine the dynamic VID VCS adjustment for ACTIVE parts. In uV/Centaur.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VCS_SLOPE_INACTIVE</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Slope value used to determine the dynamic VID VCS adjustment for INACTIVE parts. In uV/Centaur.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VCS_SLOPE_INTERCEPT</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Intercept value used to determine the dynamic VID VCS adjustment for all parts. In mV.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VPP_SLOPE</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Slope value used to determine the dynamic VID VPP adjustment for all parts. In uV/Centaur.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VPP_SLOPE_INTERCEPT</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Intercept value used to determine the dynamic VID VPP adjustment for all parts. In mV.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_DDR3_VDDR_SLOPE</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Slope value used to determine the dynamic VID DDR3 VDDR adjustment for all parts. In uV/Centaur.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_DDR3_VDDR_INTERCEPT</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Intercept value used to determine the dynamic VID DDR3 VDDR adjustment for all parts. In mV.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_DDR4_VDDR_SLOPE</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Slope value used to determine the dynamic VID DDR3 VDDR adjustment for all parts. In uV/Centaur.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_DDR4_VDDR_INTERCEPT</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Intercept value used to determine the dynamic VID DDR3 VDDR adjustment for all parts. In mV.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VOLT_OVERRIDE</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Possible DRAM voltage override.</description>
+    <valueType>uint8</valueType>
+    <enum>NONE = 0x00, VOLT_135 = 0x01, VOLT_120 = 0x02</enum>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VOLT_COMPLIANT_DIMMS</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>List of Voltages that are compliant with the system. DIMMs that do not have voltages listed in their SPD as supported are errored out.  Procedure defined is currently 1.2V and 1.35V only.</description>
+    <valueType>uint8</valueType>
+    <enum> PROCEDURE_DEFINED = 0x00, ALL_VOLTAGES = 0x01</enum>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MRW_MCS_PREFETCH_RETRY_THRESHOLD</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Option to control MCS prefetch retry threshold, for performance optimization. This attribute controls the number of retries in the prefetch engine. Retry threshold available ranges from 16 to 30. Note: Values outside those ranges will default to 30. In MRW.</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MRW_POWER_CONTROL_REQUESTED</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Capable power control settings. In MRW.</description>
+    <valueType>uint8</valueType>
+    <enum>OFF = 0x00, SLOWEXIT = 0x01, FASTEXIT = 0x02</enum>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_AVDD_OFFSET</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Dynamic VID offset applied to AVDD. In mV.</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VDD_OFFSET</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Dynamic VID offset applied to VDD. In mV.</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VCS_OFFSET</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Dynamic VID offset applied to VCS. In mV.</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VPP_OFFSET</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Dynamic VID offset applied to VPP. In mV.</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VDDR_OFFSET</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Dynamic VID offset applied to VDDR. In mV.</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VDDR_OVERIDE_SPD</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Possible VDDR voltage override.</description>
+    <valueType>uint8</valueType>
+    <enum>NONE = 0x00, VOLT_1350 = 0x01, VOLT_1200 = 0x02</enum>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_VPD_ISDIMMTOC4DQ</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        ISDIMM DQ mapping that comes from QX keyword on the CDIMM VPD.
+    </description>
+    <valueType>uint8</valueType>
+    <array>4 80</array>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_VPD_ISDIMMTOC4DQS</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        ISDIMM DQQ mapping that comes from QS keyword on the CDIMM VPD. 
+    </description>
+    <valueType>uint8</valueType>
+    <array>4 20</array>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_ISDIMM_POWER_CURVE_ALGORITHM_VERSION</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Version of algorithm and dependent attributes used to calculate ISDIMM power curve attributes</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <readable/>
+    <writeable/>
+    <persistent/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MRW_DDR3_VDDR_MAX_LIMIT</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Maximum voltage limit for the dynamic VID DDR3 VDDR voltage setpoint. In mV.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MRW_DDR4_VDDR_MAX_LIMIT</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Maximum voltage limit for the dynamic VID DDR4 VDDR voltage setpoint. In mV.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>  
+
+<attribute>
+    <id>ATTR_CEN_MRW_MEM_SENSOR_CACHE_ADDR_MAP</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Machine Readable Workbook value detailing the wiring of the 8 dimm temperature sensors for non custom dimms, in DIMM A0,A1,B0,B1,C0,C1,D0,D1 order. One nibble per sensor where bit0 (MSB) is the i2c bus the sensor is attached to (0 for master, 1 for spare) and bits 1:3 are for A2,A1,A0 of the sensor i2c address (where A2 is MSB)</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_VMEM_REGULATOR_MAX_DIMM_COUNT</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Maximum number of installed DIMMs per VMEM regulator for all VMEM regulators in the system.</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook enablement of the HWP code to adjust the VMEM regulator power limit based on number of installed DIMMs.</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <enum>FALSE = 0, TRUE = 1</enum>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook value for the maximum possible number of dimms that can be installed under any of the VMEM regulators.</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook DDR3 VMEM regulator power limit per CDIMM assuming a full configuration. Units in cW.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR4</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook DDR4 VMEM regulator power limit per CDIMM assuming a full configuration. Units in cW.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MRW_WR_VREF_CHECK_VREF_STEP_SIZE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook attribute that holds the step size of the VREF when doing a box shmoo</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MRW_WR_VREF_CHECK_DELAY_STEP_SIZE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook attribute that holds the step size of the delay when doing a box shmoo</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <persistRuntime/>
+</attribute>
+
+<!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB -->
+<!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP -->
+</attributes>
author	Luke Mulkey <lwmulkey@us.ibm.com>	2016-11-14 16:33:46 -0600
committer	Daniel M. Crowell <dcrowell@us.ibm.com>	2017-08-04 09:10:53 -0400
commit	c999985603ebc509c3c64210c5332635e85e98af (patch)
tree	e475130fc1d642070e6b5b32d2365ca6047ad19d
parent	7302a891f6709ebdd7f5a65d29417f6b372e6e69 (diff)
download	talos-hostboot-c999985603ebc509c3c64210c5332635e85e98af.tar.gz talos-hostboot-c999985603ebc509c3c64210c5332635e85e98af.zip