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| author | Soma BhanuTej <soma.bhanu@in.ibm.com> | 2018-03-02 04:40:18 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-03-16 14:27:15 -0400 |
| commit | c09c372348bdd5fdc0e484ea162bbc2cae1dc8c3 (patch) | |
| tree | e086878055299060c8b3af782da34ce2e5da4783 | |
| parent | 288ca88910b6e039466ba500b4d939e95c2e33fd (diff) | |
| download | talos-hostboot-c09c372348bdd5fdc0e484ea162bbc2cae1dc8c3.tar.gz talos-hostboot-c09c372348bdd5fdc0e484ea162bbc2cae1dc8c3.zip | |
Change TP FIR bits 38, 39, 40 as recoverable & Masked
Change-Id: Ib21a9940b9b458a74d24a4a6bf1ad734ec4896c3
CQ: SW419535
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54951
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Daniel J. Henderson <hende@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54956
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C index fd16a1a01..765a6f548 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C @@ -76,7 +76,7 @@ const uint64_t PERV_LFIR_ACTION0[15] = const uint64_t PERV_LFIR_ACTION1[15] = { - 0xF000042000000000ULL, // TP + 0xF000042003800000ULL, // TP 0xF000000000000000ULL, // N0 0xF000000000000000ULL, // N1 0xF000000000000000ULL, // N2 @@ -95,7 +95,7 @@ const uint64_t PERV_LFIR_ACTION1[15] = const uint64_t PERV_LFIR_MASK[15] = { - 0x0FFFBBFFFC400000ULL, // TP + 0x0FFFBBFFFFC00000ULL, // TP 0x0FFFFFFFFFC00000ULL, // N0 0x0FFFFFFFFFC00000ULL, // N1 0x0FFFFFFFFFC00000ULL, // N2 |
