PRD: initial single bit analysis for Centaur

This is all the easy stuff (simple callouts in threshold). The more
complex changes will come in a later commit.

Change-Id: Id2bb2028fa8f3023395c025d8c9d24449b2fd3b5
RTC: 187481
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57426
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57478
CI-Ready: Zane C. Shelley <zshelle@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>

3 files changed, 494 insertions, 420 deletions

diff --git a/src/usr/diag/prdf/common/plat/cen/cen_centaur.rule b/src/usr/diag/prdf/common/plat/cen/cen_centaur.rule
index eff545ead..37298d943 100644
--- a/src/usr/diag/prdf/common/plat/cen/cen_centaur.rule
+++ b/src/usr/diag/prdf/common/plat/cen/cen_centaur.rule
@@ -5,7 +5,7 @@
 #
 # OpenPOWER HostBoot Project
 #
-# Contributors Listed Below - COPYRIGHT 2016,2017
+# Contributors Listed Below - COPYRIGHT 2016,2018
 # [+] International Business Machines Corp.
 #
 #
@@ -98,12 +98,12 @@ chip cen_centaur
     };
 
     ############################################################################
-    # TP chiplet pervasive FIR
+    # Centaur chip TP_LFIR
     ############################################################################
 
     register TP_LFIR
     {
-        name        "TP chiplet pervasive FIR";
+        name        "Centaur chip TP_LFIR";
         scomaddr    0x0104000A;
         reset       (&, 0x0104000B);
         mask        (|, 0x0104000F);
@@ -112,14 +112,14 @@ chip cen_centaur
 
     register TP_LFIR_MASK
     {
-        name        "TP chiplet pervasive FIR MASK";
+        name        "Centaur chip TP_LFIR MASK";
         scomaddr    0x0104000D;
         capture     group default;
     };
 
     register TP_LFIR_ACT0
     {
-        name        "TP chiplet pervasive FIR ACT0";
+        name        "Centaur chip TP_LFIR ACT0";
         scomaddr    0x01040010;
         capture     group default;
         capture     req nonzero("TP_LFIR");
@@ -127,7 +127,7 @@ chip cen_centaur
 
     register TP_LFIR_ACT1
     {
-        name        "TP chiplet pervasive FIR ACT1";
+        name        "Centaur chip TP_LFIR ACT1";
         scomaddr    0x01040011;
         capture     group default;
         capture     req nonzero("TP_LFIR");
@@ -159,12 +159,12 @@ chip cen_centaur
     };
 
     ############################################################################
-    # NEST chiplet pervasive FIR
+    # Centaur chip NEST_LFIR
     ############################################################################
 
     register NEST_LFIR
     {
-        name        "NEST chiplet pervasive FIR";
+        name        "Centaur chip NEST_LFIR";
         scomaddr    0x0204000A;
         reset       (&, 0x0204000B);
         mask        (|, 0x0204000F);
@@ -173,14 +173,14 @@ chip cen_centaur
 
     register NEST_LFIR_MASK
     {
-        name        "NEST chiplet pervasive FIR MASK";
+        name        "Centaur chip NEST_LFIR MASK";
         scomaddr    0x0204000D;
         capture     group default;
     };
 
     register NEST_LFIR_ACT0
     {
-        name        "NEST chiplet pervasive FIR ACT0";
+        name        "Centaur chip NEST_LFIR ACT0";
         scomaddr    0x02040010;
         capture     group default;
         capture     req nonzero("NEST_LFIR");
@@ -188,19 +188,19 @@ chip cen_centaur
 
     register NEST_LFIR_ACT1
     {
-        name        "NEST chiplet pervasive FIR ACT1";
+        name        "Centaur chip NEST_LFIR ACT1";
         scomaddr    0x02040011;
         capture     group default;
         capture     req nonzero("NEST_LFIR");
     };
 
     ############################################################################
-    # Memory Buffer DMI FIR
+    # Centaur chip DMIFIR
     ############################################################################
 
     register DMIFIR
     {
-        name        "Memory Buffer DMI FIR";
+        name        "Centaur chip DMIFIR";
         scomaddr    0x02010400;
         reset       (&, 0x02010401);
         mask        (|, 0x02010405);
@@ -209,14 +209,14 @@ chip cen_centaur
 
     register DMIFIR_MASK
     {
-        name        "Memory Buffer DMI FIR MASK";
+        name        "Centaur chip DMIFIR MASK";
         scomaddr    0x02010403;
         capture     group default;
     };
 
     register DMIFIR_ACT0
     {
-        name        "Memory Buffer DMI FIR ACT0";
+        name        "Centaur chip DMIFIR ACT0";
         scomaddr    0x02010406;
         capture     group default;
         capture     req nonzero("DMIFIR");
@@ -224,19 +224,19 @@ chip cen_centaur
 
     register DMIFIR_ACT1
     {
-        name        "Memory Buffer DMI FIR ACT1";
+        name        "Centaur chip DMIFIR ACT1";
         scomaddr    0x02010407;
         capture     group default;
         capture     req nonzero("DMIFIR");
     };
 
     ############################################################################
-    # Memory Buffer MBI FIR
+    # Centaur chip MBIFIR
     ############################################################################
 
     register MBIFIR
     {
-        name        "Memory Buffer MBI FIR";
+        name        "Centaur chip MBIFIR";
         scomaddr    0x02010800;
         reset       (&, 0x02010801);
         mask        (|, 0x02010805);
@@ -245,14 +245,14 @@ chip cen_centaur
 
     register MBIFIR_MASK
     {
-        name        "Memory Buffer MBI FIR MASK";
+        name        "Centaur chip MBIFIR MASK";
         scomaddr    0x02010803;
         capture     group default;
     };
 
     register MBIFIR_ACT0
     {
-        name        "Memory Buffer MBI FIR ACT0";
+        name        "Centaur chip MBIFIR ACT0";
         scomaddr    0x02010806;
         capture     group default;
         capture     req nonzero("MBIFIR");
@@ -260,19 +260,19 @@ chip cen_centaur
 
     register MBIFIR_ACT1
     {
-        name        "Memory Buffer MBI FIR ACT1";
+        name        "Centaur chip MBIFIR ACT1";
         scomaddr    0x02010807;
         capture     group default;
         capture     req nonzero("MBIFIR");
     };
 
     ############################################################################
-    # Memory Buffer MBS FIR
+    # Centaur chip MBSFIR
     ############################################################################
 
     register MBSFIR
     {
-        name        "Memory Buffer MBS FIR";
+        name        "Centaur chip MBSFIR";
         scomaddr    0x02011400;
         reset       (&, 0x02011401);
         mask        (|, 0x02011405);
@@ -281,14 +281,14 @@ chip cen_centaur
 
     register MBSFIR_MASK
     {
-        name        "Memory Buffer MBS FIR MASK";
+        name        "Centaur chip MBSFIR MASK";
         scomaddr    0x02011403;
         capture     group default;
     };
 
     register MBSFIR_ACT0
     {
-        name        "Memory Buffer MBS FIR ACT0";
+        name        "Centaur chip MBSFIR ACT0";
         scomaddr    0x02011406;
         capture     group default;
         capture     req nonzero("MBSFIR");
@@ -296,33 +296,33 @@ chip cen_centaur
 
     register MBSFIR_ACT1
     {
-        name        "Memory Buffer MBS FIR ACT1";
+        name        "Centaur chip MBSFIR ACT1";
         scomaddr    0x02011407;
         capture     group default;
         capture     req nonzero("MBSFIR");
     };
 
     ############################################################################
-    # Memory Buffer MBS SECURE FIR
+    # Centaur chip MBSSECUREFIR
     ############################################################################
 
     # This register is hardwired to channel failure (checkstop) and we cannot
     # mask or change the state of the action registers.
     register MBSSECUREFIR
     {
-        name        "Memory Buffer MBS SECURE FIR";
+        name        "Centaur chip MBSSECUREFIR";
         scomaddr    0x0201141e;
         reset       (&, 0x0201141f);
         capture     group default;
     };
 
     ############################################################################
-    # Memory Buffer MBS ECC FIR 0
+    # Centaur chip MBSECCFIR 0
     ############################################################################
 
     register MBSECCFIR_0
     {
-        name        "Memory Buffer MBS ECC FIR 0";
+        name        "Centaur chip MBSECCFIR 0";
         scomaddr    0x02011440;
         reset       (&, 0x02011441);
         mask        (|, 0x02011445);
@@ -331,14 +331,14 @@ chip cen_centaur
 
     register MBSECCFIR_0_MASK
     {
-        name        "Memory Buffer MBS ECC FIR 0 MASK";
+        name        "Centaur chip MBSECCFIR 0 MASK";
         scomaddr    0x02011443;
         capture     group default;
     };
 
     register MBSECCFIR_0_ACT0
     {
-        name        "Memory Buffer MBS ECC FIR 0 ACT0";
+        name        "Centaur chip MBSECCFIR 0 ACT0";
         scomaddr    0x02011446;
         capture     group default;
         capture     req nonzero("MBSECCFIR_0");
@@ -346,19 +346,19 @@ chip cen_centaur
 
     register MBSECCFIR_0_ACT1
     {
-        name        "Memory Buffer MBS ECC FIR 0 ACT1";
+        name        "Centaur chip MBSECCFIR 0 ACT1";
         scomaddr    0x02011447;
         capture     group default;
         capture     req nonzero("MBSECCFIR_0");
     };
 
     ############################################################################
-    # Memory Buffer MBS ECC FIR 1
+    # Centaur chip MBSECCFIR 1
     ############################################################################
 
     register MBSECCFIR_1
     {
-        name        "Memory Buffer MBS ECC FIR 1";
+        name        "Centaur chip MBSECCFIR 1";
         scomaddr    0x02011480;
         reset       (&, 0x02011481);
         mask        (|, 0x02011485);
@@ -367,14 +367,14 @@ chip cen_centaur
 
     register MBSECCFIR_1_MASK
     {
-        name        "Memory Buffer MBS ECC FIR 1 MASK";
+        name        "Centaur chip MBSECCFIR 1 MASK";
         scomaddr    0x02011483;
         capture     group default;
     };
 
     register MBSECCFIR_1_ACT0
     {
-        name        "Memory Buffer MBS ECC FIR 1 ACT0";
+        name        "Centaur chip MBSECCFIR 1 ACT0";
         scomaddr    0x02011486;
         capture     group default;
         capture     req nonzero("MBSECCFIR_1");
@@ -382,19 +382,19 @@ chip cen_centaur
 
     register MBSECCFIR_1_ACT1
     {
-        name        "Memory Buffer MBS ECC FIR 1 ACT1";
+        name        "Centaur chip MBSECCFIR 1 ACT1";
         scomaddr    0x02011487;
         capture     group default;
         capture     req nonzero("MBSECCFIR_1");
     };
 
     ############################################################################
-    # Memory Buffer SCAC FIR
+    # Centaur chip SCACFIR
     ############################################################################
 
     register SCACFIR
     {
-        name        "Memory Buffer SCAC FIR";
+        name        "Centaur chip SCACFIR";
         scomaddr    0x020115c0;
         reset       (&, 0x020115c1);
         mask        (|, 0x020115c5);
@@ -403,14 +403,14 @@ chip cen_centaur
 
     register SCACFIR_MASK
     {
-        name        "Memory Buffer SCAC FIR MASK";
+        name        "Centaur chip SCACFIR MASK";
         scomaddr    0x020115c3;
         capture     group default;
     };
 
     register SCACFIR_ACT0
     {
-        name        "Memory Buffer SCAC FIR ACT0";
+        name        "Centaur chip SCACFIR ACT0";
         scomaddr    0x020115c6;
         capture     group default;
         capture     req nonzero("SCACFIR");
@@ -418,19 +418,19 @@ chip cen_centaur
 
     register SCACFIR_ACT1
     {
-        name        "Memory Buffer SCAC FIR ACT1";
+        name        "Centaur chip SCACFIR ACT1";
         scomaddr    0x020115c7;
         capture     group default;
         capture     req nonzero("SCACFIR");
     };
 
     ############################################################################
-    # Memory Buffer MCBIST FIR 0
+    # Centaur chip MCBISTFIR 0
     ############################################################################
 
     register MCBISTFIR_0
     {
-        name        "Memory Buffer MCBIST FIR 0";
+        name        "Centaur chip MCBISTFIR 0";
         scomaddr    0x02011600;
         reset       (&, 0x02011601);
         mask        (|, 0x02011605);
@@ -439,14 +439,14 @@ chip cen_centaur
 
     register MCBISTFIR_0_MASK
     {
-        name        "Memory Buffer MCBIST FIR 0 MASK";
+        name        "Centaur chip MCBISTFIR 0 MASK";
         scomaddr    0x02011603;
         capture     group default;
     };
 
     register MCBISTFIR_0_ACT0
     {
-        name        "Memory Buffer MCBIST FIR 0 ACT0";
+        name        "Centaur chip MCBISTFIR 0 ACT0";
         scomaddr    0x02011606;
         capture     group default;
         capture     req nonzero("MCBISTFIR_0");
@@ -454,19 +454,19 @@ chip cen_centaur
 
     register MCBISTFIR_0_ACT1
     {
-        name        "Memory Buffer MCBIST FIR 0 ACT1";
+        name        "Centaur chip MCBISTFIR 0 ACT1";
         scomaddr    0x02011607;
         capture     group default;
         capture     req nonzero("MCBISTFIR_0");
     };
 
     ############################################################################
-    # Memory Buffer MCBIST FIR 1
+    # Centaur chip MCBISTFIR 1
     ############################################################################
 
     register MCBISTFIR_1
     {
-        name        "Memory Buffer MCBIST FIR 1";
+        name        "Centaur chip MCBISTFIR 1";
         scomaddr    0x02011700;
         reset       (&, 0x02011701);
         mask        (|, 0x02011705);
@@ -475,14 +475,14 @@ chip cen_centaur
 
     register MCBISTFIR_1_MASK
     {
-        name        "Memory Buffer MCBIST FIR 1 MASK";
+        name        "Centaur chip MCBISTFIR 1 MASK";
         scomaddr    0x02011703;
         capture     group default;
     };
 
     register MCBISTFIR_1_ACT0
     {
-        name        "Memory Buffer MCBIST FIR 1 ACT0";
+        name        "Centaur chip MCBISTFIR 1 ACT0";
         scomaddr    0x02011706;
         capture     group default;
         capture     req nonzero("MCBISTFIR_1");
@@ -490,7 +490,7 @@ chip cen_centaur
 
     register MCBISTFIR_1_ACT1
     {
-        name        "Memory Buffer MCBIST FIR 1 ACT1";
+        name        "Centaur chip MCBISTFIR 1 ACT1";
         scomaddr    0x02011707;
         capture     group default;
         capture     req nonzero("MCBISTFIR_1");
@@ -540,12 +540,12 @@ chip cen_centaur
     };
 
     ############################################################################
-    # MEM chiplet pervasive FIR
+    # Centaur chip MEM_LFIR
     ############################################################################
 
     register MEM_LFIR
     {
-        name        "MEM chiplet pervasive FIR";
+        name        "Centaur chip MEM_LFIR";
         scomaddr    0x0304000A;
         reset       (&, 0x0304000B);
         mask        (|, 0x0304000F);
@@ -554,14 +554,14 @@ chip cen_centaur
 
     register MEM_LFIR_MASK
     {
-        name        "MEM chiplet pervasive FIR MASK";
+        name        "Centaur chip MEM_LFIR MASK";
         scomaddr    0x0304000D;
         capture     group default;
     };
 
     register MEM_LFIR_ACT0
     {
-        name        "MEM chiplet pervasive FIR ACT0";
+        name        "Centaur chip MEM_LFIR ACT0";
         scomaddr    0x03040010;
         capture     group default;
         capture     req nonzero("MEM_LFIR");
@@ -569,13 +569,12 @@ chip cen_centaur
 
     register MEM_LFIR_ACT1
     {
-        name        "MEM chiplet pervasive FIR ACT1";
+        name        "Centaur chip MEM_LFIR ACT1";
         scomaddr    0x03040011;
         capture     group default;
         capture     req nonzero("MEM_LFIR");
     };
 
-
 # Include registers not defined by the xml
 .include "cen_centaur_regs.rule";
 
@@ -664,7 +663,7 @@ group gTP_CHIPLET_FIR filter singlebit
 };
 
 ################################################################################
-# TP chiplet pervasive FIR
+# Centaur chip TP_LFIR
 ################################################################################
 
 rule rTP_LFIR
@@ -675,102 +674,107 @@ rule rTP_LFIR
     TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 &  TP_LFIR_ACT1;
 };
 
-group gTP_LFIR filter singlebit
+group gTP_LFIR filter singlebit, cs_root_cause( 19, 20 )
 {
     /** TP_LFIR[0]
      *  CFIR internal parity error
      */
-    (rTP_LFIR, bit(0)) ? TBDDefaultCallout;
+    (rTP_LFIR, bit(0)) ? threshold_and_mask_self;
 
     /** TP_LFIR[1]
      *  GPIO (PCB error)
      */
-    (rTP_LFIR, bit(1)) ? TBDDefaultCallout;
+    (rTP_LFIR, bit(1)) ? defaultMaskedError;
 
     /** TP_LFIR[2]
      *  CC (PCB error)
      */
-    (rTP_LFIR, bit(2)) ? TBDDefaultCallout;
+    (rTP_LFIR, bit(2)) ? defaultMaskedError;
 
     /** TP_LFIR[3]
      *  CC (OPCG, parity, scan collision, ...)
      */
-    (rTP_LFIR, bit(3)) ? TBDDefaultCallout;
+    (rTP_LFIR, bit(3)) ? defaultMaskedError;
 
     /** TP_LFIR[4]
      *  PSC (PCB error)
      */
-    (rTP_LFIR, bit(4)) ? TBDDefaultCallout;
+    (rTP_LFIR, bit(4)) ? defaultMaskedError;
 
     /** TP_LFIR[5]
      *  PSC (parity error)
      */
-    (rTP_LFIR, bit(5)) ? TBDDefaultCallout;
+    (rTP_LFIR, bit(5)) ? defaultMaskedError;
 
     /** TP_LFIR[6]
      *  Thermal (parity error)
      */
-    (rTP_LFIR, bit(6)) ? TBDDefaultCallout;
+    (rTP_LFIR, bit(6)) ? defaultMaskedError;
 
     /** TP_LFIR[7]
      *  Thermal (PCB error)
      */
-    (rTP_LFIR, bit(7)) ? TBDDefaultCallout;
+    (rTP_LFIR, bit(7)) ? defaultMaskedError;
 
     /** TP_LFIR[8]
      *  Thermal (critical trip error)
      */
-    (rTP_LFIR, bit(8)) ? TBDDefaultCallout;
+    (rTP_LFIR, bit(8)) ? defaultMaskedError;
 
     /** TP_LFIR[9]
      *  Thermal (fatal trip error)
      */
-    (rTP_LFIR, bit(9)) ? TBDDefaultCallout;
+    (rTP_LFIR, bit(9)) ? defaultMaskedError;
 
     /** TP_LFIR[10]
      *  Thermal (voltage trip error)
      */
-    (rTP_LFIR, bit(10)) ? TBDDefaultCallout;
+    (rTP_LFIR, bit(10)) ? defaultMaskedError;
 
-    /** TP_LFIR[11:12]
+    /** TP_LFIR[11]
      *  Trace Array ( error)
      */
-    (rTP_LFIR, bit(11|12)) ? TBDDefaultCallout;
+    (rTP_LFIR, bit(11)) ? defaultMaskedError;
+
+    /** TP_LFIR[12]
+     *  Trace Array ( error)
+     */
+    (rTP_LFIR, bit(12)) ? defaultMaskedError;
 
     /** TP_LFIR[13:14]
      *  ITR
      */
-    (rTP_LFIR, bit(13|14)) ? TBDDefaultCallout;
+    (rTP_LFIR, bit(13|14)) ? threshold_and_mask_self;
 
     /** TP_LFIR[15]
      *  ITR (itr_tc_pcbsl_slave_fir_err)
      */
-    (rTP_LFIR, bit(15)) ? TBDDefaultCallout;
+    (rTP_LFIR, bit(15)) ? defaultMaskedError;
 
     /** TP_LFIR[16:18]
      *  PIB
      */
-    (rTP_LFIR, bit(16|17|18)) ? TBDDefaultCallout;
+    (rTP_LFIR, bit(16|17|18)) ? defaultMaskedError;
 
     /** TP_LFIR[19]
-     *  NEST PLLlock
+     *  NEST PLL unlock
      */
     (rTP_LFIR, bit(19)) ? TBDDefaultCallout;
 
     /** TP_LFIR[20]
-     *  MEM PLLlock
+     *  MEM PLL unlock
      */
     (rTP_LFIR, bit(20)) ? TBDDefaultCallout;
 
     /** TP_LFIR[21:39]
      *  Reserved
      */
-    (rTP_LFIR, bit(21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? TBDDefaultCallout;
+    (rTP_LFIR, bit(21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? defaultMaskedError;
 
     /** TP_LFIR[40]
      *  malfunction alert (local xstop in another chiplet)
      */
-    (rTP_LFIR, bit(40)) ? TBDDefaultCallout;
+    (rTP_LFIR, bit(40)) ? defaultMaskedError;
 
 };
 
@@ -841,7 +845,7 @@ group gNEST_CHIPLET_FIR filter singlebit
 };
 
 ################################################################################
-# NEST chiplet pervasive FIR
+# Centaur chip NEST_LFIR
 ################################################################################
 
 rule rNEST_LFIR
@@ -852,82 +856,87 @@ rule rNEST_LFIR
     NEST_LFIR & ~NEST_LFIR_MASK & ~NEST_LFIR_ACT0 &  NEST_LFIR_ACT1;
 };
 
-group gNEST_LFIR filter singlebit
+group gNEST_LFIR filter singlebit, cs_root_cause
 {
     /** NEST_LFIR[0]
      *  CFIR internal parity error
      */
-    (rNEST_LFIR, bit(0)) ? TBDDefaultCallout;
+    (rNEST_LFIR, bit(0)) ? threshold_and_mask_self;
 
     /** NEST_LFIR[1]
      *  GPIO (PCB error)
      */
-    (rNEST_LFIR, bit(1)) ? TBDDefaultCallout;
+    (rNEST_LFIR, bit(1)) ? defaultMaskedError;
 
     /** NEST_LFIR[2]
      *  CC (PCB error)
      */
-    (rNEST_LFIR, bit(2)) ? TBDDefaultCallout;
+    (rNEST_LFIR, bit(2)) ? defaultMaskedError;
 
     /** NEST_LFIR[3]
      *  CC (OPCG, parity, scan collision, ...)
      */
-    (rNEST_LFIR, bit(3)) ? TBDDefaultCallout;
+    (rNEST_LFIR, bit(3)) ? defaultMaskedError;
 
     /** NEST_LFIR[4]
      *  PSC (PCB error)
      */
-    (rNEST_LFIR, bit(4)) ? TBDDefaultCallout;
+    (rNEST_LFIR, bit(4)) ? defaultMaskedError;
 
     /** NEST_LFIR[5]
      *  PSC (parity error)
      */
-    (rNEST_LFIR, bit(5)) ? TBDDefaultCallout;
+    (rNEST_LFIR, bit(5)) ? defaultMaskedError;
 
     /** NEST_LFIR[6]
      *  Thermal (parity error)
      */
-    (rNEST_LFIR, bit(6)) ? TBDDefaultCallout;
+    (rNEST_LFIR, bit(6)) ? defaultMaskedError;
 
     /** NEST_LFIR[7]
      *  Thermal (PCB error)
      */
-    (rNEST_LFIR, bit(7)) ? TBDDefaultCallout;
+    (rNEST_LFIR, bit(7)) ? defaultMaskedError;
 
     /** NEST_LFIR[8]
      *  Thermal (critical trip error)
      */
-    (rNEST_LFIR, bit(8)) ? TBDDefaultCallout;
+    (rNEST_LFIR, bit(8)) ? defaultMaskedError;
 
     /** NEST_LFIR[9]
      *  Thermal (fatal trip error)
      */
-    (rNEST_LFIR, bit(9)) ? TBDDefaultCallout;
+    (rNEST_LFIR, bit(9)) ? defaultMaskedError;
 
     /** NEST_LFIR[10]
      *  Thermal (voltage trip error)
      */
-    (rNEST_LFIR, bit(10)) ? TBDDefaultCallout;
+    (rNEST_LFIR, bit(10)) ? defaultMaskedError;
 
-    /** NEST_LFIR[11:12]
+    /** NEST_LFIR[11]
      *  Trace Array ( error)
      */
-    (rNEST_LFIR, bit(11|12)) ? TBDDefaultCallout;
+    (rNEST_LFIR, bit(11)) ? defaultMaskedError;
+
+    /** NEST_LFIR[12]
+     *  Trace Array ( error)
+     */
+    (rNEST_LFIR, bit(12)) ? defaultMaskedError;
 
     /** NEST_LFIR[13:39]
      *  Reserved
      */
-    (rNEST_LFIR, bit(13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? TBDDefaultCallout;
+    (rNEST_LFIR, bit(13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? defaultMaskedError;
 
     /** NEST_LFIR[40]
      *  malfunction alert (local xstop in another chiplet)
      */
-    (rNEST_LFIR, bit(40)) ? TBDDefaultCallout;
+    (rNEST_LFIR, bit(40)) ? defaultMaskedError;
 
 };
 
 ################################################################################
-# Memory Buffer DMI FIR
+# Centaur chip DMIFIR
 ################################################################################
 
 rule rDMIFIR
@@ -938,32 +947,32 @@ rule rDMIFIR
     DMIFIR & ~DMIFIR_MASK & ~DMIFIR_ACT0 &  DMIFIR_ACT1;
 };
 
-group gDMIFIR filter singlebit
+group gDMIFIR filter singlebit, cs_root_cause( 10 )
 {
     /** DMIFIR[0]
      *  RX invalid state or parity error
      */
-    (rDMIFIR, bit(0)) ? TBDDefaultCallout;
+    (rDMIFIR, bit(0)) ? defaultMaskedError;
 
     /** DMIFIR[1]
      *  TX invalid state or parity error
      */
-    (rDMIFIR, bit(1)) ? TBDDefaultCallout;
+    (rDMIFIR, bit(1)) ? defaultMaskedError;
 
     /** DMIFIR[2]
      *  GCR hang error
      */
-    (rDMIFIR, bit(2)) ? TBDDefaultCallout;
+    (rDMIFIR, bit(2)) ? self_th_1;
 
     /** DMIFIR[3:7]
      *  Reserved
      */
-    (rDMIFIR, bit(3|4|5|6|7)) ? TBDDefaultCallout;
+    (rDMIFIR, bit(3|4|5|6|7)) ? defaultMaskedError;
 
     /** DMIFIR[8]
      *  Training error
      */
-    (rDMIFIR, bit(8)) ? TBDDefaultCallout;
+    (rDMIFIR, bit(8)) ? defaultMaskedError;
 
     /** DMIFIR[9]
      *  Spare lane deployed
@@ -985,25 +994,45 @@ group gDMIFIR filter singlebit
      */
     (rDMIFIR, bit(12)) ? TBDDefaultCallout;
 
-    /** DMIFIR[13:47]
+    /** DMIFIR[13:15]
      *  Reserved
      */
-    (rDMIFIR, bit(13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40|41|42|43|44|45|46|47)) ? TBDDefaultCallout;
+    (rDMIFIR, bit(13|14|15)) ? defaultMaskedError;
+
+    /** DMIFIR[16:23]
+     *  Bus 1 - unused
+     */
+    (rDMIFIR, bit(16|17|18|19|20|21|22|23)) ? defaultMaskedError;
+
+    /** DMIFIR[24:31]
+     *  Bus 2 - unused
+     */
+    (rDMIFIR, bit(24|25|26|27|28|29|30|31)) ? defaultMaskedError;
+
+    /** DMIFIR[32:39]
+     *  Bus 3 - unused
+     */
+    (rDMIFIR, bit(32|33|34|35|36|37|38|39)) ? defaultMaskedError;
+
+    /** DMIFIR[40:47]
+     *  Bus 4 - unused
+     */
+    (rDMIFIR, bit(40|41|42|43|44|45|46|47)) ? defaultMaskedError;
 
     /** DMIFIR[48]
-     *  SCOM FIR error
+     *  scom error
      */
-    (rDMIFIR, bit(48)) ? TBDDefaultCallout;
+    (rDMIFIR, bit(48)) ? threshold_and_mask_self;
 
     /** DMIFIR[49]
-     *  SCOM FIR error clone
+     *  scom error
      */
-    (rDMIFIR, bit(49)) ? TBDDefaultCallout;
+    (rDMIFIR, bit(49)) ? threshold_and_mask_self;
 
 };
 
 ################################################################################
-# Memory Buffer MBI FIR
+# Centaur chip MBIFIR
 ################################################################################
 
 rule rMBIFIR
@@ -1014,7 +1043,7 @@ rule rMBIFIR
     MBIFIR & ~MBIFIR_MASK & ~MBIFIR_ACT0 &  MBIFIR_ACT1;
 };
 
-group gMBIFIR filter singlebit
+group gMBIFIR filter singlebit, cs_root_cause( 0, 6, 8, 9 )
 {
     /** MBIFIR[0]
      *  Replay Timeout
@@ -1022,129 +1051,129 @@ group gMBIFIR filter singlebit
     (rMBIFIR, bit(0)) ? TBDDefaultCallout;
 
     /** MBIFIR[1]
-     *  CHANNEL_FAIL
+     *  Channel Fail
      */
-    (rMBIFIR, bit(1)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(1)) ? defaultMaskedError;
 
     /** MBIFIR[2]
-     *  CRC_ERROR
+     *  CRC Error
      */
-    (rMBIFIR, bit(2)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(2)) ? defaultMaskedError;
 
     /** MBIFIR[3]
-     *  FRAME_NOACK
+     *  Frame NoAck
      */
-    (rMBIFIR, bit(3)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(3)) ? defaultMaskedError;
 
     /** MBIFIR[4]
-     *  SEQID_OUT_OF_ORDER
+     *  Seqid Out of Order
      */
-    (rMBIFIR, bit(4)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(4)) ? defaultMaskedError;
 
     /** MBIFIR[5]
-     *  REPLAY_BUFFER_ECC_CE
+     *  Replay Buffer ECC CE
      */
-    (rMBIFIR, bit(5)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(5)) ? self_th_5perHour;
 
     /** MBIFIR[6]
-     *  REPLAY_BUFFER_ECC_UE
+     *  Replay Buffer ECC UE
      */
-    (rMBIFIR, bit(6)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(6)) ? self_th_1;
 
     /** MBIFIR[7]
-     *  MBI_STATE_MACHINE_TIMEOUT
+     *  MBI State Machine Timeout
      */
-    (rMBIFIR, bit(7)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(7)) ? defaultMaskedError;
 
     /** MBIFIR[8]
-     *  MBI_INTERNAL_CONTROL_PARITY_ERROR
+     *  MBI Internal Control Parity Error
      */
-    (rMBIFIR, bit(8)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(8)) ? self_th_1;
 
     /** MBIFIR[9]
-     *  MBI_DATA_FLOW_PARITY_ERROR
+     *  MBI Data Flow Parity Error
      */
-    (rMBIFIR, bit(9)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(9)) ? self_th_1;
 
     /** MBIFIR[10]
-     *  CRC_PERFORMANCE_DEGRADATION
+     *  CRC Performance Degradation
      */
-    (rMBIFIR, bit(10)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(10)) ? defaultMaskedError;
 
     /** MBIFIR[11]
-     *  HOST_MC_GLOBAL_CHECKSTOP
+     *  Global Host MC Checkstop
      */
-    (rMBIFIR, bit(11)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(11)) ? defaultMaskedError;
 
     /** MBIFIR[12]
-     *  HOST_MC_TRACESTOP
+     *  Host MC Tracestop
      */
-    (rMBIFIR, bit(12)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(12)) ? defaultMaskedError;
 
     /** MBIFIR[13]
-     *  CHANNEL_INTERLOCK_FAIL
+     *  Channel Interlock Fail
      */
-    (rMBIFIR, bit(13)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(13)) ? defaultMaskedError;
 
     /** MBIFIR[14]
-     *  HOST_MC_LOCAL_CHECKSTOP
+     *  Host MC Local Checkstop
      */
-    (rMBIFIR, bit(14)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(14)) ? defaultMaskedError;
 
     /** MBIFIR[15]
-     *  FRTL_COuNTER_OVERFLOW
+     *  FRTL Counter Overflow
      */
-    (rMBIFIR, bit(15)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(15)) ? defaultMaskedError;
 
     /** MBIFIR[16]
-     *  SCOM_REGISTER_PARITY_ERROR
+     *  SCOM Register parity error
      */
-    (rMBIFIR, bit(16)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(16)) ? self_th_1;
 
     /** MBIFIR[17]
-     *  IO_FAULT: IO to MBI
+     *  IO Fault
      */
-    (rMBIFIR, bit(17)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(17)) ? defaultMaskedError;
 
     /** MBIFIR[18]
-     *  MULTIPLE_REPLAY
+     *  Multiple Replay
      */
-    (rMBIFIR, bit(18)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(18)) ? defaultMaskedError;
 
     /** MBIFIR[19]
-     *  MBICFG_PARITY_SCOM_ERROR
+     *  MBICFG parity error
      */
-    (rMBIFIR, bit(19)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(19)) ? self_th_1;
 
     /** MBIFIR[20]
-     *  BUFFER_OVERRUN_ERROR
+     *  Replay Buffer Overrun
      */
     (rMBIFIR, bit(20)) ? TBDDefaultCallout;
 
     /** MBIFIR[21]
-     *  WAT_ERROR
+     *  WAT error
      */
-    (rMBIFIR, bit(21)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(21)) ? defaultMaskedError;
 
     /** MBIFIR[22:24]
      *  Reserved
      */
-    (rMBIFIR, bit(22|23|24)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(22|23|24)) ? defaultMaskedError;
 
     /** MBIFIR[25]
-     *  SCOM FIR error
+     *  internal scom error
      */
-    (rMBIFIR, bit(25)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(25)) ? threshold_and_mask_self;
 
     /** MBIFIR[26]
-     *  SCOM FIR error clone
+     *  internal scom error clone
      */
-    (rMBIFIR, bit(26)) ? TBDDefaultCallout;
+    (rMBIFIR, bit(26)) ? threshold_and_mask_self;
 
 };
 
 ################################################################################
-# Memory Buffer MBS FIR
+# Centaur chip MBSFIR
 ################################################################################
 
 rule rMBSFIR
@@ -1155,27 +1184,27 @@ rule rMBSFIR
     MBSFIR & ~MBSFIR_MASK & ~MBSFIR_ACT0 &  MBSFIR_ACT1;
 };
 
-group gMBSFIR filter singlebit
+group gMBSFIR filter singlebit, cs_root_cause( 0, 1, 2, 4, 6, 8, 10, 13, 16, 18, 20, 27, 30 )
 {
     /** MBSFIR[0]
-     *  INT_PROTOCOL_ERROR
+     *  HOST_PROTOCOL_ERROR
      */
     (rMBSFIR, bit(0)) ? TBDDefaultCallout;
 
     /** MBSFIR[1]
-     *  INVALID_ADDRESS_ERROR
+     *  INT_PROTOCOL_ERROR
      */
-    (rMBSFIR, bit(1)) ? TBDDefaultCallout;
+    (rMBSFIR, bit(1)) ? self_th_1;
 
     /** MBSFIR[2]
      *  INVALID_ADDRESS_ERROR
      */
-    (rMBSFIR, bit(2)) ? TBDDefaultCallout;
+    (rMBSFIR, bit(2)) ? level2_th_1;
 
     /** MBSFIR[3]
      *  EXTERNAL_TIMEOUT
      */
-    (rMBSFIR, bit(3)) ? TBDDefaultCallout;
+    (rMBSFIR, bit(3)) ? level2_th_1;
 
     /** MBSFIR[4]
      *  INTERNAL_TIMEOUT
@@ -1185,22 +1214,22 @@ group gMBSFIR filter singlebit
     /** MBSFIR[5]
      *  INT_BUFFER_CE
      */
-    (rMBSFIR, bit(5)) ? TBDDefaultCallout;
+    (rMBSFIR, bit(5)) ? self_th_32perDay;
 
     /** MBSFIR[6]
      *  INT_BUFFER_UE
      */
-    (rMBSFIR, bit(6)) ? TBDDefaultCallout;
+    (rMBSFIR, bit(6)) ? self_th_1;
 
     /** MBSFIR[7]
      *  INT_BUFFER_SUE
      */
-    (rMBSFIR, bit(7)) ? TBDDefaultCallout;
+    (rMBSFIR, bit(7)) ? defaultMaskedError;
 
     /** MBSFIR[8]
      *  INT_PARITY_ERROR
      */
-    (rMBSFIR, bit(8)) ? TBDDefaultCallout;
+    (rMBSFIR, bit(8)) ? self_th_1;
 
     /** MBSFIR[9]
      *  CACHE_SRW_CE
@@ -1215,7 +1244,7 @@ group gMBSFIR filter singlebit
     /** MBSFIR[11]
      *  CACHE_SRW_SUE
      */
-    (rMBSFIR, bit(11)) ? TBDDefaultCallout;
+    (rMBSFIR, bit(11)) ? defaultMaskedError;
 
     /** MBSFIR[12]
      *  CACHE_CO_CE
@@ -1230,7 +1259,7 @@ group gMBSFIR filter singlebit
     /** MBSFIR[14]
      *  CACHE_CO_SUE
      */
-    (rMBSFIR, bit(14)) ? TBDDefaultCallout;
+    (rMBSFIR, bit(14)) ? defaultMaskedError;
 
     /** MBSFIR[15]
      *  DIR_CE
@@ -1245,7 +1274,7 @@ group gMBSFIR filter singlebit
     /** MBSFIR[17]
      *  DIR_MEMBER_DELETED
      */
-    (rMBSFIR, bit(17)) ? TBDDefaultCallout;
+    (rMBSFIR, bit(17)) ? defaultMaskedError;
 
     /** MBSFIR[18]
      *  DIR_ALL_MEMBERS_DELETED
@@ -1258,54 +1287,54 @@ group gMBSFIR filter singlebit
     (rMBSFIR, bit(19)) ? TBDDefaultCallout;
 
     /** MBSFIR[20]
-     *  EDRAM_ERROR
+     *  EDRAM ERROR
      */
     (rMBSFIR, bit(20)) ? TBDDefaultCallout;
 
     /** MBSFIR[21]
      *  EMERGENCY_THROTTLE_SET
      */
-    (rMBSFIR, bit(21)) ? TBDDefaultCallout;
+    (rMBSFIR, bit(21)) ? defaultMaskedError;
 
     /** MBSFIR[22]
      *  HOST_INBAND_READ_ERROR
      */
-    (rMBSFIR, bit(22)) ? TBDDefaultCallout;
+    (rMBSFIR, bit(22)) ? defaultMaskedError;
 
     /** MBSFIR[23]
      *  HOST_INBAND_WRITE_ERROR
      */
-    (rMBSFIR, bit(23)) ? TBDDefaultCallout;
+    (rMBSFIR, bit(23)) ? defaultMaskedError;
 
     /** MBSFIR[24]
      *  OCC_INBAND_READ_ERROR
      */
-    (rMBSFIR, bit(24)) ? TBDDefaultCallout;
+    (rMBSFIR, bit(24)) ? defaultMaskedError;
 
     /** MBSFIR[25]
      *  OCC_INBAND_WRITE_ERROR
      */
-    (rMBSFIR, bit(25)) ? TBDDefaultCallout;
+    (rMBSFIR, bit(25)) ? defaultMaskedError;
 
     /** MBSFIR[26]
      *  SRB_BUFFER_CE
      */
-    (rMBSFIR, bit(26)) ? TBDDefaultCallout;
+    (rMBSFIR, bit(26)) ? threshold_and_mask_self;
 
     /** MBSFIR[27]
      *  SRB_BUFFER_UE
      */
-    (rMBSFIR, bit(27)) ? TBDDefaultCallout;
+    (rMBSFIR, bit(27)) ? self_th_1;
 
     /** MBSFIR[28]
      *  SRB_BUFFER_SUE
      */
-    (rMBSFIR, bit(28)) ? TBDDefaultCallout;
+    (rMBSFIR, bit(28)) ? defaultMaskedError;
 
     /** MBSFIR[29]
-     *  SCOM FIR error
+     *  DIR_PURGE_CE
      */
-    (rMBSFIR, bit(29)) ? TBDDefaultCallout; # CENTAUR_10
+    (rMBSFIR, bit(29)) ? defaultMaskedError;
 
     /** MBSFIR[30]
      *  PROXIMAL_CE_UE
@@ -1315,22 +1344,22 @@ group gMBSFIR filter singlebit
     /** MBSFIR[31:32]
      *  Spare
      */
-    (rMBSFIR, bit(31|32)) ? TBDDefaultCallout;
+    (rMBSFIR, bit(31|32)) ? defaultMaskedError;
 
     /** MBSFIR[33]
      *  SCOM FIR error
      */
-    (rMBSFIR, bit(33)) ? TBDDefaultCallout;
+    (rMBSFIR, bit(33)) ? threshold_and_mask_self;
 
     /** MBSFIR[34]
      *  SCOM FIR error clone
      */
-    (rMBSFIR, bit(34)) ? TBDDefaultCallout;
+    (rMBSFIR, bit(34)) ? threshold_and_mask_self;
 
 };
 
 ################################################################################
-# Memory Buffer MBS SECURE FIR
+# Centaur chip MBSSECUREFIR
 ################################################################################
 
 rule rMBSSECUREFIR
@@ -1339,42 +1368,42 @@ rule rMBSSECUREFIR
     MBSSECUREFIR;
 };
 
-group gMBSSECUREFIR filter singlebit
+group gMBSSECUREFIR filter singlebit, cs_root_cause( 0, 1, 2, 3, 4, 5 )
 {
     /** MBSSECUREFIR[0]
-     *  INVALID_MBSXCR_ACCESS
+     *  Invalid MBSXCR access
      */
-    (rMBSSECUREFIR, bit(0)) ? TBDDefaultCallout;
+    (rMBSSECUREFIR, bit(0)) ? level2_th_1_UERE;
 
     /** MBSSECUREFIR[1]
-     *  INVALID_MBAXCR01_ACCESS
+     *  Invalid MBSXCR01 access
      */
-    (rMBSSECUREFIR, bit(1)) ? TBDDefaultCallout;
+    (rMBSSECUREFIR, bit(1)) ? level2_th_1_UERE;
 
     /** MBSSECUREFIR[2]
-     *  INVALID_MBAXCR23_ACCESS
+     *  Invalid MBSXCR23 access
      */
-    (rMBSSECUREFIR, bit(2)) ? TBDDefaultCallout;
+    (rMBSSECUREFIR, bit(2)) ? level2_th_1_UERE;
 
     /** MBSSECUREFIR[3]
-     *  INVALID_MBAXCRMS_ACCRESS
+     *  Invalid MBSXCRMS access
      */
-    (rMBSSECUREFIR, bit(3)) ? TBDDefaultCallout;
+    (rMBSSECUREFIR, bit(3)) ? level2_th_1_UERE;
 
     /** MBSSECUREFIR[4]
-     *  Spare
+     *  spare
      */
-    (rMBSSECUREFIR, bit(4)) ? TBDDefaultCallout;
+    (rMBSSECUREFIR, bit(4)) ? level2_th_1_UERE;
 
     /** MBSSECUREFIR[5]
-     *  INVALID_SIR_MASK_OR_ACTION_REGISTER_ACCESS
+     *  Invalid SIR mask or action reg access
      */
-    (rMBSSECUREFIR, bit(5)) ? TBDDefaultCallout;
+    (rMBSSECUREFIR, bit(5)) ? level2_th_1_UERE;
 
 };
 
 ################################################################################
-# Memory Buffer MBS ECC FIR 0
+# Centaur chip MBSECCFIR 0
 ################################################################################
 
 rule rMBSECCFIR_0
@@ -1385,7 +1414,7 @@ rule rMBSECCFIR_0
     MBSECCFIR_0 & ~MBSECCFIR_0_MASK & ~MBSECCFIR_0_ACT0 &  MBSECCFIR_0_ACT1;
 };
 
-group gMBSECCFIR_0 filter singlebit
+group gMBSECCFIR_0 filter singlebit, cs_root_cause
 {
     /** MBSECCFIR_0[0]
      *  Memory chip mark on rank 0
@@ -1430,7 +1459,7 @@ group gMBSECCFIR_0 filter singlebit
     /** MBSECCFIR_0[8:15]
      *  Reserved
      */
-    (rMBSECCFIR_0, bit(8|9|10|11|12|13|14|15)) ? TBDDefaultCallout;
+    (rMBSECCFIR_0, bit(8|9|10|11|12|13|14|15)) ? defaultMaskedError;
 
     /** MBSECCFIR_0[16]
      *  Memory NCE
@@ -1445,7 +1474,7 @@ group gMBSECCFIR_0 filter singlebit
     /** MBSECCFIR_0[18]
      *  Memory SUE
      */
-    (rMBSECCFIR_0, bit(18)) ? TBDDefaultCallout;
+    (rMBSECCFIR_0, bit(18)) ? defaultMaskedError;
 
     /** MBSECCFIR_0[19]
      *  Memory UE
@@ -1455,47 +1484,47 @@ group gMBSECCFIR_0 filter singlebit
     /** MBSECCFIR_0[20:27]
      *  Maintenance chip mark
      */
-    (rMBSECCFIR_0, bit(20|21|22|23|24|25|26|27)) ? TBDDefaultCallout;
+    (rMBSECCFIR_0, bit(20|21|22|23|24|25|26|27)) ? defaultMaskedError;
 
     /** MBSECCFIR_0[28:35]
      *  Reserved
      */
-    (rMBSECCFIR_0, bit(28|29|30|31|32|33|34|35)) ? TBDDefaultCallout;
+    (rMBSECCFIR_0, bit(28|29|30|31|32|33|34|35)) ? defaultMaskedError;
 
     /** MBSECCFIR_0[36]
      *  Maintenance NCE
      */
-    (rMBSECCFIR_0, bit(36)) ? TBDDefaultCallout;
+    (rMBSECCFIR_0, bit(36)) ? defaultMaskedError;
 
     /** MBSECCFIR_0[37]
      *  Maintenance SCE
      */
-    (rMBSECCFIR_0, bit(37)) ? TBDDefaultCallout;
+    (rMBSECCFIR_0, bit(37)) ? defaultMaskedError;
 
     /** MBSECCFIR_0[38]
      *  Maintenance MCE
      */
-    (rMBSECCFIR_0, bit(38)) ? TBDDefaultCallout;
+    (rMBSECCFIR_0, bit(38)) ? defaultMaskedError;
 
     /** MBSECCFIR_0[39]
      *  Maintenance RCE
      */
-    (rMBSECCFIR_0, bit(39)) ? TBDDefaultCallout;
+    (rMBSECCFIR_0, bit(39)) ? defaultMaskedError;
 
     /** MBSECCFIR_0[40]
      *  Maintenance SUE
      */
-    (rMBSECCFIR_0, bit(40)) ? TBDDefaultCallout;
+    (rMBSECCFIR_0, bit(40)) ? defaultMaskedError;
 
     /** MBSECCFIR_0[41]
      *  Maintenance UE
      */
-    (rMBSECCFIR_0, bit(41)) ? TBDDefaultCallout;
+    (rMBSECCFIR_0, bit(41)) ? defaultMaskedError;
 
     /** MBSECCFIR_0[42]
      *  MPE during use maintenance mark mode
      */
-    (rMBSECCFIR_0, bit(42)) ? TBDDefaultCallout;
+    (rMBSECCFIR_0, bit(42)) ? defaultMaskedError;
 
     /** MBSECCFIR_0[43]
      *  Prefetch Memory UE
@@ -1505,25 +1534,25 @@ group gMBSECCFIR_0 filter singlebit
     /** MBSECCFIR_0[44]
      *  Memory RCD parity error
      */
-    (rMBSECCFIR_0, bit(44)) ? TBDDefaultCallout;
+    (rMBSECCFIR_0, bit(44)) ? self_th_1; # CUMULUS_10
 
     /** MBSECCFIR_0[45]
      *  Maintenance RCD parity error
      */
-    (rMBSECCFIR_0, bit(45)) ? TBDDefaultCallout;
+    (rMBSECCFIR_0, bit(45)) ? defaultMaskedError;
 
     /** MBSECCFIR_0[46]
-     *  Recoverable configuration register parity error
+     *  Recoverable config reg PE
      */
     (rMBSECCFIR_0, bit(46)) ? TBDDefaultCallout;
 
     /** MBSECCFIR_0[47]
-     *  Unrecoverable configuration register parity error
+     *  Unrecoverable config reg PE
      */
     (rMBSECCFIR_0, bit(47)) ? TBDDefaultCallout;
 
     /** MBSECCFIR_0[48]
-     *  Maskable configuration register parity error
+     *  Maskable config reg PE
      */
     (rMBSECCFIR_0, bit(48)) ? TBDDefaultCallout;
 
@@ -1533,19 +1562,19 @@ group gMBSECCFIR_0 filter singlebit
     (rMBSECCFIR_0, bit(49)) ? TBDDefaultCallout;
 
     /** MBSECCFIR_0[50]
-     *  Internal Scom Error
+     *  internal scom error
      */
     (rMBSECCFIR_0, bit(50)) ? TBDDefaultCallout;
 
     /** MBSECCFIR_0[51]
-     *  SCOM FIR error clone
+     *  internal scom error clone
      */
     (rMBSECCFIR_0, bit(51)) ? TBDDefaultCallout;
 
 };
 
 ################################################################################
-# Memory Buffer MBS ECC FIR 1
+# Centaur chip MBSECCFIR 1
 ################################################################################
 
 rule rMBSECCFIR_1
@@ -1601,7 +1630,7 @@ group gMBSECCFIR_1 filter singlebit
     /** MBSECCFIR_1[8:15]
      *  Reserved
      */
-    (rMBSECCFIR_1, bit(8|9|10|11|12|13|14|15)) ? TBDDefaultCallout;
+    (rMBSECCFIR_1, bit(8|9|10|11|12|13|14|15)) ? defaultMaskedError;
 
     /** MBSECCFIR_1[16]
      *  Memory NCE
@@ -1616,7 +1645,7 @@ group gMBSECCFIR_1 filter singlebit
     /** MBSECCFIR_1[18]
      *  Memory SUE
      */
-    (rMBSECCFIR_1, bit(18)) ? TBDDefaultCallout;
+    (rMBSECCFIR_1, bit(18)) ? defaultMaskedError;
 
     /** MBSECCFIR_1[19]
      *  Memory UE
@@ -1626,47 +1655,47 @@ group gMBSECCFIR_1 filter singlebit
     /** MBSECCFIR_1[20:27]
      *  Maintenance chip mark
      */
-    (rMBSECCFIR_1, bit(20|21|22|23|24|25|26|27)) ? TBDDefaultCallout;
+    (rMBSECCFIR_1, bit(20|21|22|23|24|25|26|27)) ? defaultMaskedError;
 
     /** MBSECCFIR_1[28:35]
      *  Reserved
      */
-    (rMBSECCFIR_1, bit(28|29|30|31|32|33|34|35)) ? TBDDefaultCallout;
+    (rMBSECCFIR_1, bit(28|29|30|31|32|33|34|35)) ? defaultMaskedError;
 
     /** MBSECCFIR_1[36]
      *  Maintenance NCE
      */
-    (rMBSECCFIR_1, bit(36)) ? TBDDefaultCallout;
+    (rMBSECCFIR_1, bit(36)) ? defaultMaskedError;
 
     /** MBSECCFIR_1[37]
      *  Maintenance SCE
      */
-    (rMBSECCFIR_1, bit(37)) ? TBDDefaultCallout;
+    (rMBSECCFIR_1, bit(37)) ? defaultMaskedError;
 
     /** MBSECCFIR_1[38]
      *  Maintenance MCE
      */
-    (rMBSECCFIR_1, bit(38)) ? TBDDefaultCallout;
+    (rMBSECCFIR_1, bit(38)) ? defaultMaskedError;
 
     /** MBSECCFIR_1[39]
      *  Maintenance RCE
      */
-    (rMBSECCFIR_1, bit(39)) ? TBDDefaultCallout;
+    (rMBSECCFIR_1, bit(39)) ? defaultMaskedError;
 
     /** MBSECCFIR_1[40]
      *  Maintenance SUE
      */
-    (rMBSECCFIR_1, bit(40)) ? TBDDefaultCallout;
+    (rMBSECCFIR_1, bit(40)) ? defaultMaskedError;
 
     /** MBSECCFIR_1[41]
      *  Maintenance UE
      */
-    (rMBSECCFIR_1, bit(41)) ? TBDDefaultCallout;
+    (rMBSECCFIR_1, bit(41)) ? defaultMaskedError;
 
     /** MBSECCFIR_1[42]
      *  MPE during use maintenance mark mode
      */
-    (rMBSECCFIR_1, bit(42)) ? TBDDefaultCallout;
+    (rMBSECCFIR_1, bit(42)) ? defaultMaskedError;
 
     /** MBSECCFIR_1[43]
      *  Prefetch Memory UE
@@ -1676,25 +1705,25 @@ group gMBSECCFIR_1 filter singlebit
     /** MBSECCFIR_1[44]
      *  Memory RCD parity error
      */
-    (rMBSECCFIR_1, bit(44)) ? TBDDefaultCallout;
+    (rMBSECCFIR_1, bit(44)) ? self_th_1; # CUMULUS_10
 
     /** MBSECCFIR_1[45]
      *  Maintenance RCD parity error
      */
-    (rMBSECCFIR_1, bit(45)) ? TBDDefaultCallout;
+    (rMBSECCFIR_1, bit(45)) ? defaultMaskedError;
 
     /** MBSECCFIR_1[46]
-     *  Recoverable configuration register parity error
+     *  Recoverable config reg PE
      */
     (rMBSECCFIR_1, bit(46)) ? TBDDefaultCallout;
 
     /** MBSECCFIR_1[47]
-     *  Unrecoverable configuration register parity error
+     *  Unrecoverable config reg PE
      */
     (rMBSECCFIR_1, bit(47)) ? TBDDefaultCallout;
 
     /** MBSECCFIR_1[48]
-     *  Maskable configuration register parity error
+     *  Maskable config reg PE
      */
     (rMBSECCFIR_1, bit(48)) ? TBDDefaultCallout;
 
@@ -1704,19 +1733,19 @@ group gMBSECCFIR_1 filter singlebit
     (rMBSECCFIR_1, bit(49)) ? TBDDefaultCallout;
 
     /** MBSECCFIR_1[50]
-     *  Internal Scom Error
+     *  internal scom error
      */
     (rMBSECCFIR_1, bit(50)) ? TBDDefaultCallout;
 
     /** MBSECCFIR_1[51]
-     *  SCOM FIR error clone
+     *  internal scom error clone
      */
     (rMBSECCFIR_1, bit(51)) ? TBDDefaultCallout;
 
 };
 
 ################################################################################
-# Memory Buffer SCAC FIR
+# Centaur chip SCACFIR
 ################################################################################
 
 rule rSCACFIR
@@ -1727,162 +1756,162 @@ rule rSCACFIR
     SCACFIR & ~SCACFIR_MASK & ~SCACFIR_ACT0 &  SCACFIR_ACT1;
 };
 
-group gSCACFIR filter singlebit
+group gSCACFIR filter singlebit, cs_root_cause
 {
     /** SCACFIR[0]
      *  I2CM(0) Invalid Address
      */
-    (rSCACFIR, bit(0)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(0)) ? defaultMaskedError;
 
     /** SCACFIR[1]
      *  I2CM(1) Invalid Write
      */
-    (rSCACFIR, bit(1)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(1)) ? defaultMaskedError;
 
     /** SCACFIR[2]
      *  I2CM(2) Invalid Read
      */
-    (rSCACFIR, bit(2)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(2)) ? defaultMaskedError;
 
     /** SCACFIR[3]
      *  I2CM(3) Pib Address Parity Error
      */
-    (rSCACFIR, bit(3)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(3)) ? defaultMaskedError;
 
     /** SCACFIR[4]
      *  I2CM(4) Pib Parity Error
      */
-    (rSCACFIR, bit(4)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(4)) ? defaultMaskedError;
 
     /** SCACFIR[5]
      *  I2CM(5) LB parity error
      */
-    (rSCACFIR, bit(5)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(5)) ? defaultMaskedError;
 
     /** SCACFIR[6:9]
-     *  Reserved at 0 for external macro expansion reporting.
+     *  spare
      */
-    (rSCACFIR, bit(6|7|8|9)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(6|7|8|9)) ? defaultMaskedError;
 
     /** SCACFIR[10]
      *  I2CM(45) : Invalid Command
      */
-    (rSCACFIR, bit(10)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(10)) ? defaultMaskedError;
 
     /** SCACFIR[11]
      *  I2CM(46) : Parity Error
      */
-    (rSCACFIR, bit(11)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(11)) ? defaultMaskedError;
 
     /** SCACFIR[12]
      *  I2CM(47): Backend Overrun Error
      */
-    (rSCACFIR, bit(12)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(12)) ? defaultMaskedError;
 
     /** SCACFIR[13]
      *  I2CM(48): Backend Access Error
      */
-    (rSCACFIR, bit(13)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(13)) ? defaultMaskedError;
 
     /** SCACFIR[14]
      *  I2CM(49): Arbitration Lost Error
      */
-    (rSCACFIR, bit(14)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(14)) ? defaultMaskedError;
 
     /** SCACFIR[15]
      *  I2CM(50): Nack Received Error
      */
-    (rSCACFIR, bit(15)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(15)) ? defaultMaskedError;
 
     /** SCACFIR[16]
      *  I2CM(53): Stop Error
      */
-    (rSCACFIR, bit(16)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(16)) ? defaultMaskedError;
 
     /** SCACFIR[17]
      *  Local PIB Response code 1
      */
-    (rSCACFIR, bit(17)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(17)) ? defaultMaskedError;
 
     /** SCACFIR[18]
      *  Local PIB Response code 2
      */
-    (rSCACFIR, bit(18)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(18)) ? defaultMaskedError;
 
     /** SCACFIR[19]
      *  Local PIB Response code 3
      */
-    (rSCACFIR, bit(19)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(19)) ? defaultMaskedError;
 
     /** SCACFIR[20]
      *  Local PIB Response code 4
      */
-    (rSCACFIR, bit(20)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(20)) ? defaultMaskedError;
 
     /** SCACFIR[21]
      *  Local PIB Response code 5
      */
-    (rSCACFIR, bit(21)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(21)) ? defaultMaskedError;
 
     /** SCACFIR[22]
      *  Local PIB Response code 6
      */
-    (rSCACFIR, bit(22)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(22)) ? defaultMaskedError;
 
     /** SCACFIR[23]
      *  Local PIB Response code 7
      */
-    (rSCACFIR, bit(23)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(23)) ? defaultMaskedError;
 
     /** SCACFIR[24]
      *  Stall Threshold Error
      */
-    (rSCACFIR, bit(24)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(24)) ? defaultMaskedError;
 
     /** SCACFIR[25]
      *  Parity Error on Internal Register
      */
-    (rSCACFIR, bit(25)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(25)) ? self_th_1;
 
     /** SCACFIR[26]
      *  Parity Error on Pib Target Register
      */
-    (rSCACFIR, bit(26)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(26)) ? self_th_1;
 
     /** SCACFIR[27:31]
      *  Reserved
      */
-    (rSCACFIR, bit(27|28|29|30|31)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(27|28|29|30|31)) ? defaultMaskedError;
 
     /** SCACFIR[32]
      *  State Machine / Ctrl Logic Error
      */
-    (rSCACFIR, bit(32)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(32)) ? self_th_1;
 
     /** SCACFIR[33]
      *  Register access error
      */
-    (rSCACFIR, bit(33)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(33)) ? level2_th_1;
 
     /** SCACFIR[34]
-     *  Reset command error
+     *  PIB error initiating RESET cmd to I2CM
      */
-    (rSCACFIR, bit(34)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(34)) ? defaultMaskedError;
 
     /** SCACFIR[35]
-     *  SCOM FIR error
+     *  Internal SCOM Error
      */
-    (rSCACFIR, bit(35)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(35)) ? threshold_and_mask_self;
 
     /** SCACFIR[36]
-     *  SCOM FIR error clone
+     *  Internal SCOM Error
      */
-    (rSCACFIR, bit(36)) ? TBDDefaultCallout;
+    (rSCACFIR, bit(36)) ? threshold_and_mask_self;
 
 };
 
 ################################################################################
-# Memory Buffer MCBIST FIR 0
+# Centaur chip MCBISTFIR 0
 ################################################################################
 
 rule rMCBISTFIR_0
@@ -1893,7 +1922,7 @@ rule rMCBISTFIR_0
     MCBISTFIR_0 & ~MCBISTFIR_0_MASK & ~MCBISTFIR_0_ACT0 &  MCBISTFIR_0_ACT1;
 };
 
-group gMCBISTFIR_0 filter singlebit
+group gMCBISTFIR_0 filter singlebit, cs_root_cause
 {
     /** MCBISTFIR_0[0]
      *  SCOM Parity Errors
@@ -1908,17 +1937,17 @@ group gMCBISTFIR_0 filter singlebit
     /** MCBISTFIR_0[2]
      *  DRAM event 0 error
      */
-    (rMCBISTFIR_0, bit(2)) ? TBDDefaultCallout;
+    (rMCBISTFIR_0, bit(2)) ? defaultMaskedError;
 
     /** MCBISTFIR_0[3]
      *  DRAM event 1 error
      */
-    (rMCBISTFIR_0, bit(3)) ? TBDDefaultCallout;
+    (rMCBISTFIR_0, bit(3)) ? defaultMaskedError;
 
     /** MCBISTFIR_0[4:14]
      *  Reserved
      */
-    (rMCBISTFIR_0, bit(4|5|6|7|8|9|10|11|12|13|14)) ? TBDDefaultCallout;
+    (rMCBISTFIR_0, bit(4|5|6|7|8|9|10|11|12|13|14)) ? defaultMaskedError;
 
     /** MCBISTFIR_0[15]
      *  SCOM FIR error
@@ -1933,7 +1962,7 @@ group gMCBISTFIR_0 filter singlebit
 };
 
 ################################################################################
-# Memory Buffer MCBIST FIR 1
+# Centaur chip MCBISTFIR 1
 ################################################################################
 
 rule rMCBISTFIR_1
@@ -1944,7 +1973,7 @@ rule rMCBISTFIR_1
     MCBISTFIR_1 & ~MCBISTFIR_1_MASK & ~MCBISTFIR_1_ACT0 &  MCBISTFIR_1_ACT1;
 };
 
-group gMCBISTFIR_1 filter singlebit
+group gMCBISTFIR_1 filter singlebit, cs_root_cause
 {
     /** MCBISTFIR_1[0]
      *  SCOM Parity Errors
@@ -1959,17 +1988,17 @@ group gMCBISTFIR_1 filter singlebit
     /** MCBISTFIR_1[2]
      *  DRAM event 0 error
      */
-    (rMCBISTFIR_1, bit(2)) ? TBDDefaultCallout;
+    (rMCBISTFIR_1, bit(2)) ? defaultMaskedError;
 
     /** MCBISTFIR_1[3]
      *  DRAM event 1 error
      */
-    (rMCBISTFIR_1, bit(3)) ? TBDDefaultCallout;
+    (rMCBISTFIR_1, bit(3)) ? defaultMaskedError;
 
     /** MCBISTFIR_1[4:14]
      *  Reserved
      */
-    (rMCBISTFIR_1, bit(4|5|6|7|8|9|10|11|12|13|14)) ? TBDDefaultCallout;
+    (rMCBISTFIR_1, bit(4|5|6|7|8|9|10|11|12|13|14)) ? defaultMaskedError;
 
     /** MCBISTFIR_1[15]
      *  SCOM FIR error
@@ -2069,7 +2098,7 @@ group gMEM_CHIPLET_SPA_FIR filter singlebit
 };
 
 ################################################################################
-# MEM chiplet pervasive FIR
+# Centaur chip MEM_LFIR
 ################################################################################
 
 rule rMEM_LFIR
@@ -2080,82 +2109,92 @@ rule rMEM_LFIR
     MEM_LFIR & ~MEM_LFIR_MASK & ~MEM_LFIR_ACT0 &  MEM_LFIR_ACT1;
 };
 
-group gMEM_LFIR filter singlebit
+group gMEM_LFIR filter singlebit, cs_root_cause
 {
     /** MEM_LFIR[0]
      *  CFIR internal parity error
      */
-    (rMEM_LFIR, bit(0)) ? TBDDefaultCallout;
+    (rMEM_LFIR, bit(0)) ? threshold_and_mask_self;
 
     /** MEM_LFIR[1]
      *  GPIO (PCB error)
      */
-    (rMEM_LFIR, bit(1)) ? TBDDefaultCallout;
+    (rMEM_LFIR, bit(1)) ? defaultMaskedError;
 
     /** MEM_LFIR[2]
      *  CC (PCB error)
      */
-    (rMEM_LFIR, bit(2)) ? TBDDefaultCallout;
+    (rMEM_LFIR, bit(2)) ? defaultMaskedError;
 
     /** MEM_LFIR[3]
      *  CC (OPCG, parity, scan collision, ...)
      */
-    (rMEM_LFIR, bit(3)) ? TBDDefaultCallout;
+    (rMEM_LFIR, bit(3)) ? defaultMaskedError;
 
     /** MEM_LFIR[4]
      *  PSC (PCB error)
      */
-    (rMEM_LFIR, bit(4)) ? TBDDefaultCallout;
+    (rMEM_LFIR, bit(4)) ? defaultMaskedError;
 
     /** MEM_LFIR[5]
      *  PSC (parity error)
      */
-    (rMEM_LFIR, bit(5)) ? TBDDefaultCallout;
+    (rMEM_LFIR, bit(5)) ? defaultMaskedError;
 
     /** MEM_LFIR[6]
      *  Thermal (parity error)
      */
-    (rMEM_LFIR, bit(6)) ? TBDDefaultCallout;
+    (rMEM_LFIR, bit(6)) ? defaultMaskedError;
 
     /** MEM_LFIR[7]
      *  Thermal (PCB error)
      */
-    (rMEM_LFIR, bit(7)) ? TBDDefaultCallout;
+    (rMEM_LFIR, bit(7)) ? defaultMaskedError;
 
     /** MEM_LFIR[8]
      *  Thermal (critical trip error)
      */
-    (rMEM_LFIR, bit(8)) ? TBDDefaultCallout;
+    (rMEM_LFIR, bit(8)) ? defaultMaskedError;
 
     /** MEM_LFIR[9]
      *  Thermal (fatal trip error)
      */
-    (rMEM_LFIR, bit(9)) ? TBDDefaultCallout;
+    (rMEM_LFIR, bit(9)) ? defaultMaskedError;
 
     /** MEM_LFIR[10]
      *  Thermal (voltage trip error)
      */
-    (rMEM_LFIR, bit(10)) ? TBDDefaultCallout;
+    (rMEM_LFIR, bit(10)) ? defaultMaskedError;
+
+    /** MEM_LFIR[11]
+     *  MBA01 Trace Array ( error)
+     */
+    (rMEM_LFIR, bit(11)) ? defaultMaskedError;
 
-    /** MEM_LFIR[11:12]
+    /** MEM_LFIR[12]
      *  MBA01 Trace Array ( error)
      */
-    (rMEM_LFIR, bit(11|12)) ? TBDDefaultCallout;
+    (rMEM_LFIR, bit(12)) ? defaultMaskedError;
+
+    /** MEM_LFIR[13]
+     *  MBA23 Trace Array ( error)
+     */
+    (rMEM_LFIR, bit(13)) ? defaultMaskedError;
 
-    /** MEM_LFIR[13:14]
+    /** MEM_LFIR[14]
      *  MBA23 Trace Array ( error)
      */
-    (rMEM_LFIR, bit(13|14)) ? TBDDefaultCallout;
+    (rMEM_LFIR, bit(14)) ? defaultMaskedError;
 
     /** MEM_LFIR[15:39]
      *  Reserved
      */
-    (rMEM_LFIR, bit(15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? TBDDefaultCallout;
+    (rMEM_LFIR, bit(15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? defaultMaskedError;
 
     /** MEM_LFIR[40]
      *  malfunction alert (local xstop in another chiplet)
      */
-    (rMEM_LFIR, bit(40)) ? TBDDefaultCallout;
+    (rMEM_LFIR, bit(40)) ? defaultMaskedError;
 
 };
 
diff --git a/src/usr/diag/prdf/common/plat/cen/cen_common_actions.rule b/src/usr/diag/prdf/common/plat/cen/cen_common_actions.rule
index 8c6a3f1cb..e9f2e9b3b 100644
--- a/src/usr/diag/prdf/common/plat/cen/cen_common_actions.rule
+++ b/src/usr/diag/prdf/common/plat/cen/cen_common_actions.rule
@@ -5,7 +5,7 @@
 #
 # OpenPOWER HostBoot Project
 #
-# Contributors Listed Below - COPYRIGHT 2017
+# Contributors Listed Below - COPYRIGHT 2017,2018
 # [+] International Business Machines Corp.
 #
 #
@@ -71,6 +71,12 @@ actionclass threshold32pday
     threshold( field(32 / day) );
 };
 
+/** Threshold of 5 per hour */
+actionclass threshold5phour
+{
+    threshold( field(5 / hour) );
+};
+
 ################################################################################
 #                       Threshold and Mask policy
 ################################################################################
@@ -112,6 +118,40 @@ actionclass callout2ndLvlMed
 { callout(procedure(LEVEL2_SUPPORT), MRU_MED); };
 
 ################################################################################
+#                           Callouts with thresholds                           #
+################################################################################
+
+actionclass self_th_1
+{
+    calloutSelfMed;
+    threshold1;
+};
+
+actionclass self_th_5perHour
+{
+    calloutSelfMed;
+    threshold5phour;
+};
+
+actionclass self_th_32perDay
+{
+    calloutSelfMed;
+    threshold32pday;
+};
+
+actionclass level2_th_1
+{
+    callout2ndLvlMed;
+    threshold1;
+};
+
+################################################################################
+#                           Callouts with flags                                #
+################################################################################
+
+actionclass level2_th_1_UERE { level2_th_1; SueSource; };
+
+################################################################################
 #                               Default callouts                               #
 ################################################################################
 
diff --git a/src/usr/diag/prdf/common/plat/cen/cen_mba.rule b/src/usr/diag/prdf/common/plat/cen/cen_mba.rule
index 8f22ea592..23b6f4f3e 100644
--- a/src/usr/diag/prdf/common/plat/cen/cen_mba.rule
+++ b/src/usr/diag/prdf/common/plat/cen/cen_mba.rule
@@ -5,7 +5,7 @@
 #
 # OpenPOWER HostBoot Project
 #
-# Contributors Listed Below - COPYRIGHT 2012,2017
+# Contributors Listed Below - COPYRIGHT 2012,2018
 # [+] International Business Machines Corp.
 #
 #
@@ -44,12 +44,12 @@ chip cen_mba
  #############################################################################
 
     ############################################################################
-    # Memory Buffer MBA CAL FIR
+    # Centaur chip MBA target MBACALFIR
     ############################################################################
 
     register MBACALFIR
     {
-        name        "Memory Buffer MBA CAL FIR";
+        name        "Centaur chip MBA target MBACALFIR";
         scomaddr    0x03010400;
         reset       (&, 0x03010401);
         mask        (|, 0x03010405);
@@ -58,14 +58,14 @@ chip cen_mba
 
     register MBACALFIR_MASK
     {
-        name        "Memory Buffer MBA CAL FIR MASK";
+        name        "Centaur chip MBA target MBACALFIR MASK";
         scomaddr    0x03010403;
         capture     group default;
     };
 
     register MBACALFIR_ACT0
     {
-        name        "Memory Buffer MBA CAL FIR ACT0";
+        name        "Centaur chip MBA target MBACALFIR ACT0";
         scomaddr    0x03010406;
         capture     group default;
         capture     req nonzero("MBACALFIR");
@@ -73,33 +73,33 @@ chip cen_mba
 
     register MBACALFIR_ACT1
     {
-        name        "Memory Buffer MBA CAL FIR ACT1";
+        name        "Centaur chip MBA target MBACALFIR ACT1";
         scomaddr    0x03010407;
         capture     group default;
         capture     req nonzero("MBACALFIR");
     };
 
     ############################################################################
-    # Memory Buffer MBA SECURE FIR
+    # Centaur chip MBA target MBASECUREFIR
     ############################################################################
 
     # This register is hardwired to channel failure (checkstop) and we cannot
     # mask or change the state of the action registers.
     register MBASECUREFIR
     {
-        name        "Memory Buffer MBA SECURE FIR";
+        name        "Centaur chip MBA target MBASECUREFIR";
         scomaddr    0x0301041b;
         reset       (&, 0x0301041c);
         capture     group default;
     };
 
     ############################################################################
-    # Memory Buffer MBA FIR
+    # Centaur chip MBA target MBAFIR
     ############################################################################
 
     register MBAFIR
     {
-        name        "Memory Buffer MBA FIR";
+        name        "Centaur chip MBA target MBAFIR";
         scomaddr    0x03010600;
         reset       (&, 0x03010601);
         mask        (|, 0x03010605);
@@ -108,14 +108,14 @@ chip cen_mba
 
     register MBAFIR_MASK
     {
-        name        "Memory Buffer MBA FIR MASK";
+        name        "Centaur chip MBA target MBAFIR MASK";
         scomaddr    0x03010603;
         capture     group default;
     };
 
     register MBAFIR_ACT0
     {
-        name        "Memory Buffer MBA FIR ACT0";
+        name        "Centaur chip MBA target MBAFIR ACT0";
         scomaddr    0x03010606;
         capture     group default;
         capture     req nonzero("MBAFIR");
@@ -123,19 +123,19 @@ chip cen_mba
 
     register MBAFIR_ACT1
     {
-        name        "Memory Buffer MBA FIR ACT1";
+        name        "Centaur chip MBA target MBAFIR ACT1";
         scomaddr    0x03010607;
         capture     group default;
         capture     req nonzero("MBAFIR");
     };
 
     ############################################################################
-    # Memory Buffer MBA SPA register
+    # Centaur chip MBA target MBASPA
     ############################################################################
 
     register MBASPA
     {
-        name        "Memory Buffer MBA SPA register";
+        name        "Centaur chip MBA target MBASPA";
         scomaddr    0x03010611;
         reset       (&, 0x03010612);
         mask        (|, 0x03010614);
@@ -144,18 +144,18 @@ chip cen_mba
 
     register MBASPA_MASK
     {
-        name        "Memory Buffer MBA SPA register MASK";
+        name        "Centaur chip MBA target MBASPA MASK";
         scomaddr    0x03010614;
         capture     group default;
     };
 
     ############################################################################
-    # Memory Buffer MBA DDR PHY FIR
+    # Centaur chip MBA target MBADDRPHYFIR
     ############################################################################
 
     register MBADDRPHYFIR
     {
-        name        "Memory Buffer MBA DDR PHY FIR";
+        name        "Centaur chip MBA target MBADDRPHYFIR";
         scomaddr    0x800200900301143F;
         reset       (&, 0x800200910301143F);
         mask        (|, 0x800200950301143F);
@@ -164,14 +164,14 @@ chip cen_mba
 
     register MBADDRPHYFIR_MASK
     {
-        name        "Memory Buffer MBA DDR PHY FIR MASK";
+        name        "Centaur chip MBA target MBADDRPHYFIR MASK";
         scomaddr    0x800200930301143F;
         capture     group default;
     };
 
     register MBADDRPHYFIR_ACT0
     {
-        name        "Memory Buffer MBA DDR PHY FIR ACT0";
+        name        "Centaur chip MBA target MBADDRPHYFIR ACT0";
         scomaddr    0x800200960301143F;
         capture     group default;
         capture     req nonzero("MBADDRPHYFIR");
@@ -179,7 +179,7 @@ chip cen_mba
 
     register MBADDRPHYFIR_ACT1
     {
-        name        "Memory Buffer MBA DDR PHY FIR ACT1";
+        name        "Centaur chip MBA target MBADDRPHYFIR ACT1";
         scomaddr    0x800200970301143F;
         capture     group default;
         capture     req nonzero("MBADDRPHYFIR");
@@ -233,7 +233,7 @@ group gMBA attntype UNIT_CS, RECOVERABLE, HOST_ATTN filter singlebit
 };
 
 ################################################################################
-# Memory Buffer MBA CAL FIR
+# Centaur chip MBA target MBACALFIR
 ################################################################################
 
 rule rMBACALFIR
@@ -244,27 +244,27 @@ rule rMBACALFIR
     MBACALFIR & ~MBACALFIR_MASK & ~MBACALFIR_ACT0 &  MBACALFIR_ACT1;
 };
 
-group gMBACALFIR filter singlebit
+group gMBACALFIR filter singlebit, cs_root_cause
 {
     /** MBACALFIR[0]
      *  MBA_RECOVERABLE_ERROR
      */
-    (rMBACALFIR, bit(0)) ? TBDDefaultCallout;
+    (rMBACALFIR, bit(0)) ? self_th_1;
 
     /** MBACALFIR[1]
      *  MBA_NONRECOVERABLE_ERROR
      */
-    (rMBACALFIR, bit(1)) ? TBDDefaultCallout;
+    (rMBACALFIR, bit(1)) ? self_th_1;
 
     /** MBACALFIR[2]
      *  REFRESH_OVERRUN
      */
-    (rMBACALFIR, bit(2)) ? TBDDefaultCallout;
+    (rMBACALFIR, bit(2)) ? self_th_1;
 
     /** MBACALFIR[3]
      *  WAT_ERROR
      */
-    (rMBACALFIR, bit(3)) ? TBDDefaultCallout;
+    (rMBACALFIR, bit(3)) ? defaultMaskedError;
 
     /** MBACALFIR[4]
      *  RCD parity error on port 0
@@ -274,12 +274,12 @@ group gMBACALFIR filter singlebit
     /** MBACALFIR[5]
      *  DDR0_CAL_TIMEOUT_ERR
      */
-    (rMBACALFIR, bit(5)) ? TBDDefaultCallout;
+    (rMBACALFIR, bit(5)) ? self_th_1;
 
     /** MBACALFIR[6]
      *  DDR1_CAL_TIMEOUT_ERR
      */
-    (rMBACALFIR, bit(6)) ? TBDDefaultCallout;
+    (rMBACALFIR, bit(6)) ? self_th_1;
 
     /** MBACALFIR[7]
      *  RCD parity error on port 1
@@ -289,97 +289,97 @@ group gMBACALFIR filter singlebit
     /** MBACALFIR[8]
      *  MBX_TO_MBA_PAR_ERROR
      */
-    (rMBACALFIR, bit(8)) ? TBDDefaultCallout;
+    (rMBACALFIR, bit(8)) ? self_th_1;
 
     /** MBACALFIR[9]
      *  MBA_WRD_UE
      */
-    (rMBACALFIR, bit(9)) ? TBDDefaultCallout;
+    (rMBACALFIR, bit(9)) ? self_th_1;
 
     /** MBACALFIR[10]
      *  MBA_WRD_CE
      */
-    (rMBACALFIR, bit(10)) ? TBDDefaultCallout;
+    (rMBACALFIR, bit(10)) ? threshold_and_mask_self;
 
     /** MBACALFIR[11]
      *  MBA_MAINT_UE
      */
-    (rMBACALFIR, bit(11)) ? TBDDefaultCallout;
+    (rMBACALFIR, bit(11)) ? self_th_1;
 
     /** MBACALFIR[12]
      *  MBA_MAINT_CE
      */
-    (rMBACALFIR, bit(12)) ? TBDDefaultCallout;
+    (rMBACALFIR, bit(12)) ? self_th_32perDay;
 
     /** MBACALFIR[13]
      *  DDR_CAL_RESET_TIMEOUT
      */
-    (rMBACALFIR, bit(13)) ? TBDDefaultCallout;
+    (rMBACALFIR, bit(13)) ? self_th_1;
 
     /** MBACALFIR[14]
      *  WRQ_DATA_CE
      */
-    (rMBACALFIR, bit(14)) ? TBDDefaultCallout;
+    (rMBACALFIR, bit(14)) ? threshold_and_mask_self;
 
     /** MBACALFIR[15]
      *  WRQ_DATA_UE
      */
-    (rMBACALFIR, bit(15)) ? TBDDefaultCallout;
+    (rMBACALFIR, bit(15)) ? self_th_1;
 
     /** MBACALFIR[16]
      *  WRQ_DATA_SUE
      */
-    (rMBACALFIR, bit(16)) ? TBDDefaultCallout;
+    (rMBACALFIR, bit(16)) ? defaultMaskedError;
 
     /** MBACALFIR[17]
      *  WRQ_RRQ_HANG_ERR
      */
-    (rMBACALFIR, bit(17)) ? TBDDefaultCallout;
+    (rMBACALFIR, bit(17)) ? self_th_1;
 
     /** MBACALFIR[18]
      *  SM_1HOT_ERR
      */
-    (rMBACALFIR, bit(18)) ? TBDDefaultCallout;
+    (rMBACALFIR, bit(18)) ? self_th_1;
 
     /** MBACALFIR[19]
      *  WRD_SCOM_ERROR
      */
-    (rMBACALFIR, bit(19)) ? TBDDefaultCallout;
+    (rMBACALFIR, bit(19)) ? threshold_and_mask_self;
 
     /** MBACALFIR[20]
-     *  SCOM FIR error
+     *  RHMR_PRIM_REACHED_MAX
      */
-    (rMBACALFIR, bit(20)) ? TBDDefaultCallout; # DD1 action, masked for DD2+
+    (rMBACALFIR, bit(20)) ? defaultMaskedError;
 
     /** MBACALFIR[21]
-     *  SCOM FIR error clone
+     *  RHMR_SEC_REACHED_MAX
      */
-    (rMBACALFIR, bit(21)) ? TBDDefaultCallout; # DD1 action, masked for DD2+
+    (rMBACALFIR, bit(21)) ? defaultMaskedError;
 
     /** MBACALFIR[22]
      *  RHMR_SEC_ALREADY_FULL
      */
-    (rMBACALFIR, bit(22)) ? TBDDefaultCallout; # DD2+ only
+    (rMBACALFIR, bit(22)) ? defaultMaskedError;
 
     /** MBACALFIR[23]
      *  Reserved
      */
-    (rMBACALFIR, bit(23)) ? TBDDefaultCallout; # DD2+ only
+    (rMBACALFIR, bit(23)) ? defaultMaskedError;
 
     /** MBACALFIR[24]
      *  SCOM FIR error
      */
-    (rMBACALFIR, bit(24)) ? TBDDefaultCallout; # DD2+ only
+    (rMBACALFIR, bit(24)) ? threshold_and_mask_self;
 
     /** MBACALFIR[25]
      *  SCOM FIR error clone
      */
-    (rMBACALFIR, bit(25)) ? TBDDefaultCallout; # DD2+ only
+    (rMBACALFIR, bit(25)) ? threshold_and_mask_self;
 
 };
 
 ################################################################################
-# Memory Buffer MBA SECURE FIR
+# Centaur chip MBA target MBASECUREFIR
 ################################################################################
 
 rule rMBASECUREFIR
@@ -388,42 +388,42 @@ rule rMBASECUREFIR
     MBASECUREFIR;
 };
 
-group gMBASECUREFIR filter singlebit
+group gMBASECUREFIR filter singlebit, cs_root_cause( 0, 1, 2, 3, 4, 5 )
 {
     /** MBASECUREFIR[0]
-     *  INVALID_MBA_CAL0Q_ACCESS
+     *  Invalid MBA_CALQ0 access
      */
-    (rMBASECUREFIR, bit(0)) ? TBDDefaultCallout;
+    (rMBASECUREFIR, bit(0)) ? level2_th_1_UERE;
 
     /** MBASECUREFIR[1]
-     *  INVALID_MBA_CAL1Q_ACCESS
+     *  Invalid MBA_CALQ1 access
      */
-    (rMBASECUREFIR, bit(1)) ? TBDDefaultCallout;
+    (rMBASECUREFIR, bit(1)) ? level2_th_1_UERE;
 
     /** MBASECUREFIR[2]
-     *  INVALID_MBA_CAL2Q_ACCESS
+     *  Invalid MBA_CAL2Q access
      */
-    (rMBASECUREFIR, bit(2)) ? TBDDefaultCallout;
+    (rMBASECUREFIR, bit(2)) ? level2_th_1_UERE;
 
     /** MBASECUREFIR[3]
-     *  INVALID_MBA_CAL3Q_ACCESS
+     *  Invalid MBA_CAL3Q access
      */
-    (rMBASECUREFIR, bit(3)) ? TBDDefaultCallout;
+    (rMBASECUREFIR, bit(3)) ? level2_th_1_UERE;
 
     /** MBASECUREFIR[4]
-     *  INVALID_DDR_CONFIG_REG_ACCESS
+     *  Invalid DDR config reg access
      */
-    (rMBASECUREFIR, bit(4)) ? TBDDefaultCallout;
+    (rMBASECUREFIR, bit(4)) ? level2_th_1_UERE;
 
     /** MBASECUREFIR[5]
-     *  INVALID_SIR_MASK_OR_ACTION_REGISTER_ACCESS
+     *  Invalid SIR mask or action reg access
      */
-    (rMBASECUREFIR, bit(5)) ? TBDDefaultCallout;
+    (rMBASECUREFIR, bit(5)) ? level2_th_1_UERE;
 
 };
 
 ################################################################################
-# Memory Buffer MBA FIR
+# Centaur chip MBA target MBAFIR
 ################################################################################
 
 rule rMBAFIR
@@ -434,72 +434,72 @@ rule rMBAFIR
     MBAFIR & ~MBAFIR_MASK & ~MBAFIR_ACT0 &  MBAFIR_ACT1;
 };
 
-group gMBAFIR filter singlebit
+group gMBAFIR filter singlebit, cs_root_cause( 3, 5, 6, 7, 8 )
 {
     /** MBAFIR[0]
      *  Invalid Maintenance Command
      */
-    (rMBAFIR, bit(0)) ? TBDDefaultCallout;
+    (rMBAFIR, bit(0)) ? defaultMaskedError;
 
     /** MBAFIR[1]
      *  Invalid Maintenance Address
      */
-    (rMBAFIR, bit(1)) ? TBDDefaultCallout;
+    (rMBAFIR, bit(1)) ? defaultMaskedError;
 
     /** MBAFIR[2]
      *  Multi-address Maintenance Cmd Timeout
      */
-    (rMBAFIR, bit(2)) ? TBDDefaultCallout;
+    (rMBAFIR, bit(2)) ? self_th_1;
 
     /** MBAFIR[3]
      *  Internal FSM parity error
      */
-    (rMBAFIR, bit(3)) ? TBDDefaultCallout;
+    (rMBAFIR, bit(3)) ? self_th_1;
 
     /** MBAFIR[4]
      *  MCBIST error
      */
-    (rMBAFIR, bit(4)) ? TBDDefaultCallout;
+    (rMBAFIR, bit(4)) ? defaultMaskedError;
 
     /** MBAFIR[5]
      *  SCOM command register parity error
      */
-    (rMBAFIR, bit(5)) ? TBDDefaultCallout;
+    (rMBAFIR, bit(5)) ? self_th_1;
 
     /** MBAFIR[6]
      *  Unrecoverable channel error
      */
-    (rMBAFIR, bit(6)) ? TBDDefaultCallout;
+    (rMBAFIR, bit(6)) ? self_th_1;
 
     /** MBAFIR[7]
      *  UE or CE Error in WRD caw2 data latches
      */
-    (rMBAFIR, bit(7)) ? TBDDefaultCallout;
+    (rMBAFIR, bit(7)) ? self_th_1;
 
     /** MBAFIR[8]
-     *  An illegal state transition in maintenance state machine
+     *  Illegal transition maint state machine
      */
-    (rMBAFIR, bit(8)) ? TBDDefaultCallout; # DD2+ only
+    (rMBAFIR, bit(8)) ? self_th_1;
 
     /** MBAFIR[9:14]
-     *  Reserved
+     *  RESERVED
      */
-    (rMBAFIR, bit(9|10|11|12|13|14)) ? TBDDefaultCallout;
+    (rMBAFIR, bit(9|10|11|12|13|14)) ? defaultMaskedError;
 
     /** MBAFIR[15]
-     *  SCOM FIR error
+     *  SCOM Internal Error
      */
-    (rMBAFIR, bit(15)) ? TBDDefaultCallout;
+    (rMBAFIR, bit(15)) ? threshold_and_mask_self;
 
     /** MBAFIR[16]
-     *  SCOM FIR error clone
+     *  SCOM Internal Error Copy
      */
-    (rMBAFIR, bit(16)) ? TBDDefaultCallout;
+    (rMBAFIR, bit(16)) ? threshold_and_mask_self;
 
 };
 
 ################################################################################
-# Memory Buffer MBA SPA register
+# Centaur chip MBA target MBASPA
 ################################################################################
 
 rule rMBASPA
@@ -508,7 +508,7 @@ rule rMBASPA
     MBASPA & ~MBASPA_MASK;
 };
 
-group gMBASPA filter singlebit
+group gMBASPA filter singlebit, cs_root_cause
 {
     /** MBASPA[0]
      *  Maintenance command complete
@@ -518,62 +518,57 @@ group gMBASPA filter singlebit
     /** MBASPA[1]
      *  Hard NCE ETE
      */
-    (rMBASPA, bit(1)) ? TBDDefaultCallout;
+    (rMBASPA, bit(1)) ? defaultMaskedError;
 
     /** MBASPA[2]
      *  Soft NCE ETE
      */
-    (rMBASPA, bit(2)) ? TBDDefaultCallout;
+    (rMBASPA, bit(2)) ? defaultMaskedError;
 
     /** MBASPA[3]
      *  Intermittent NCE ETE
      */
-    (rMBASPA, bit(3)) ? TBDDefaultCallout;
+    (rMBASPA, bit(3)) ? defaultMaskedError;
 
     /** MBASPA[4]
      *  Retry CE ETE
      */
-    (rMBASPA, bit(4)) ? TBDDefaultCallout;
+    (rMBASPA, bit(4)) ? defaultMaskedError;
 
     /** MBASPA[5]
-     *  Emergency throttle attention
+     *  Emergency throttle action detected
      */
-    (rMBASPA, bit(5)) ? TBDDefaultCallout;
+    (rMBASPA, bit(5)) ? defaultMaskedError;
 
     /** MBASPA[6]
      *  Firmware generated attention 0
      */
-    (rMBASPA, bit(6)) ? TBDDefaultCallout;
+    (rMBASPA, bit(6)) ? defaultMaskedError;
 
     /** MBASPA[7]
      *  Firmware generated attention 1
      */
-    (rMBASPA, bit(7)) ? TBDDefaultCallout;
+    (rMBASPA, bit(7)) ? defaultMaskedError;
 
     /** MBASPA[8]
-     *  Maintenance command complete
+     *  WAT debug attention
      */
-    # WORKAROUND: HW217608
-    # For Centaur DD1.0, the hardware team will utilize the WAT logic to look
-    # for a command complete and trigger this bit. Note that the HW will still
-    # trigger MBASPA[0], however, that bit should be masked for this
-    # workaround.
-    (rMBASPA, bit(8)) ? maintenance_command_complete; # DD1 only
+    (rMBASPA, bit(8)) ? defaultMaskedError;
 
     /** MBASPA[9]
      *  Spare
      */
-    (rMBASPA, bit(9)) ? TBDDefaultCallout;
+    (rMBASPA, bit(9)) ? defaultMaskedError;
 
     /** MBASPA[10]
      *  MCBIST done
      */
-    (rMBASPA, bit(10)) ? TBDDefaultCallout;
+    (rMBASPA, bit(10)) ? defaultMaskedError;
 
 };
 
 ################################################################################
-# Memory Buffer MBA DDR PHY FIR
+# Centaur chip MBA target MBADDRPHYFIR
 ################################################################################
 
 rule rMBADDRPHYFIR
@@ -584,67 +579,67 @@ rule rMBADDRPHYFIR
     MBADDRPHYFIR & ~MBADDRPHYFIR_MASK & ~MBADDRPHYFIR_ACT0 &  MBADDRPHYFIR_ACT1;
 };
 
-group gMBADDRPHYFIR filter singlebit
+group gMBADDRPHYFIR filter singlebit, cs_root_cause
 {
     /** MBADDRPHYFIR[48]
      *  FSM Error Checkstop
      */
-    (rMBADDRPHYFIR, bit(48)) ? TBDDefaultCallout;
+    (rMBADDRPHYFIR, bit(48)) ? self_th_1;
 
     /** MBADDRPHYFIR[49]
      *  Parity Error Checkstop
      */
-    (rMBADDRPHYFIR, bit(49)) ? TBDDefaultCallout;
+    (rMBADDRPHYFIR, bit(49)) ? self_th_1;
 
     /** MBADDRPHYFIR[50]
      *  Calibration Error RE
      */
-    (rMBADDRPHYFIR, bit(50)) ? TBDDefaultCallout;
+    (rMBADDRPHYFIR, bit(50)) ? defaultMaskedError;
 
     /** MBADDRPHYFIR[51]
      *  FSM Recoverable Error
      */
-    (rMBADDRPHYFIR, bit(51)) ? TBDDefaultCallout;
+    (rMBADDRPHYFIR, bit(51)) ? self_th_32perDay;
 
     /** MBADDRPHYFIR[52]
      *  Parity Recoverable Error
      */
-    (rMBADDRPHYFIR, bit(52)) ? TBDDefaultCallout;
+    (rMBADDRPHYFIR, bit(52)) ? self_th_32perDay;
 
     /** MBADDRPHYFIR[53]
      *  Parity Recoverable Error
      */
-    (rMBADDRPHYFIR, bit(53)) ? TBDDefaultCallout;
+    (rMBADDRPHYFIR, bit(53)) ? threshold_and_mask_self;
 
     /** MBADDRPHYFIR[54:55]
      *  Reserved
      */
-    (rMBADDRPHYFIR, bit(54|55)) ? TBDDefaultCallout;
+    (rMBADDRPHYFIR, bit(54|55)) ? defaultMaskedError;
 
     /** MBADDRPHYFIR[56]
      *  FSM Error Checkstop
      */
-    (rMBADDRPHYFIR, bit(56)) ? TBDDefaultCallout;
+    (rMBADDRPHYFIR, bit(56)) ? self_th_1;
 
     /** MBADDRPHYFIR[57]
      *  Parity Error Checkstop
      */
-    (rMBADDRPHYFIR, bit(57)) ? TBDDefaultCallout;
+    (rMBADDRPHYFIR, bit(57)) ? self_th_1;
 
     /** MBADDRPHYFIR[58]
      *  Calibration Error RE
      */
-    (rMBADDRPHYFIR, bit(58)) ? TBDDefaultCallout;
+    (rMBADDRPHYFIR, bit(58)) ? defaultMaskedError;
 
     /** MBADDRPHYFIR[59]
      *  FSM Recoverable Error
      */
-    (rMBADDRPHYFIR, bit(59)) ? TBDDefaultCallout;
+    (rMBADDRPHYFIR, bit(59)) ? self_th_32perDay;
 
     /** MBADDRPHYFIR[60]
      *  Parity Recoverable Error
      */
-    (rMBADDRPHYFIR, bit(60)) ? TBDDefaultCallout;
+    (rMBADDRPHYFIR, bit(60)) ? self_th_32perDay;
 
 };