Increment base memory address by node

Change-Id: I524a9814cfc9a2b0d831ab31f9ed63e008ffa304
CQ: SW236248
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7429
Tested-by: Jenkins Server
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

6 files changed, 41 insertions, 23 deletions

diff --git a/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.C b/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.C
index 739533493..962d097c8 100644
--- a/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.C
+++ b/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.C
@@ -361,7 +361,6 @@ void*    call_host_build_winkle( void    *io_pArgs )
     uint32_t    l_poreSize      =   0;
     void        *l_pRealMemBase = NULL;
     void* l_pVirtMemBase        = NULL;
-    uint64_t l_memBase   = VMM_HOMER_REGION_START_ADDR;
 
     ISTEP_ERROR::IStepError     l_StepError;
 
@@ -376,13 +375,21 @@ void*    call_host_build_winkle( void    *io_pArgs )
 
 
     do  {
+        // Get the node-offset for our instance by looking at the HRMOR
+        uint64_t l_memBase = cpu_spr_value(CPU_SPR_HRMOR);
+        // mask off the secureboot offset
+        l_memBase = 0xFFFFF00000000000 & l_memBase;
+
+        // Now offset up to our hardcoded region
+        l_memBase += VMM_HOMER_REGION_START_ADDR;
+
         //  Get a chunk of real memory big enough to store all the possible
         //  SLW images.
 
         assert(VMM_HOMER_REGION_SIZE <= THIRTYTWO_GB,
                "host_build_winkle: Unsupported HOMER Region size");
 
-        //If running Sapphire need to place this at the top of memory
+        //If running Sapphire need to place this at the top of memory instead
         if(is_sapphire_load())
         {
             l_memBase = get_top_mem_addr();
diff --git a/src/usr/hwpf/hwp/mc_config/mc_config.C b/src/usr/hwpf/hwp/mc_config/mc_config.C
index 9d05c062e..dad3fa964 100644
--- a/src/usr/hwpf/hwp/mc_config/mc_config.C
+++ b/src/usr/hwpf/hwp/mc_config/mc_config.C
@@ -324,7 +324,7 @@ errlHndl_t call_mss_eff_grouping()
     return l_err;
 }
 
-errlHndl_t call_opt_memmap()
+errlHndl_t call_opt_memmap( bool i_initBase )
 {
     errlHndl_t l_err = NULL;
 
@@ -348,8 +348,7 @@ errlHndl_t call_opt_memmap()
         l_fapi_procs.push_back(l_fapi_target);
     }
 
-    bool l_initProcMemBaseAttr = false;
-    FAPI_INVOKE_HWP(l_err, opt_memmap, l_fapi_procs, l_initProcMemBaseAttr);
+    FAPI_INVOKE_HWP(l_err, opt_memmap, l_fapi_procs, i_initBase);
 
     if ( l_err )
     {
@@ -436,30 +435,24 @@ void*    call_mss_eff_config( void *io_pArgs )
 
     if (l_StepError.isNull())
     {
-        TARGETING::TargetHandleList l_procs;
-        getAllChips(l_procs, TYPE_PROC);
-
-        for (TARGETING::TargetHandleList::const_iterator
-           l_iter = l_procs.begin(); l_iter != l_procs.end(); ++l_iter)
-        {
-            TARGETING::Target*  l_target = *l_iter;
-
-            uint64_t l_base = 0;
-            l_target->setAttr<ATTR_MEM_BASE>( l_base  );
-
-            l_base = 0x0002000000000000UL; // 512TB
-            l_target->setAttr<ATTR_MIRROR_BASE>( l_base );
-        }
-
-        l_err = call_mss_eff_grouping();
+        // Flush out BASE attributes to starting values
+        l_err = call_opt_memmap(true);
 
         if (!l_err)
         {
-            l_err = call_opt_memmap();
+            // Stack the memory on each chip
+            l_err = call_mss_eff_grouping();
 
             if (!l_err)
             {
-                l_err = call_mss_eff_grouping();
+                // Move the BASES around to the real final values
+                l_err = call_opt_memmap(false);
+
+                if (!l_err)
+                {
+                    // Stack the memory again based on system-wide positions
+                    l_err = call_mss_eff_grouping();
+                }
             }
         }
 
diff --git a/src/usr/targeting/common/genHwsvMrwXml.pl b/src/usr/targeting/common/genHwsvMrwXml.pl
index 832f1219d..1ef3a2827 100755
--- a/src/usr/targeting/common/genHwsvMrwXml.pl
+++ b/src/usr/targeting/common/genHwsvMrwXml.pl
@@ -118,6 +118,14 @@ my @systemAttr; # Repeated {ATTR, VAL, ATTR, VAL, ATTR, VAL...}
 # Setting ALL_MCS_IN_INTERLEAVING_GROUP to zero. Need to replace with:
 # $reqPol->{'all_mcs_in_interleaving_group"}
 
+#No mirroring supported yet so the policy is just based on multi-node or not
+my $placement = 0x0; #NORMAL
+if ($sysname eq "brazos")
+{
+    $placement = 0x3; #DRAWER
+}
+
+
 push @systemAttr,
 [
     "FREQ_PROC_REFCLOCK", $reqPol->{'processor-refclock-frequency'}->{content},
@@ -174,6 +182,7 @@ push @systemAttr,
     "PROC_R_LOADLINE_VCS", $reqPol->{'proc_r_loadline_vcs'},
     "PROC_R_DISTLOSS_VCS", $reqPol->{'proc_r_distloss_vcs'},
     "PROC_VRM_VOFFSET_VCS", $reqPol->{'proc_vrm_voffset_vcs'},
+    "MEM_MIRROR_PLACEMENT_POLICY", $placement,
 ];
 
 #------------------------------------------------------------------------------
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index b3aa6f2e7..1e93a4b1d 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -11397,6 +11397,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
         NORMAL  = non-mirrored start: 0, mirrored start: 512TB
         FLIPPED = mirrored start: 0, non-mirrored start: 512TB
         SELECTIVE = non-mirrored/mirrored start (interleaved): 0
+        DRAWER = non-mirrored start: 1TB*drawer, mirrored start: 512TB+(1TB*drawer/2)
     </description>
     <simpleType>
       <uint8_t>
diff --git a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
index bd7ba6a90..528dfc8a9 100644
--- a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
@@ -231,6 +231,10 @@
         <id>PROC_VRM_VOFFSET_VCS</id>
         <default>0</default>
     </attribute>
+    <attribute>
+        <id>MEM_MIRROR_PLACEMENT_POLICY</id>
+        <default>0</default><!-- NORMAL -->
+    </attribute>
     <!-- End System Attributes from MRW -->
     <attribute>
         <id>ISTEP_MODE</id>
diff --git a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml
index b782f8c8e..1fd97bc16 100644
--- a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml
@@ -227,6 +227,10 @@
         <id>PROC_VRM_VOFFSET_VCS</id>
         <default>0</default>
     </attribute>
+    <attribute>
+        <id>MEM_MIRROR_PLACEMENT_POLICY</id>
+        <default>0</default><!-- NORMAL -->
+    </attribute>
     <!-- End System Attributes from MRW -->
     <attribute>
         <id>ISTEP_MODE</id>