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authorRicardo Mata <ricmata@us.ibm.com>2018-04-12 11:16:28 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2018-04-16 23:35:41 -0400
commit6722b72b63af100493aed5b308300a559aaf5676 (patch)
treec6f252a8d69d02c56ce2650faae135a3e4d8d329
parent01e036e0a5a1f8009978501bf4ff472706868d5f (diff)
downloadtalos-hostboot-6722b72b63af100493aed5b308300a559aaf5676.tar.gz
talos-hostboot-6722b72b63af100493aed5b308300a559aaf5676.zip
Discovered a bug in how the IOVALIDs are set up for PEC2.
These changes reflects the fix for SW417485. Change-Id: I7f112caf6e578644ec30302884fb2719aa686bc0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57113 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57142 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C
index ac00d7e61..20ae258ca 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C
@@ -265,6 +265,7 @@ fapi2::ReturnCode p9_pcie_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C
if ((l_buf.getBit(PEC_IOP_IOVALID_ENABLE_STACK1_BIT)) || (l_buf.getBit(PEC_IOP_IOVALID_ENABLE_STACK2_BIT)))
{
l_buf.setBit<PEC_IOP_IOVALID_ENABLE_STACK0_BIT>();
+ l_buf.setBit<PEC_IOP_IOVALID_ENABLE_STACK1_BIT>();
}
FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
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