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| author | Joe McGill <jmcgill@us.ibm.com> | 2017-11-30 15:07:30 -0600 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-12-22 13:28:12 -0500 |
| commit | d65acc669a101f78eecf16e9a3f8d9bb373441c8 (patch) | |
| tree | bb951fceb73b3508a9b0f165327ccbc43367907a | |
| parent | 63167adf8994c5b89f5a52d0a1a81e84a91b7f1e (diff) | |
| download | talos-hostboot-d65acc669a101f78eecf16e9a3f8d9bb373441c8.tar.gz talos-hostboot-d65acc669a101f78eecf16e9a3f8d9bb373441c8.zip | |
checkstop on MCD UE when extended addressing mode is enabled
option2 workaround enables extended addressing mode -- based
on HW413218 the MCD UE FIR bit needs to trigger checkstop
option1 workaround disables the MCD -- for cleanliness
explicitly mask MCD FIR
Change-Id: Ie519e66f9518c5b73cb6cebac2cb7c150cc9917c
CQ: HW413218
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50243
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50289
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C index 819dea211..75d274b97 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C @@ -224,6 +224,22 @@ p9_setup_bars_mcd_enable( if (l_addr_extension_group_id || l_addr_extension_chip_id) { + // adjust FIR setup for HW413218 + l_fir_data = MCD_FIR_ACTION0; + l_fir_data.clearBit<PU_MCD1_MCD_FIR_MASK_REG_ARRAY_ECC_UE>(); + FAPI_TRY(fapi2::putScom(i_target, PU_MCD_FIR_ACTION0_REG, l_fir_data), + "Error from putScom (PU_MCD_FIR_ACTION0_REG)"); + FAPI_TRY(fapi2::putScom(i_target, PU_MCD1_MCD_FIR_ACTION0_REG, l_fir_data), + "Error from putScom (PU_MCD1_MCD_FIR_ACTION0_REG)"); + + l_fir_data = MCD_FIR_ACTION1; + l_fir_data.clearBit<PU_MCD1_MCD_FIR_MASK_REG_ARRAY_ECC_UE>(); + FAPI_TRY(fapi2::putScom(i_target, PU_MCD_FIR_ACTION1_REG, l_fir_data), + "Error from putScom (PU_MCD_FIR_ACTION1_REG)"); + FAPI_TRY(fapi2::putScom(i_target, PU_MCD1_MCD_FIR_ACTION1_REG, l_fir_data), + "Error from putScom (PU_MCD1_MCD_FIR_ACTION1_REG)"); + + // setup extended addressing l_mcd_vgc_data.setBit<P9N2_PU_BANK0_MCD_VGC_EXT_ADDR_FAC_ENABLE>(); l_mcd_vgc_data.insertFromRight<P9N2_PU_BANK0_MCD_VGC_EXT_ADDR_FAC_MASK, P9N2_PU_BANK0_MCD_VGC_EXT_ADDR_FAC_MASK_LEN>((l_addr_extension_group_id << 3) | @@ -1267,6 +1283,16 @@ p9_setup_bars(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) "Error from p9_setup_bars_mcd"); } } + else + { + // mask MCD FIRs + fapi2::buffer<uint64_t> l_fir_data; + l_fir_data.flush<1>(); + FAPI_TRY(fapi2::putScom(i_target, PU_MCD_FIR_MASK_REG, l_fir_data), + "Error from putScom (PU_MCD_FIR_MASK_REG)"); + FAPI_TRY(fapi2::putScom(i_target, PU_MCD1_MCD_FIR_MASK_REG, l_fir_data), + "Error from putScom (PU_MCD1_MCD_FIR_MASK_REG)"); + } // INT FAPI_TRY(p9_setup_bars_int(i_target, FAPI_SYSTEM, l_chip_info), |
