Set Centaur L4 Cache state correctly

Change-Id: Iebc3c9fd42ef0a3852f7df6d380089d182531359
CQ: SW209633
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5137
Tested-by: Jenkins Server
Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
Reviewed-by: Donald E. Dahle <dedahle@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

6 files changed, 285 insertions, 125 deletions

diff --git a/src/build/debug/Hostboot/HwpfAttrOverride.pm b/src/build/debug/Hostboot/HwpfAttrOverride.pm
index daff19f5b..7ab2f25d3 100755
--- a/src/build/debug/Hostboot/HwpfAttrOverride.pm
+++ b/src/build/debug/Hostboot/HwpfAttrOverride.pm
@@ -629,7 +629,7 @@ sub main
             #     uint32_t iv_valSize;    // Size of the attribute value in bytes
             # };
             my $addr = $overrideHeaderAddr;
-            ::write32($addr, $attrIdVal);
+            ::write32($addr, hex $attrIdVal);
             $addr += 4;
             ::write32($addr, $targType);
             $addr += 4;
diff --git a/src/include/usr/hwpf/istepreasoncodes.H b/src/include/usr/hwpf/istepreasoncodes.H
index 5461dba6a..dc36f7e94 100644
--- a/src/include/usr/hwpf/istepreasoncodes.H
+++ b/src/include/usr/hwpf/istepreasoncodes.H
@@ -178,6 +178,7 @@ enum istepReasonCode
     ISTEP_PROC_GETECID_FAILED                   = ISTEP_COMP_ID | 0x2F,
     ISTEP_TOP_LEVEL_TARGET_NULL                 = ISTEP_COMP_ID | 0x30,
     ISTEP_DECONFIGURE_MBA_FAILED                = ISTEP_COMP_ID | 0x31,
+    ISTEP_DECONFIGURE_L4_FAILED                 = ISTEP_COMP_ID | 0x32,
 };  // end ISTEP
 
 }
diff --git a/src/usr/hwpf/hwp/centaur_ec_attributes.xml b/src/usr/hwpf/hwp/centaur_ec_attributes.xml
index 882f3d03b..fb99b1eb2 100644
--- a/src/usr/hwpf/hwp/centaur_ec_attributes.xml
+++ b/src/usr/hwpf/hwp/centaur_ec_attributes.xml
@@ -22,6 +22,7 @@
 <!-- IBM_PROLOG_END_TAG                                                     -->
 <attributes>
 <!-- ********************************************************************* -->
+  <!-- $Id: centaur_ec_attributes.xml,v 1.5 2013/06/18 22:04:09 mjjones Exp $ -->
   <attribute>
     <id>ATTR_CENTAUR_EC_WRITE_FIR_MASK_FEATURE</id>
     <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
@@ -40,7 +41,7 @@
     </chipEcFeature>
   </attribute>
 
- <attribute>
+  <attribute>
     <id>ATTR_CENTAUR_EC_MSS_CONTINUE_ON_DP18_PLL_LOCK_FAIL</id>
     <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>
@@ -57,10 +58,13 @@ Controls the ddr_phy_reset procedure.  When set to TRUE, the procedure will cont
     </chipEcFeature>
   </attribute>
 
-<attribute>
+  <attribute>
     <id>ATTR_CENTAUR_EC_MSS_READ_PHASE_SELECT_RESET</id>
     <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
-    <description>Set by the platform depending on DD1 vs DD2.  If true, then training and periodic training needs to make adjustments to the read phase select.  In DD2, we expect this to be fixed.</description>
+    <description>
+      If true, then training and periodic training needs to make adjustments to the read phase select.
+      In DD2, this is expected to be fixed.
+    </description>
     <chipEcFeature>
       <chip>
         <name>ENUM_ATTR_NAME_CENTAUR</name>
@@ -70,6 +74,26 @@ Controls the ddr_phy_reset procedure.  When set to TRUE, the procedure will cont
         </ec>
       </chip>
     </chipEcFeature>
-</attribute>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CENTAUR_EC_CHECK_L4_CACHE_ENABLE_UNKNOWN</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+      If true then mss_get_cen_ecid needs to read an ECBIT from the ECID in
+      order to determine if the L4 Cache Enable data in the ECID is in an
+      unknown state.
+      This is true for Centaur 1.*
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
 
 </attributes>
diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_training.C b/src/usr/hwpf/hwp/dmi_training/dmi_training.C
index 409f8ad65..16d7e6298 100644
--- a/src/usr/hwpf/hwp/dmi_training/dmi_training.C
+++ b/src/usr/hwpf/hwp/dmi_training/dmi_training.C
@@ -255,49 +255,104 @@ void*    call_mss_getecid( void *io_pArgs )
             // - fapi::ENUM_ATTR_MSS_CACHE_ENABLE_ON
             // - fapi::ENUM_ATTR_MSS_CACHE_ENABLE_HALF_A
             // - fapi::ENUM_ATTR_MSS_CACHE_ENABLE_HALF_B
-            // Firmware does not support HALF-enabled, it is treated like OFF.
-            // If the L4 cache is not ON then the L4 Target is deconfigured.
-            // The ATTR_MSS_CACHE_ENABLE attribute is set to either ON/OFF
-
-            // TODO SW209633
-            // This will provide a new version of mss_get_cen_ecid that will
-            // potentially report some different cache status values. For all
-            // values, if the value is not ON then firmware will treat the cache
-            // as OFF. Until the new mss_get_cen_ecid is available always treat
-            // the cache as OFF to workaround a problem in manufacturing. As
-            // part of SW209633, uncomment the following line.
-            //if (l_cache_enable != fapi::ENUM_ATTR_MSS_CACHE_ENABLE_ON)
+            // - fapi::ENUM_ATTR_MSS_CACHE_ENABLE_UNK_OFF
+            // - fapi::ENUM_ATTR_MSS_CACHE_ENABLE_UNK_ON
+            // - fapi::ENUM_ATTR_MSS_CACHE_ENABLE_UNK_HALF_A
+            // - fapi::ENUM_ATTR_MSS_CACHE_ENABLE_UNK_HALF_B
+            // The UNK values are for DD1.* Centaur chips where the fuses were
+            // not blown correctly so the cache may not be in the correct state.
+            //
+            // Firmware does not normally support HALF enabled
+            // If ON then ATTR_MSS_CACHE_ENABLE is set to ON
+            // Else ATTR_MSS_CACHE_ENABLE is set to OFF and the L4 Target is
+            //   deconfigured
+            //
+            // However, an engineer can override ATTR_MSS_CACHE_ENABLE. If they
+            // override it to HALF_A or HALF_B then
+            // - ATTR_MSS_CACHE_ENABLE is set to HALF_X
+            // - The L4 Target is not deconfigured
+            if (l_cache_enable != fapi::ENUM_ATTR_MSS_CACHE_ENABLE_ON)
             {
                 TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                    "mss_get_cen_ecid returned L4 not-on (0x%02x)",
+                    "call_mss_getecid: mss_get_cen_ecid returned L4 not-on (0x%02x)",
                     l_cache_enable);
                 l_cache_enable = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_OFF;
+            }
+
+            // Set the ATTR_MSS_CACHE_ENABLE attribute
+            l_pCentaur->setAttr<TARGETING::ATTR_MSS_CACHE_ENABLE>(
+                l_cache_enable);
 
+            // Read the ATTR_MSS_CACHE_ENABLE back to pick up any override
+            uint8_t l_cache_enable_attr =
+                l_pCentaur->getAttr<TARGETING::ATTR_MSS_CACHE_ENABLE>();
+
+            if (l_cache_enable != l_cache_enable_attr)
+            {
+                TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                    "call_mss_getecid: ATTR_MSS_CACHE_ENABLE override (0x%02x)",
+                    l_cache_enable_attr);
+            }
+
+            // At this point HALF_A/HALF_B are only possible due to override
+            if ((l_cache_enable_attr !=
+                 fapi::ENUM_ATTR_MSS_CACHE_ENABLE_ON) &&
+                (l_cache_enable_attr !=
+                 fapi::ENUM_ATTR_MSS_CACHE_ENABLE_HALF_A) &&
+                (l_cache_enable_attr !=
+                 fapi::ENUM_ATTR_MSS_CACHE_ENABLE_HALF_B))
+            {
+                // Deconfigure the L4 Cache Targets (there should be 1)
                 TargetHandleList l_list;
-                getChildChiplets(l_list,
-                                 l_pCentaur,
-                                 TYPE_L4, false );
+                getChildChiplets(l_list, l_pCentaur, TYPE_L4, false);
 
                 TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                        "deconfigure %d -  L4s assocated with this centaur "
-                        "huid = 0x%.8X", l_list.size(), get_huid(l_pCentaur));
+                    "call_mss_getecid: deconfiguring %d L4s (Centaur huid: 0x%.8X)",
+                    l_list.size(), get_huid(l_pCentaur));
 
                 for (TargetHandleList::const_iterator
                         l_l4_iter = l_list.begin();
                         l_l4_iter != l_list.end();
                         ++l_l4_iter)
                 {
-                        TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                                "deconfigure L4 0x%.8X", get_huid( *l_l4_iter));
+                    TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                        "call_mss_getecid: deconfiguring L4 (huid: 0x%.8X)",
+                        get_huid( *l_l4_iter));
 
-                    // call HWAS to deconfigure
                     l_err = HWAS::theDeconfigGard().
-                                        deconfigureTarget( **l_l4_iter , 0);
+                        deconfigureTarget(**l_l4_iter , 0);
+
+                    if (l_err)
+                    {
+                        TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                                  "ERROR: error deconfiguring Centaur L4");
+
+                        /*@
+                         * @errortype
+                         * @reasoncode  ISTEP_DECONFIGURE_L4_FAILED
+                         * @severity    ERRORLOG::ERRL_SEV_UNRECOVERABLE
+                         * @moduleid    ISTEP_MSS_GETECID
+                         * @userdata1   bytes 0-1: plid identifying first error
+                         *              bytes 2-3: reason code of first error
+                         * @userdata2   bytes 0-1: total number of elogs included
+                         *              bytes 2-3: N/A
+                         * @devdesc     call to deconfigure Centaur L4 failed
+                         *              see error log in the user details section for
+                         *              additional details.
+                         */
+                        l_StepError.addErrorDetails(ISTEP_DECONFIGURE_L4_FAILED,
+                                                    ISTEP_MSS_GETECID,
+                                                    l_err);
+                        errlCommit(l_err, HWPF_COMP_ID);
+                        break;
+                    }
                 }
             }
-
-            l_pCentaur->setAttr<TARGETING::ATTR_MSS_CACHE_ENABLE>(
-                                                                l_cache_enable);
+            else
+            {
+                TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                    "call_mss_getecid: Centaur L4 good, not deconfiguring");
+            }
         }
 
         TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
diff --git a/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.C b/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.C
index 0383e9eb9..ad7c9398a 100644
--- a/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.C
+++ b/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_get_cen_ecid.C,v 1.18 2013/03/27 13:20:55 bellows Exp $
+// $Id: mss_get_cen_ecid.C,v 1.22 2013/06/18 22:03:57 mjjones Exp $
 //------------------------------------------------------------------------------
 // *|
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -39,6 +39,9 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//   1.21  | bellows  |14-JUN-13| ECBIT added for case when we can trust the cache enable
+//   1.20  | bellows  |22-MAY-13| Bluewaterfall matching actual ECID definition
+//   1.19  | bellows  |15-MAY-13| Added Bluewaterfall handling
 //   1.18  | bellows  |27-MAR-13| Fixes to rc handling from reviewer comments
 //   1.17  | bellows  |26-MAR-13| Additional reviewer comments
 //   1.16  | bellows  |26-MAR-13| Cleanup because of Firmware Gerrit Review Comments
@@ -77,130 +80,207 @@ fapi::ReturnCode mss_get_cen_ecid(
     )
 {
     // return code
-    fapi::ReturnCode rc;
-    uint64_t data[2];
-    uint32_t rc_ecmd;
+  fapi::ReturnCode rc;
+  uint64_t data[2];
+  uint32_t rc_ecmd;
     // mark HWP entry
 
-    ecmdDataBufferBase scom(64);
-    FAPI_IMP("Entering mss_get_cen_ecid....");
-    rc = fapiGetScom( i_target, ECID_PART_0_0x00010000, scom );
-    if (rc)
-    {
-        FAPI_ERR("mss_get_cen_ecid: could not read scom address 0x00010000" );
-        return rc;
-    }
-    scom.reverse();
-    data[0] = scom.getDoubleWord(0);
+  ecmdDataBufferBase scom(64);
+  FAPI_IMP("Entering mss_get_cen_ecid....");
+  rc = fapiGetScom( i_target, ECID_PART_0_0x00010000, scom );
+  if (rc)
+  {
+    FAPI_ERR("mss_get_cen_ecid: could not read scom address 0x00010000" );
+    return rc;
+  }
+  scom.reverse();
+  data[0] = scom.getDoubleWord(0);
     //gets the second part of the ecid and sets the attribute
-    rc = fapiGetScom( i_target, ECID_PART_1_0x00010001, scom );
-    if (rc)
-    {
-        FAPI_ERR("mss_get_cen_ecid: could not read scom address 0x00010001" );
-        return rc;
-    }
-    scom.reverse();
-    data[1] = scom.getDoubleWord(0);
-    rc = FAPI_ATTR_SET(ATTR_ECID, &i_target, data);
-    if (rc)
-    {
-        FAPI_ERR("mss_get_cen_ecid: set ATTR_ECID" );
-        return rc;
-    }
+  rc = fapiGetScom( i_target, ECID_PART_1_0x00010001, scom );
+  if (rc)
+  {
+    FAPI_ERR("mss_get_cen_ecid: could not read scom address 0x00010001" );
+    return rc;
+  }
+  scom.reverse();
+  data[1] = scom.getDoubleWord(0);
+  rc = FAPI_ATTR_SET(ATTR_ECID, &i_target, data);
+  if (rc)
+  {
+    FAPI_ERR("mss_get_cen_ecid: set ATTR_ECID" );
+    return rc;
+  }
 
     //get bit128
-    uint8_t bit128=0;
-    rc_ecmd = scom.extract(&bit128,63,1);
-    bit128 = bit128 >> 7;
+  uint8_t bit128=0;
+  rc_ecmd = scom.extract(&bit128,63,1);
+  bit128 = bit128 >> 7;
+  if(rc_ecmd) {
+    FAPI_ERR("mss_get_cen_ecid: could not extract cache data_valid bit" );
+    rc.setEcmdError(rc_ecmd);
+    return rc;
+  }
+
+  if(bit128 == 1) { // Cache enable bit is valid
+
+    //gets bits 113 and 114 to determine the state of the cache
+    uint8_t bit113_114=0;
+    rc_ecmd = scom.extract(&bit113_114,48,2);
+    bit113_114 = bit113_114 >> 6;
+    uint8_t t;
     if(rc_ecmd) {
-      FAPI_ERR("mss_get_cen_ecid: could not extract cache data_valid bit" );
+      FAPI_ERR("mss_get_cen_ecid: could not extract cache data" );
       rc.setEcmdError(rc_ecmd);
       return rc;
     }
+    //determines the state of the cache
+    if(bit113_114 == 0) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_ON;
+    else if(bit113_114 == 1) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_HALF_A;
+    else if(bit113_114 == 2) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_HALF_B;
+    else t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_OFF;
 
-    if(bit128 == 1) { // Cache enable bit is valid
+    // Centaur DD1.X chips have an ECBIT in bit127, if this is zero then the
+    // cache enable bits are in an unknown state. DD2.X chips and higher do not
+    // have an ECBIT. The decision to look at the ECBIT is done with a Chip EC
+    // Feature Attribute - the attribute XML can be easily tweaked if it is
+    // found that other DD levels also have an ECBIT.
+    // Centaur | DataValid | ECBIT  | Return Value   | Firmware Action | Cronus Action**|
+    // 1.*     | 0         | 0 or 1 | DIS            | DIS             | DIS            |
+    // 1.*     | 1         | 0      | Unk ENA/DIS/A/B| DIS             | ENA/DIS/A/B    |
+    // 1.*     | 1         | 1      | ENA/DIS/A/B    | ENA/DIS*        | ENA/DIS/A/B    |
+    // != 1.*  | 0         | N/A    | DIS            | DIS             | DIS            |
+    // != 1.*  | 1         | N/A    | ENA/DIS/A/B    | ENA/DIS         | ENA/DIS/A/B    |
+    // 
+    // * firmware can suport paritial cache if it wants to for DD1.* (e.g. DD1.0 DD1.01, DD1.1 etc)
+    //    However, if it chooses to, it should still make all Unk ones disabled
+    // ** Cronus Action - cronus and all fapi procedures only support the original defintion of ENA/DIS/A/B
+    //    Cronus actually uses its config file for the 4 values and checks the hardware via the get_cen_ecid
+    //    procedure during step 11 to make sure the end user does not enable a disable cache
+    //    Under cronus, the Unk information is only printed to the screen
+    uint8_t l_checkL4CacheEnableUnknown = 0;
+    rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_CHECK_L4_CACHE_ENABLE_UNKNOWN,
+                       &i_target, l_checkL4CacheEnableUnknown);
+    if (!rc.ok()) {
+      FAPI_ERR("mss_get_cen_ecid: could not get CHECK_L4_CACHE_ENABLE_VALIDITY attr" );
+      return rc;
+    }
 
-    //gets bits 113 and 114 to determine the state of the cache
-      uint8_t bit113_114=0;
-      rc_ecmd = scom.extract(&bit113_114,48,2);
-      bit113_114 = bit113_114 >> 6;
-      uint8_t t;
+    if (l_checkL4CacheEnableUnknown)
+    {
+      uint8_t bit127 = 0;
+      rc_ecmd = scom.extract(&bit127,62,1);
+      bit127 = bit127 >> 7;
       if(rc_ecmd) {
-        FAPI_ERR("mss_get_cen_ecid: could not extract cache data" );
+        FAPI_ERR("mss_get_cen_ecid: could not extract ECBIT bit" );
         rc.setEcmdError(rc_ecmd);
         return rc;
       }
-    //determines the state of the cache
-      if(bit113_114 == 0) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_ON;
-      else if(bit113_114 == 1) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_HALF_A;
-      else if(bit113_114 == 2) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_HALF_B;
-      else t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_OFF;
-      o_cache_enable = t;
-    }
-    else {
-      FAPI_INF("Cache Dissbled because eDRAM data bits are assumed to be bad");
-      o_cache_enable = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_OFF;
+      if(bit127 == 0) {
+        FAPI_INF("mss_get_cen_ecid: Cache Enable Bits are in Unknown State");
+        if(bit113_114 == 0) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_UNK_ON;
+        else if(bit113_114 == 1) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_UNK_HALF_A;
+        else if(bit113_114 == 2) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_UNK_HALF_B;
+        else t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_UNK_OFF;
+      }
+      else
+      {
+        FAPI_INF("mss_get_cen_ecid: Cache Enable Bits are in Known State");
+      }
     }
 
+    o_cache_enable = t;
+  }
+  else {
+    FAPI_INF("Cache Disbled because eDRAM data bits are assumed to be bad");
+    o_cache_enable = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_OFF;
+  }
+
     //reads in the ECID info for whether a DDR port side is good or bad
-    rc_ecmd = scom.extract(&o_ddr_port_status,50,2);
-    o_ddr_port_status = o_ddr_port_status >> 6;
-    if(rc_ecmd) {
-       FAPI_ERR("mss_get_cen_ecid: could not extract DDR status data" );
-       rc.setEcmdError(rc_ecmd);
-       return rc;
-    }
+  rc_ecmd = scom.extract(&o_ddr_port_status,50,2);
+  o_ddr_port_status = o_ddr_port_status >> 6;
+  if(rc_ecmd) {
+    FAPI_ERR("mss_get_cen_ecid: could not extract DDR status data" );
+    rc.setEcmdError(rc_ecmd);
+    return rc;
+  }
 
      //116..123         average PSRO from 85C wafer test
-    uint8_t bit117_124=0;
-    rc_ecmd = scom.extract(&bit117_124,52,8);
-    if(rc_ecmd) {
-       FAPI_ERR("mss_get_cen_ecid: could not extract PSRO" );
-       rc.setEcmdError(rc_ecmd);
-       return rc;
-    }
-    rc = FAPI_ATTR_SET(ATTR_MSS_PSRO, &i_target, bit117_124);
-    if (!rc.ok()) {
-       FAPI_ERR("mss_get_cen_ecid: could not set ATTR_MSS_PSRO" );
-       return rc;
-    }
+  uint8_t bit117_124=0;
+  rc_ecmd = scom.extract(&bit117_124,52,8);
+  if(rc_ecmd) {
+    FAPI_ERR("mss_get_cen_ecid: could not extract PSRO" );
+    rc.setEcmdError(rc_ecmd);
+    return rc;
+  }
+  rc = FAPI_ATTR_SET(ATTR_MSS_PSRO, &i_target, bit117_124);
+  if (!rc.ok()) {
+    FAPI_ERR("mss_get_cen_ecid: could not set ATTR_MSS_PSRO" );
+    return rc;
+  }
 
     // read the bit in the ecid to see if we are a DD1.01
    // Bit 124 DD1.01  Indicator Bit. Set to '1' for DD1.01 devices
-    uint8_t bit125 =0;
-    rc_ecmd = scom.extract(&bit125,60,1);
-    bit125 = bit125 >> 7;
-    if(rc_ecmd) {
-       FAPI_ERR("mss_get_cen_ecid: could not extract dd1.01 indicator bit" );
-       rc.setEcmdError(rc_ecmd);
-       return rc;
-    }
-    o_centaur_sub_revision=bit125;
+  uint8_t bit125 =0;
+  rc_ecmd = scom.extract(&bit125,60,1);
+  bit125 = bit125 >> 7;
+  if(rc_ecmd) {
+    FAPI_ERR("mss_get_cen_ecid: could not extract dd1.01 indicator bit" );
+    rc.setEcmdError(rc_ecmd);
+    return rc;
+  }
+  o_centaur_sub_revision=bit125;
     // The ecid contains the chip's subrevision, changes in the subrevision should not
     // change firmware behavior but for the exceptions, update attributes to indicate
     // those behaviors
-    uint8_t ec;
-    uint8_t l_nwell_misplacement = 0;
-    rc = FAPI_ATTR_GET_PRIVILEGED(ATTR_EC, &i_target, ec);
-    if (!rc.ok()) {
-       FAPI_ERR("mss_get_cen_ecid: could not GET PRIVILEGED ATTR_EC" );
-       return rc;
-    }
-    if ((ec == 0x10) && (o_centaur_sub_revision < 1))
-    {
+  uint8_t ec;
+  uint8_t l_nwell_misplacement = 0;
+  rc = FAPI_ATTR_GET_PRIVILEGED(ATTR_EC, &i_target, ec);
+  if (!rc.ok()) {
+    FAPI_ERR("mss_get_cen_ecid: could not GET PRIVILEGED ATTR_EC" );
+    return rc;
+  }
+  if ((ec == 0x10) && (o_centaur_sub_revision < 1))
+  {
   // For DD1.00, the transistor misplaced in the nwell needs some setting adjustments to get it to function
   // after DD1.00, we no longer need to make that adjustment
-       l_nwell_misplacement = 1;
+    l_nwell_misplacement = 1;
+  }
+
+  uint8_t bit126 =0;
+  rc_ecmd = scom.extract(&bit126,61,1);
+  bit126 = bit126 >> 7;
+  if(rc_ecmd) {
+    FAPI_ERR("mss_get_cen_ecid: could not extract dd1.03 indicator bit" );
+    rc.setEcmdError(rc_ecmd);
+    return rc;
+  }
+  uint8_t l_bluewaterfall_broken = 0;
+  if (ec == 0x10) {
+    if(bit126 == 0)
+    {
+  // on and after DD1.03, we no longer need to make adjustments due to the bluewaterfall - this is before
+      l_bluewaterfall_broken = 1;
     }
-    rc = FAPI_ATTR_SET(ATTR_MSS_NWELL_MISPLACEMENT, &i_target, l_nwell_misplacement);
-    if (!rc.ok()) {
-       FAPI_ERR("mss_get_cen_ecid: could not set ATTR_MSS_NWELL_MISPLACEMENT" );
-       return rc;
+    else {
+      l_nwell_misplacement = 0; // Assume if the bluewaterfall is fixed, then the nwell is also fixed
     }
+  }
+  rc = FAPI_ATTR_SET(ATTR_MSS_BLUEWATERFALL_BROKEN, &i_target, l_bluewaterfall_broken);
+  if (!rc.ok()) {
+    FAPI_ERR("mss_get_cen_ecid: could not set ATTR_MSS_BLUEWATERFALL_BROKEN" );
+    return rc;
+  }
 
-   // mark HWP exit
-    FAPI_IMP("Exiting mss_get_cen_ecid....");
+  // we have to look at both the bluewaterfall and the n-well misplacement to determine the proper valuse of the n-well
+  rc = FAPI_ATTR_SET(ATTR_MSS_NWELL_MISPLACEMENT, &i_target, l_nwell_misplacement);
+  if (!rc.ok()) {
+    FAPI_ERR("mss_get_cen_ecid: could not set ATTR_MSS_NWELL_MISPLACEMENT" );
     return rc;
+  }
+
+   // mark HWP exit
+  FAPI_IMP("Exiting mss_get_cen_ecid....");
+  return rc;
 }
 
 } // extern "C"
diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml
index 2fbf850fc..4ea2f6de6 100644
--- a/src/usr/hwpf/hwp/memory_attributes.xml
+++ b/src/usr/hwpf/hwp/memory_attributes.xml
@@ -1930,9 +1930,9 @@ firmware notes: none</description>
 <attribute>
     <id>ATTR_MSS_CACHE_ENABLE</id>
     <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
-    <description>Value of on or off.  Determines if the L4 is enabled or not. See chapter 6 of the Centaur Workbook.  On means the full cache is enabled.  HALF_A (EVEN) means only A is enabled and HALF_B (ODD) means only B is enabled. This value is set by the platform which can get the chips value by running the mss_cen_get_ecid function.</description>
+    <description>Reflects the functionality of the L4 Cache.  Determines if the L4 is enabled or not. See chapter 6 of the Centaur Workbook.  On means the full cache is enabled.  HALF_A (EVEN) means only A is enabled and HALF_B (ODD) means only B is enabled. For DD1X, the values of UNK_OFF, UNK_ON, UNK_HALF_A and UNK_HALFB were added because early parts did not have the fuses blown correctly, so the cache repairs may not have worked. This value is set by the platform which can get the chips value by running the mss_cen_get_ecid function.</description>
     <valueType>uint8</valueType>
-    <enum>OFF = 0, ON = 1, HALF_A = 3, HALF_B = 5</enum>
+    <enum>OFF = 0, ON = 1, HALF_A = 3, HALF_B = 5, UNK_OFF = 8, UNK_ON = 9, UNK_HALF_A = 0xB, UNK_HALF_B = 0xD</enum>
     <platInit/>
     <odmVisable/>
     <odmChangeable/>