PRDF:Added support for FIR after conclusion of review - part2

Updated action for following FIR

    - MCDFIR
    - EHHCAFIR
    - ENHCAFIR
    - PCIE_LFIR

RTC: 23127
Change-Id: Ic82c1c254f3e28dd781b66fb74b11ae7374f139c
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5960
Tested-by: Jenkins Server
Reviewed-by: Christopher T. Phan <cphan@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Reviewed-by: Zane Shelley <zshelle@us.ibm.com>
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/6233

4 files changed, 369 insertions, 30 deletions

diff --git a/src/usr/diag/prdf/common/plat/pegasus/CommonActions.rule b/src/usr/diag/prdf/common/plat/pegasus/CommonActions.rule
index b22e7e76a..974dc9c5e 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/CommonActions.rule
+++ b/src/usr/diag/prdf/common/plat/pegasus/CommonActions.rule
@@ -219,6 +219,12 @@ actionclass calloutProcHighThr1SUE
     threshold1;
 };
 
+/** Callout 2nd level support of afer 32 events per day */
+actionclass callout2ndLvlMedThr32perDay
+{
+    callout2ndLvlMed;
+    threshold32pday;
+};
 ################################################################################
 #                               Dump Types                                     #
 ################################################################################
diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PB.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PB.rule
index 4defae80c..758bee5cb 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PB.rule
+++ b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PB.rule
@@ -83,7 +83,7 @@ group gPbChipletFir filter singlebit
     /** PB_CHIPLET_FIR[14]
      *  Attention from EHHCAFIR
      */
-    (PbChipletFir, bit(14)) ? defaultMaskedError;
+    (PbChipletFir, bit(14)) ? analyze(gEhHcaFir);
 
     /** PB_CHIPLET_FIR[15]
      *  Attention from NXASFIR
@@ -93,7 +93,7 @@ group gPbChipletFir filter singlebit
     /** PB_CHIPLET_FIR[16]
      *  Attention from ENHCAFIR
      */
-    (PbChipletFir, bit(16)) ? defaultMaskedError;
+    (PbChipletFir, bit(16)) ? analyze(gEnHcaFir);
 
     /** PB_CHIPLET_FIR[17|18|19]
      *  Attention from PCINESTFIRs
@@ -999,6 +999,8 @@ group gNxCxaFir filter singlebit
 ################################################################################
 # PB Chiplet MCDFIR
 ################################################################################
+# based on p8dd1_mss_FFDC_59.xls
+################################################################################
 
 rule McdFir
 {
@@ -1011,52 +1013,53 @@ group gMcdFir filter singlebit
     /** MCDFIR[0]
      *  MCD_ARRAY_ECC_UE_ERR
      */
-    (McdFir, bit(0)) ? TBDDefaultCallout;
+    (McdFir, bit(0)) ? SelfHighThr32PerDay;
 
     /** MCDFIR[1]
      *  MCD_ARRAY_ECC_CE_ERR
      */
-    (McdFir, bit(1)) ? TBDDefaultCallout;
+    (McdFir, bit(1)) ? SelfHighThr32PerDay;
 
     /** MCDFIR[2]
      *  MCD_REG_PARITY_ERR
      */
-    (McdFir, bit(2)) ? TBDDefaultCallout;
+    (McdFir, bit(2)) ? SelfHighThr32PerDay;
 
     /** MCDFIR[3]
      *  MCD_SM_ERR
      */
+    #FIXME RTC 23127 NX target not available as yet
     (McdFir, bit(3)) ? TBDDefaultCallout;
 
     /** MCDFIR[4]
      *  MCD_REC_HANG_ERR
      */
-    (McdFir, bit(4)) ? TBDDefaultCallout;
+    (McdFir, bit(4)) ? defaultMaskedError;
 
     /** MCDFIR[5]
      *  MCD_PB_PARITY_ERR
      */
-    (McdFir, bit(5)) ? TBDDefaultCallout;
+    (McdFir, bit(5)) ? defaultMaskedError;
 
     /** MCDFIR[6]
      *  MCD_UNSOLICITED_CRESP_ERR
      */
-    (McdFir, bit(6)) ? TBDDefaultCallout;
+    (McdFir, bit(6)) ? defaultMaskedError;
 
     /** MCDFIR[7]
      *  MCD_ACK_DEAD_ERR
      */
-    (McdFir, bit(7)) ? TBDDefaultCallout;
+    (McdFir, bit(7)) ? defaultMaskedError;
 
     /** MCDFIR[8]
      *  FIR_PARITY_ERR2
      */
-    (McdFir, bit(8)) ? TBDDefaultCallout;
+    (McdFir, bit(8)) ? defaultMaskedError;
 
     /** MCDFIR[9]
      *  FIR_PARITY_ERR
      */
-    (McdFir, bit(9)) ? TBDDefaultCallout;
+    (McdFir, bit(9)) ? defaultMaskedError;
 };
 
 ################################################################################
@@ -1999,6 +2002,264 @@ group gPbaFir filter singlebit
 };
 
 ################################################################################
+# PB Chiplet EHHCAFIR
+################################################################################
+# based on p8dd1_mss_FFDC_59.xls
+################################################################################
+rule EhHcaFir
+{
+    CHECK_STOP:  EHHCAFIR & ~EHHCAFIR_MASK & ~EHHCAFIR_ACT0 & ~EHHCAFIR_ACT1;
+    RECOVERABLE: EHHCAFIR & ~EHHCAFIR_MASK & ~EHHCAFIR_ACT0 &  EHHCAFIR_ACT1;
+};
+
+group gEhHcaFir filter singlebit
+{
+    /** EHHCAFIR[0]
+     *  CE1_0_OUT: array0_a CE
+     */
+    (EhHcaFir, bit(0)) ? defaultMaskedError;
+
+    /** EHHCAFIR[1]
+     *  CE2_0_OUT: array0_b CE
+     */
+    (EhHcaFir, bit(1)) ? defaultMaskedError;
+
+    /** EHHCAFIR[2]
+     *  UE1_0_OUT: array0_a ue
+     */
+    (EhHcaFir, bit(2)) ? SelfHighThr32PerDay;
+
+    /** EHHCAFIR[3]
+     *  UE2_0_OUT: array0_b ue
+     */
+    (EhHcaFir, bit(3)) ? SelfHighThr32PerDay;
+
+    /** EHHCAFIR[4]
+     *  CE1_1_OUT: array1_a CE
+     */
+    (EhHcaFir, bit(4)) ? defaultMaskedError;
+
+    /** EHHCAFIR[5]
+     *  CE2_1_OUT: array1_b CE
+     */
+    (EhHcaFir, bit(5)) ? defaultMaskedError;
+
+    /** EHHCAFIR[6]
+     *  UE1_1_OUT: array1_a ue
+     */
+    (EhHcaFir, bit(6)) ? SelfHighThr32PerDay;
+
+    /** EHHCAFIR[7]
+     *  UE2_1_OUT: array1_b ue
+     */
+    (EhHcaFir, bit(7)) ? SelfHighThr32PerDay;
+
+    /** EHHCAFIR[8]
+     *  CE1_2_OUT: array2_a CE
+     */
+    (EhHcaFir, bit(8)) ? defaultMaskedError;
+
+    /** EHHCAFIR[9]
+     *  CE2_2_OUT: array2_b CE
+     */
+    (EhHcaFir, bit(9)) ? defaultMaskedError;
+
+    /** EHHCAFIR[10]
+     *  UE1_2_OUT: array2_a ue
+     */
+    (EhHcaFir, bit(10)) ? SelfHighThr32PerDay;
+
+    /** EHHCAFIR[11]
+     *  UE2_2_OUT: array2_b ue
+     */
+    (EhHcaFir, bit(11)) ? SelfHighThr32PerDay;
+
+    /** EHHCAFIR[12]
+     *  CE1_3_OUT: array3_a CE
+     */
+    (EhHcaFir, bit(12)) ? defaultMaskedError;
+
+    /** EHHCAFIR[13]
+     *  CE2_3_OUT: array3_b CE
+     */
+    (EhHcaFir, bit(13)) ? defaultMaskedError;
+
+    /** EHHCAFIR[14]
+     *  UE1_3_OUT: array3_a ue
+     */
+    (EhHcaFir, bit(14)) ? SelfHighThr32PerDay;
+
+    /** EHHCAFIR[15]
+     *  UE2_3_OUT: array3_b ue
+     */
+    (EhHcaFir, bit(15)) ? SelfHighThr32PerDay;
+
+    /** EHHCAFIR[16]
+     *  CE1_4_OUT: array4_a CE
+     */
+    (EhHcaFir, bit(16)) ? defaultMaskedError;
+
+    /** EHHCAFIR[17]
+     *  CE2_4_OUT: array4_b CE
+     */
+    (EhHcaFir, bit(17)) ? defaultMaskedError;
+
+    /** EHHCAFIR[18]
+     *  UE1_4_OUT: array4_a ue
+     */
+    (EhHcaFir, bit(18)) ? SelfHighThr32PerDay;
+
+    /** EHHCAFIR[19]
+     *  UE2_4_OUT: array4_b ue
+     */
+    (EhHcaFir, bit(19)) ? SelfHighThr32PerDay;
+
+    /** EHHCAFIR[20]
+     *  CE1_5_OUT: array5_a CE
+     */
+    (EhHcaFir, bit(20)) ? defaultMaskedError;
+
+    /** EHHCAFIR[21]
+     *  CE2_5_OUT: array5_b CE
+     */
+    (EhHcaFir, bit(21)) ? defaultMaskedError;
+
+    /** EHHCAFIR[22]
+     *  UE1_5_OUT: array5_a ue
+     */
+    (EhHcaFir, bit(22)) ? SelfHighThr32PerDay;
+
+    /** EHHCAFIR[23]
+     *  UE2_5_OUT: array5_b ue
+     */
+    (EhHcaFir, bit(23)) ? SelfHighThr32PerDay;
+
+    /** EHHCAFIR[24]
+     *  CE1_6_OUT: array6_a CE
+     */
+    (EhHcaFir, bit(24)) ? defaultMaskedError;
+
+    /** EHHCAFIR[25]
+     *  CE2_6_OUT: array6_b CE
+     */
+    (EhHcaFir, bit(25)) ? defaultMaskedError;
+
+    /** EHHCAFIR[26]
+     *  UE1_6_OUT: array6_a ue
+     */
+    (EhHcaFir, bit(26)) ? SelfHighThr32PerDay;
+
+    /** EHHCAFIR[27]
+     *  UE2_6_OUT: array6_b ue
+     */
+    (EhHcaFir, bit(27)) ? SelfHighThr32PerDay;
+
+    /** EHHCAFIR[28]
+     *  CE1_7_OUT: array7_a CE
+     */
+    (EhHcaFir, bit(28)) ? defaultMaskedError;
+
+    /** EHHCAFIR[29]
+     *  CE2_7_OUT: array7_b CE
+     */
+    (EhHcaFir, bit(29)) ? defaultMaskedError;
+
+    /** EHHCAFIR[30]
+     *  UE1_7_OUT: array7_a ue
+     */
+    (EhHcaFir, bit(30)) ? SelfHighThr32PerDay;
+
+    /** EHHCAFIR[31]
+     *  UE2_7_OUT: array7_b ue
+     */
+    (EhHcaFir, bit(31)) ? SelfHighThr32PerDay;
+
+    /** EHHCAFIR[32]
+     *  DROP_COUNTER_FULL: Drop Counter Full
+     */
+    (EhHcaFir, bit(32)) ? defaultMaskedError;
+
+    /** EHHCAFIR[33]
+     *  INTERNAL_ERROR: Internal Error
+     */
+    (EhHcaFir, bit(33)) ? defaultMaskedError;
+
+    /** EHHCAFIR[34]
+     *  SCOM_ERROR
+     */
+    (EhHcaFir, bit(34)) ? defaultMaskedError;
+
+    /** EHHCAFIR[35]
+     *  FIR_PARITY_ERROR
+     */
+    (EhHcaFir, bit(35)) ? defaultMaskedError;
+};
+
+################################################################################
+# PB Chiplet ENHCAFIR
+################################################################################
+#action updated based on p8dd1_mss_FFDC_59.xls
+################################################################################
+
+rule EnHcaFir
+{
+    CHECK_STOP:  ENHCAFIR & ~ENHCAFIR_MASK & ~ENHCAFIR_ACT0 & ~ENHCAFIR_ACT1;
+    RECOVERABLE: ENHCAFIR & ~ENHCAFIR_MASK & ~ENHCAFIR_ACT0 &  ENHCAFIR_ACT1;
+};
+
+group gEnHcaFir filter singlebit
+{
+    /** ENHCAFIR[0]
+     *  DPX0_DAT_UE: PB0 data UE
+     */
+    (EnHcaFir, bit(0)) ? SelfHighThr32PerDay;
+
+    /** ENHCAFIR[1]
+     *  DPX0_DAT_SUE: PB0 data UE
+     */
+    (EnHcaFir, bit(1)) ? SelfHighThr32PerDay;
+
+    /** ENHCAFIR[2]
+     *  DPX0_DAT_CE: PB0 data ue
+     */
+    (EnHcaFir, bit(2)) ? SelfHighThr32PerDay;
+
+    /** ENHCAFIR[3]
+     *  Undefined
+     */
+    (EnHcaFir, bit(3)) ? defaultMaskedError;
+
+    /** ENHCAFIR[4]
+     *  CO_DROP_COUNTER_FULL: Castout Drop Counter Full
+     */
+    (EnHcaFir, bit(4)) ? defaultMaskedError;
+
+    /** ENHCAFIR[5]
+     *  DATA_HANG_DETECT: Castout Drop Counter Full
+     */
+    (EnHcaFir, bit(5)) ? defaultMaskedError;
+
+    /** ENHCAFIR[6]
+     *  UNEXPECTED_DATA_OR_CRESP: Castout Drop Counter Full
+     */
+    (EnHcaFir, bit(6)) ? defaultMaskedError;
+
+    /** ENHCAFIR[7]
+     *  INTERNAL_ERROR: Castout Drop Counter Full
+     */
+    (EnHcaFir, bit(7)) ? defaultMaskedError;
+
+    /** ENHCAFIR[8]
+     *  SCOM_ERROR
+     */
+    (EnHcaFir, bit(8)) ? defaultMaskedError;
+
+    /** ENHCAFIR[9]
+     *  FIR_PARITY_ERROR
+     */
+    (EnHcaFir, bit(9)) ? defaultMaskedError;
+};
+
 # PB Chiplet PCINESTFIRs
 ################################################################################
 
@@ -2833,13 +3094,6 @@ actionclass callout2ndLvlMedThr1
     threshold1;
 };
 
-/** Callout 2nd level support of afer 32 events per day */
-actionclass callout2ndLvlMedThr32perDay
-{
-    callout2ndLvlMed;
-    threshold32pday;
-};
-
 /** callout both ends of PSI Link.Threshold is 32 events per day.
  */
 actionclass  calloutPsiThr32
diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PCIE.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PCIE.rule
index cdc14077e..b35b1b373 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PCIE.rule
+++ b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PCIE.rule
@@ -72,6 +72,8 @@ group gPcieChipletSpa filter singlebit
 ################################################################################
 # PCIE Chiplet LFIR
 ################################################################################
+# based on p8dd1_mss_FFDC_59.xls
+################################################################################
 
 rule PcieLFir
 {
@@ -84,52 +86,72 @@ group gPcieLFir filter singlebit
     /** PCIE_LFIR[0]
      *  CFIR internal parity error
      */
-    (PcieLFir, bit(0)) ? TBDDefaultCallout;
+    (PcieLFir, bit(0)) ? SelfHighThr32PerDay;
 
     /** PCIE_LFIR[1]
      *  Local errors from GPIO (PCB error)
      */
-    (PcieLFir, bit(1)) ? TBDDefaultCallout;
+    (PcieLFir, bit(1)) ? defaultMaskedError;
 
     /** PCIE_LFIR[2]
      *  Local errors from CC (PCB error)
      */
-    (PcieLFir, bit(2)) ? TBDDefaultCallout;
+    (PcieLFir, bit(2)) ? defaultMaskedError;
 
     /** PCIE_LFIR[3]
      *  Local errors from CC (OPCG, parity, scan collision, ...)
      */
-    (PcieLFir, bit(3)) ? TBDDefaultCallout;
+    (PcieLFir, bit(3)) ? callout2ndLvlMedThr32perDay;
 
     /** PCIE_LFIR[4]
      *  Local errors from PSC (PCB error)
      */
-    (PcieLFir, bit(4)) ? TBDDefaultCallout;
+    (PcieLFir, bit(4)) ? defaultMaskedError;
 
     /** PCIE_LFIR[5]
      *  Local errors from PSC (parity error)
      */
-    (PcieLFir, bit(5)) ? TBDDefaultCallout;
+    (PcieLFir, bit(5)) ? defaultMaskedError;
 
     /** PCIE_LFIR[6]
      *  Local errors from Thermal (parity error)
      */
-    (PcieLFir, bit(6)) ? TBDDefaultCallout;
+    (PcieLFir, bit(6)) ? defaultMaskedError;
 
     /** PCIE_LFIR[7]
      *  Local errors from Thermal (PCB error)
      */
-    (PcieLFir, bit(7)) ? TBDDefaultCallout;
+    (PcieLFir, bit(7)) ? defaultMaskedError;
 
     /** PCIE_LFIR[8|9]
      *  Local errors from Thermal (Trip error)
      */
-    (PcieLFir, bit(8|9)) ? TBDDefaultCallout;
+    (PcieLFir, bit(8|9)) ? defaultMaskedError;
 
     /** PCIE_LFIR[10|11]
      *  Local errors from Trace Array ( error)
      */
-    (PcieLFir, bit(10|11)) ? TBDDefaultCallout;
+    (PcieLFir, bit(10|11)) ? defaultMaskedError;
+
+    /** PCIE_LFIR[12:20]
+     *  Unused local errors
+     */
+    (PcieLFir, bit(12|13|14|15|16|17|18|19|20)) ? defaultMaskedError;
+
+    /** PCIE_LFIR[21:30]
+     *  Unused local errors
+     */
+    (PcieLFir, bit(21|22|23|24|25|26|27|28|29|30)) ? defaultMaskedError;
+
+    /** PCIE_LFIR[31:39]
+     *  Unused local errors
+     */
+    (PcieLFir, bit(31|32|33|34|35|36|37|38|39)) ? defaultMaskedError;
+
+    /** PCIE_LFIR[40]
+     *  Malfunction alert (local xstop in another chiplet)
+     */
+    (PcieLFir, bit(40)) ? defaultMaskedError;
 };
 
 ################################################################################
diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PB.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PB.rule
index e9395f03f..772157838 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PB.rule
+++ b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PB.rule
@@ -535,22 +535,79 @@
     };
 
     ############################################################################
-    # PB Chiplet EHHCAFIR and ENHCAFIR
-    # These FIRs are completely masked but they will be captured for FFDC.
+    # PB Chiplet EHHCAFIR
     ############################################################################
 
     register EHHCAFIR
     {
         name        "EH.TPC.HCA.EHHCA_FIR_REG";
         scomaddr    0x02010980;
+        reset       (&, 0x02010981);
+        mask        (|, 0x02010985);
         capture     group default;
     };
 
+    register EHHCAFIR_MASK
+    {
+        name        "EH.TPC.HCA.EHHCA_FIR_MASK_REG";
+        scomaddr    0x02010983;
+        capture     group default;
+    };
+
+    register EHHCAFIR_ACT0
+    {
+        name        "EH.TPC.HCA.EHHCA_FIR_ACTION0_REG";
+        scomaddr    0x02010986;
+        capture     type secondary;
+        capture     group default;
+        capture     req nonzero("EHHCAFIR");
+    };
+
+    register EHHCAFIR_ACT1
+    {
+        name        "EH.TPC.HCA.EHHCA_FIR_ACTION1_REG";
+        scomaddr    0x02010987;
+        capture     type secondary;
+        capture     group default;
+        capture     req nonzero("EHHCAFIR");
+    };
+
+    ############################################################################
+    # PB Chiplet ENHCAFIR
+    ############################################################################
+
     register ENHCAFIR
     {
         name        "EN.TPC.BRIDGE.HCA.ENHCA_FIR_REG";
         scomaddr    0x02010940;
+        reset       (&, 0x02010941);
+        mask        (|, 0x02010945);
+        capture     group default;
+    };
+
+    register ENHCAFIR_MASK
+    {
+        name        "EN.TPC.BRIDGE.HCA.ENHCA_FIR_MASK_REG";
+        scomaddr    0x02010943;
+        capture     group default;
+    };
+
+    register ENHCAFIR_ACT0
+    {
+        name        "EN.TPC.BRIDGE.HCA.ENHCA_FIR_ACTION0_REG";
+        scomaddr    0x02010946;
+        capture     type secondary;
+        capture     group default;
+        capture     req nonzero("ENHCAFIR");
+    };
+
+    register ENHCAFIR_ACT1
+    {
+        name        "EN.TPC.BRIDGE.HCA.ENHCA_FIR_ACTION1_REG";
+        scomaddr    0x02010947;
+        capture     type secondary;
         capture     group default;
+        capture     req nonzero("ENHCAFIR");
     };
 
     ############################################################################