Change p9_mss_freq_system to write attributes, errors for Cronus

  Honor the maximum support frequencies based on rank configs
  Remove the MEMVPD_FREQ attribute
  Fixup VPD tooling and accessors for new freq attrs
  Fix test case handling of master ranks
  Fix handling of empty MCS in Cronus

Change-Id: I669ad0e81454f12368b484e826461ee76f7b9079
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29878
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29907
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

25 files changed, 1709 insertions, 306 deletions

diff --git a/src/import/chips/p9/procedures/hwp/accessors/p9_get_mem_vpd_keyword.C b/src/import/chips/p9/procedures/hwp/accessors/p9_get_mem_vpd_keyword.C
index 9ef8237b3..af72417c1 100644
--- a/src/import/chips/p9/procedures/hwp/accessors/p9_get_mem_vpd_keyword.C
+++ b/src/import/chips/p9/procedures/hwp/accessors/p9_get_mem_vpd_keyword.C
@@ -129,7 +129,7 @@ extern "C"
         uint8_t  l_rankShift = 0;
         uint8_t  l_freqMask  = 0;
         uint32_t l_freqTableIndex = 0;
-        fapi2::ATTR_MEMVPD_FREQS_MHZ_Type l_freqTable = {0};
+        constexpr uint32_t l_freqTable[] = {1866, 2133, 2400, 2666};
         uint32_t l_freqTableCnt = sizeof(l_freqTable) / sizeof(l_freqTable[0]);
         uint32_t l_index = 0; //start with first criteria row
         uint32_t l_indexMax = MAPPING_LAYOUT_MAXROWS;
@@ -267,11 +267,6 @@ extern "C"
         else
         {
             // Get the frequency index and calculate mask
-            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEMVPD_FREQS_MHZ,
-                                   fapi2::Target<TARGET_TYPE_SYSTEM>(),
-                                   l_freqTable),
-                     "p9_get_mem_vpd_keyword: get ATTR_MEMVPD_FREQS_MHZ failed");
-
             for (; l_freqTableIndex < l_freqTableCnt; l_freqTableIndex++)
             {
                 if (i_vpd_info.iv_freq_mhz == l_freqTable[l_freqTableIndex])
@@ -289,7 +284,7 @@ extern "C"
                         set_MEMVPDFREQ3(uint32_t(l_freqTable[3])).
                         set_TARGET(i_target).
                         set_VPDTYPE(i_vpd_info.iv_vpd_type),
-                        "Frequency %d not in ATTR_MEMVPD_FREQS_MHZ",
+                        "Frequency %d not supported by Nimbus",
                         i_vpd_info.iv_freq_mhz);
             l_freqMask = (MAPPING_LAYOUT_FREQ_0 >> l_freqTableIndex); //zero based
             FAPI_DBG ("p9_get_mem_vpd_keyword: frequency index = %d mask=0x%02x",
diff --git a/src/import/chips/p9/procedures/hwp/accessors/p9_get_mem_vpd_keyword.H b/src/import/chips/p9/procedures/hwp/accessors/p9_get_mem_vpd_keyword.H
index 4baff3fa9..6bdaf6dbb 100644
--- a/src/import/chips/p9/procedures/hwp/accessors/p9_get_mem_vpd_keyword.H
+++ b/src/import/chips/p9/procedures/hwp/accessors/p9_get_mem_vpd_keyword.H
@@ -92,7 +92,7 @@ extern "C"
     ///             ... through ..
     ///             0x0002 dimm0 rank count 4, dimm1 rank count 2
     ///             0x0001 dimm0 rank count 4, dimm1 rank count 4
-    /// ffff        frequency index from ATTR_MEMVPD_FREQS_MHZ
+    /// ffff        frequency index from ATTR_MSS_MRW_SUPPORTED_FREQ
     ///             0x80 index 0
     ///             ... through ..
     ///             0x10 index 3
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C
index 426ef605d..0a5abdbb2 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C
@@ -288,45 +288,6 @@ fapi_try_exit:
 }
 
 ///
-/// @brief Determines & sets effective config for number of master ranks per dimm
-/// @param[in] i_target FAPI2 target
-/// @return fapi2::FAPI2_RC_SUCCESS if okay
-///
-fapi2::ReturnCode eff_config::master_ranks_per_dimm(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
-{
-    const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
-    const auto l_mca = find_target<TARGET_TYPE_MCA>(i_target);
-
-    uint8_t l_decoder_val = 0;
-    fapi2::buffer<uint8_t> l_ranks_configed;
-    uint8_t l_attrs_master_ranks_per_dimm[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
-    uint8_t l_attrs_dimm_ranks_configed[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
-
-    // Get & update MCS attributes
-    FAPI_TRY( iv_pDecoder->num_package_ranks_per_dimm(i_target, l_decoder_val) );
-    FAPI_TRY(eff_num_master_ranks_per_dimm(l_mcs, &l_attrs_master_ranks_per_dimm[0][0]));
-    FAPI_TRY(eff_dimm_ranks_configed(l_mcs, &l_attrs_dimm_ranks_configed[0][0]));
-
-    l_attrs_master_ranks_per_dimm[index(l_mca)][index(i_target)] = l_decoder_val;
-
-    // Set configed ranks. Set the bit representing the master rank configured (0 being left most.) So,
-    // a 4R DIMM would be 0b11110000 (0xF0). This is used by PRD.
-    FAPI_TRY( l_ranks_configed.setBit(0, l_decoder_val) );
-    l_attrs_dimm_ranks_configed[index(l_mca)][index(i_target)] = l_ranks_configed;
-
-    FAPI_INF( "%s Num Master Ranks %d, DIMM Ranks Configed 0x%x",
-              mss::c_str(i_target),
-              l_attrs_master_ranks_per_dimm[index(l_mca)][index(i_target)],
-              l_attrs_dimm_ranks_configed[index(l_mca)][index(i_target)] );
-
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, l_mcs, l_attrs_master_ranks_per_dimm) );
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_RANKS_CONFIGED, l_mcs, l_attrs_dimm_ranks_configed) );
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
-
-///
 /// @brief Determines & sets effective config for stack type
 /// @param[in] i_target FAPI2 target
 /// @return fapi2::FAPI2_RC_SUCCESS if okay
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.C b/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.C
index ce92c500a..07e4ca4d2 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.C
@@ -66,17 +66,17 @@ namespace mss
 /// @param[in]  i_caches decoder caches
 ///
 cas_latency::cas_latency(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
-                         const std::map<uint32_t, std::shared_ptr<spd::decoder> >& i_caches)
+                         const std::map<uint32_t, std::shared_ptr<spd::decoder> >& i_caches):
+    iv_dimm_list_empty(false),
+    iv_largest_taamin(0),
+    iv_proposed_tck(0),
+    iv_common_CL(UINT64_MAX) // Masks out supported CLs
 {
-    iv_dimm_list_empty = false;
-    iv_common_CL = UINT64_MAX; // Masks out supported CLs
-    iv_largest_taamin = 0;
-    iv_proposed_tck = 0;
-
     const auto l_dimm_list = find_targets<TARGET_TYPE_DIMM>(i_target);
 
     if(l_dimm_list.empty())
     {
+        FAPI_INF("cas latency ctor seeing no DIMM on %s", mss::c_str(i_target));
         iv_dimm_list_empty = true;
         return;
     }
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/freq/cycle_time.H b/src/import/chips/p9/procedures/hwp/memory/lib/freq/cycle_time.H
index 860cf3fca..2352d14df 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/freq/cycle_time.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/freq/cycle_time.H
@@ -22,6 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+
 ///
 /// @file cycle_time.H
 /// @brief cycle time (tCK) data & functions needed for CAS latency algorithm
@@ -37,19 +38,11 @@
 
 #include <fapi2.H>
 #include <memory>
+#include <lib/freq/sync.H>
 
 namespace mss
 {
 
-enum FREQ_LIMITS
-{
-    // Can't add these limits in xml because
-    // Cronus won't know what ENUM to print out
-    // if there are two enums for the same value.
-    MAX_SUPPORTED_FREQ = fapi2::ENUM_ATTR_MSS_FREQ_MT2666,
-    MIN_SUPPORTED_FREQ = fapi2::ENUM_ATTR_MSS_FREQ_MT1866
-};
-
 enum FREQ_MARGIN : std::uint64_t
 {
     // -5% of 1866 MT/s
@@ -59,17 +52,6 @@ enum FREQ_MARGIN : std::uint64_t
     MAX_FREQ_MARGIN = 2799,
 };
 
-static const std::vector<uint64_t> P9_FREQS
-{
-    // P9 supported frequencies in addition to
-    // TK - How make sure thes vector is always updated if enums are changed?
-    fapi2::ENUM_ATTR_MSS_FREQ_MT1866,
-    fapi2::ENUM_ATTR_MSS_FREQ_MT2133,
-    fapi2::ENUM_ATTR_MSS_FREQ_MT2400,
-    fapi2::ENUM_ATTR_MSS_FREQ_MT2666,
-};
-
-
 // Proposed DDR4 Full spec update(79-4A)
 // Item No. 1716.78C
 // Page 217
@@ -86,7 +68,10 @@ static const std::vector<uint64_t> tckmin_avg_ddr4
     /* 1250, // 1600 MT/s - don't think we support this one - AAM */
 };
 
+///
 /// @brief          Selects DIMM frequency to run based on supported system frequencies
+/// @tparam         T the fapi2::TargetType for which the DIMM information exists.
+/// @param[in]      target from which to get the dimm information
 /// @param[in,out]  io_dimm_freq input is current dimm freq & output is next
 ///                 lowest dimm freq between 1866 MT/s (-5% margin)  - 2666 MT/s (+5% margin)
 /// @return         FAPI2_RC_SUCCESS iff ok
@@ -94,8 +79,13 @@ static const std::vector<uint64_t> tckmin_avg_ddr4
 /// @note           From P9 User's Manual Version 0.8 - June 08, 2015
 /// @note           Memory Controller Unit - page 199 of 456
 ///
-inline fapi2::ReturnCode select_supported_freq(uint64_t& io_dimm_freq)
+template< fapi2::TargetType T >
+inline fapi2::ReturnCode select_supported_freq(const fapi2::Target<T>& i_target, uint64_t& io_dimm_freq)
 {
+    uint32_t l_min_freq = 0;
+    uint32_t l_max_freq = 0;
+    std::vector<uint32_t> l_freqs;
+
     //TK - This 5% margin was done in P8, continue for P9 ?? - AAMARIN
 
     // Speed bins for P9 DDR4 are 1866 MT/s -  2666 MT/s
@@ -108,25 +98,31 @@ inline fapi2::ReturnCode select_supported_freq(uint64_t& io_dimm_freq)
                  "Unsupported frequency: %d.  DIMM Freq calculated is < 1773 or > 2799 MT/s",
                  io_dimm_freq);
 
+    FAPI_TRY( mss::supported_freqs(i_target, l_freqs) );
+    l_min_freq = *(l_freqs.begin());
+    l_max_freq = *(l_freqs.end() - 1);
+
     // Corner case to take into account -5% margin
-    if(io_dimm_freq  < MIN_SUPPORTED_FREQ)
+    if(io_dimm_freq  < l_min_freq)
     {
-        io_dimm_freq = MIN_SUPPORTED_FREQ;
+        io_dimm_freq = l_min_freq;
         return fapi2::FAPI2_RC_SUCCESS;
     }
 
     // Corner case to take into account +5% margin
-    if(io_dimm_freq > MAX_SUPPORTED_FREQ)
+    if(io_dimm_freq > l_max_freq)
     {
-        io_dimm_freq = MAX_SUPPORTED_FREQ;
+        io_dimm_freq = l_max_freq;
         return fapi2::FAPI2_RC_SUCCESS;
     }
 
     // Selects next lowest freq btw 1866 - 2666 [MT/s]
     {
-        auto iterator = std::upper_bound(P9_FREQS.begin(), P9_FREQS.end(), io_dimm_freq);
+        // supported_freqs sorts so upper_bound is valid.
+        auto iterator = std::upper_bound(l_freqs.begin(), l_freqs.end(), io_dimm_freq);
         io_dimm_freq = *(--iterator);
     }
+
 fapi_try_exit:
     return fapi2::current_err;
 }
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/freq/sync.C b/src/import/chips/p9/procedures/hwp/memory/lib/freq/sync.C
index c3acf1070..eb1cb3661 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/freq/sync.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/freq/sync.C
@@ -32,6 +32,7 @@
 // *HWP Team: Memory
 // *HWP Level: 2
 // *HWP Consumed by: HB:FSP
+
 #include  <vector>
 #include <map>
 
@@ -39,15 +40,23 @@
 #include <mss.H>
 #include <lib/freq/sync.H>
 #include <lib/utils/find.H>
+#include <lib/utils/assert_noexit.H>
 
 using fapi2::TARGET_TYPE_DIMM;
 using fapi2::TARGET_TYPE_MCS;
+using fapi2::TARGET_TYPE_MCA;
 using fapi2::TARGET_TYPE_MCBIST;
 using fapi2::TARGET_TYPE_SYSTEM;
 
 namespace mss
 {
 
+// This doesn't seem to be available from the XML, so we'll kind of just hard-wire it. They're
+// here as I don't think these values are generally useful and I really don't want them used
+// other places.
+constexpr size_t NUM_VPD_FREQS = 4;
+constexpr size_t NUM_MAX_FREQS = 5;
+
 ///
 /// @brief Retrieves a mapping of MSS frequency values per mcbist target
 /// @param[in] i_targets vector of controller targets
@@ -148,7 +157,6 @@ bool deconfigure(const fapi2::Target<TARGET_TYPE_MCBIST>& i_target,
     FAPI_INF("---- In deconfigure ----");
     bool l_is_hw_deconfigured = false;
 
-    // TODO - RTC 155347 fix dimm speed & nest comparison if needed
     if(i_dimm_speed != i_nest_freq)
     {
         // Deconfigure MCSes
@@ -156,13 +164,13 @@ bool deconfigure(const fapi2::Target<TARGET_TYPE_MCBIST>& i_target,
         {
             l_is_hw_deconfigured = true;
 
-            PLAT_FAPI_ASSERT_NOEXIT(false,
-                                    fapi2::MSS_FREQ_NOT_EQUAL_NEST_FREQ()
-                                    .set_MSS_FREQ(i_dimm_speed)
-                                    .set_NEST_FREQ(i_nest_freq)
-                                    .set_MCS_TARGET(l_mcs),
-                                    "Deconfiguring %s",
-                                    mss::c_str(l_mcs) );
+            MSS_ASSERT_NOEXIT(false,
+                              fapi2::MSS_FREQ_NOT_EQUAL_NEST_FREQ()
+                              .set_MSS_FREQ(i_dimm_speed)
+                              .set_NEST_FREQ(i_nest_freq)
+                              .set_MCS_TARGET(l_mcs),
+                              "Deconfiguring %s",
+                              mss::c_str(l_mcs) );
         }// end for
     }// end if
 
@@ -176,63 +184,99 @@ bool deconfigure(const fapi2::Target<TARGET_TYPE_MCBIST>& i_target,
 /// @param[in] i_nest_freq nest frequency
 /// @param[in] i_required_sync_mode system policy to enforce synchronous mode
 /// @param[out] o_selected_sync_mode final synchronous mode
+/// @param[out] o_selected_freq final freq selected, only valid if final sync mode is in-sync
 /// @return FAPI2_RC_SUCCESS iff successful
 ///
 fapi2::ReturnCode select_sync_mode(const std::map< fapi2::Target<TARGET_TYPE_MCBIST>, uint64_t >& i_freq_map,
                                    const speed_equality i_equal_dimm_speed,
                                    const uint32_t i_nest_freq,
                                    const uint8_t i_required_sync_mode,
-                                   sync_mode& o_selected_sync_mode)
+                                   uint8_t& o_selected_sync_mode,
+                                   uint64_t& o_selected_freq)
 {
     FAPI_INF("---- In select_sync_mode ----");
 
-    // Implementing frequency handling discussion:
-    // https://w3-connections.ibm.com/forums/html/topic?id=1222318f-5992-4342-a858-b75594df1be3&ps=
-    // Summary: We will always use async mode if we don't see a perfect match of dimm frequencies that match the nest
+    // If we're in SYNC_MODE_NEVER, then we're done and we tell the caller we're not in sync mode
+    if (fapi2::ENUM_ATTR_REQUIRED_SYNCH_MODE_NEVER == i_required_sync_mode)
+    {
+        o_selected_sync_mode = fapi2::ENUM_ATTR_MC_SYNC_MODE_NOT_IN_SYNC;
+        return fapi2::FAPI2_RC_SUCCESS;
+    }
+
     switch(i_equal_dimm_speed)
     {
+        // If we have MCBIST which have resolved to equal speeds ...
         case speed_equality::EQUAL_DIMM_SPEEDS:
 
-            // Do not run synchronously, even if the frequencies match
-            if (i_required_sync_mode == fapi2::ENUM_ATTR_REQUIRED_SYNCH_MODE_NEVER)
-            {
-                o_selected_sync_mode = sync_mode::MC_NOT_IN_SYNC;
-                break;
-            }
+            // Return back the resulting speed. It doesn't matter which we select from the map as they're all equal
+            // If we end up not in sync in the conditional below, thats ok - this parameter is ignored by the
+            // caller if we're not in sync mode
+            o_selected_freq = i_freq_map.begin()->second;
 
-            // Run synchronously if the dimm and nest freq matches
-            // Implicitly covers case when ATTR_REQUIRED_SYNCH_MODE is
-            // ALWAYS and UNDETERMINED
-            if( i_freq_map.begin()->second  == i_nest_freq)
-            {
-                o_selected_sync_mode = sync_mode::MC_IN_SYNC;
-            }
-            else
+            // When we selected ATTR_MSS_FREQ, we made sure that for forced sync mode cases we didn't
+            // select a DIMM freq the nest couldn't support. So if we're in forced sync mode, we're done.
+            if (i_required_sync_mode == fapi2::ENUM_ATTR_REQUIRED_SYNCH_MODE_ALWAYS)
             {
-                o_selected_sync_mode =  sync_mode::MC_NOT_IN_SYNC;
+                o_selected_sync_mode = fapi2::ENUM_ATTR_MC_SYNC_MODE_IN_SYNC;
+                // On Cronus if the o_selected_freq != i_nest_freq we've got a mismatch. Note that p9_mss_freq ensures
+                // we don't select an invalid freq, but doesn't ensure we select the current nest freq.
+#ifndef __HOSTBOOT_MODULE
+                FAPI_ASSERT(o_selected_freq == i_nest_freq,
+                            fapi2::MSS_FAILED_SYNC_MODE().set_NEST_FREQ(i_nest_freq),
+                            "Configured in sync mode, but the DIMM freq (%d) and the nest freq (%d) don't align",
+                            o_selected_freq, i_nest_freq);
+#endif
+                return fapi2::FAPI2_RC_SUCCESS;
+
             }
 
+            // So we need to decide. We know the DIMM speeds are equal and we know we picked the fastest supportable
+            // speed. So, if we're within the nest frequencies then we can run sync mode (lowest latency.) If we're
+            // outside of the nest frequencies we'll run async (higest DIMM speed.)
+            o_selected_sync_mode = (i_nest_freq <= fapi2::ENUM_ATTR_MSS_FREQ_MT2400) ?
+                                   fapi2::ENUM_ATTR_MC_SYNC_MODE_IN_SYNC : fapi2::ENUM_ATTR_MC_SYNC_MODE_NOT_IN_SYNC;
+            return fapi2::FAPI2_RC_SUCCESS;
             break;
 
         case speed_equality::NOT_EQUAL_DIMM_SPEEDS:
 
-            // Require matching frequencies and deconfigure memory that does not match the nest
+            // When we selected ATTR_MSS_FREQ, we made sure that for forced sync mode cases we didn't
+            // select a DIMM freq the nest couldn't support. That means that the fastest of the MCBIST
+            // is the one that rules the roost (the nest can support it too.) So find that, and set it to
+            // the selected frequency. Then deconfigure the slower MCBIST (unless we're in Cronus in which
+            // case we just bomb out.)
+#ifdef __HOSTBOOT_MODULE
             if( i_required_sync_mode == fapi2::ENUM_ATTR_REQUIRED_SYNCH_MODE_ALWAYS )
             {
-                for(const auto& l_it : i_freq_map)
+                uint64_t l_max_dimm_speed = 0;
+                std::for_each(i_freq_map.begin(), i_freq_map.end(),
+                              [&l_max_dimm_speed](const std::pair<fapi2::Target<TARGET_TYPE_MCBIST>, uint64_t>& m)
                 {
-                    // This can be refactored to return info people might
-                    // need.  Until then this returns true if hw was deconfigured
-                    // FFDC prints out location
-                    deconfigure(l_it.first, l_it.second, i_nest_freq);
+                    l_max_dimm_speed = std::max(l_max_dimm_speed, m.second);
+                });
 
-                }// end for
-            }// end if
+                std::for_each(i_freq_map.begin(), i_freq_map.end(),
+                              [&l_max_dimm_speed](const std::pair<fapi2::Target<TARGET_TYPE_MCBIST>, uint64_t>& m)
+                {
+                    deconfigure(m.first, m.second, l_max_dimm_speed);
+                });
 
-            // Implicitly covers case when ATTR_REQUIRED_SYNCH_MODE is
-            // NEVER, ALWAYS, and UNDETERMINED
-            o_selected_sync_mode = sync_mode::MC_NOT_IN_SYNC;
+                o_selected_sync_mode = fapi2::ENUM_ATTR_MC_SYNC_MODE_IN_SYNC;
+                o_selected_freq = l_max_dimm_speed;
+                return fapi2::FAPI2_RC_SUCCESS;
+            }
 
+#else
+            // Cronus only
+            FAPI_ASSERT(i_required_sync_mode != fapi2::ENUM_ATTR_REQUIRED_SYNCH_MODE_ALWAYS,
+                        fapi2::MSS_FAILED_SYNC_MODE().set_NEST_FREQ(i_nest_freq),
+                        "Seeing forced nest/memory sync mode but DIMM speeds differ from nest speed %d", i_nest_freq);
+#endif
+
+            // Notce that if we don't have equal DIMM speeds we're never in sync. We either error out (Cronus)
+            // or we toss a bunch of DIMM off the boat (f/w) or they didn't care wether we were sync or not.
+            o_selected_sync_mode = fapi2::ENUM_ATTR_MC_SYNC_MODE_NOT_IN_SYNC;
+            return fapi2::FAPI2_RC_SUCCESS;
             break;
 
         default:
@@ -242,6 +286,210 @@ fapi2::ReturnCode select_sync_mode(const std::map< fapi2::Target<TARGET_TYPE_MCB
     }// end switch
 
     return fapi2::FAPI2_RC_SUCCESS;
+
+#ifndef __HOSTBOOT_MODULE
+fapi_try_exit:
+    return fapi2::current_err;
+#endif
+}
+
+///
+/// @brief Create and sort a vector of supported MT/s (freq)
+/// @param[in] MCS target for which to get the DIMM configs
+/// @param[in,out] reference to a std::vector<uint32_t> space to put the sorted vector
+/// @return FAPI2_RC_SUCCESS iff ok
+/// @note Taken from ATTR_MSS_MRW_SUPPORTED_FREQ. The result is sorted so such that the min
+/// supported freq is std::vector<>.begin and the max is std::vector<>.end - 1. You can
+/// search the resulting vector for valid frequencies as it is sorted.
+///
+fapi2::ReturnCode supported_freqs(const fapi2::Target<TARGET_TYPE_MCS>& i_target, std::vector<uint32_t>& io_freqs)
+{
+    std::vector<uint32_t> l_freqs(NUM_VPD_FREQS, 0);
+    std::vector<uint32_t> l_max_freqs(NUM_MAX_FREQS, 0);
+    uint8_t l_req_sync_mode = 0;
+
+    FAPI_TRY( mss::mrw_supported_freq(l_freqs.data()) );
+    FAPI_TRY( mss::max_allowed_dimm_freq(l_max_freqs.data()) );
+    FAPI_TRY( mss::required_synch_mode(l_req_sync_mode) );
+
+    FAPI_INF("attribute supported freqs %d %d %d %d",
+             l_freqs[0], l_freqs[1], l_freqs[2], l_freqs[3]);
+
+    FAPI_INF("attribute supported max freqs %d %d %d %d %d",
+             l_max_freqs[0], l_max_freqs[1], l_max_freqs[2], l_max_freqs[3], l_max_freqs[4]);
+
+    FAPI_INF("attribute required sync mode %d", l_req_sync_mode);
+
+    FAPI_TRY( supported_freqs_helper(i_target,
+                                     l_freqs,
+                                     l_max_freqs,
+                                     l_req_sync_mode == fapi2::ENUM_ATTR_REQUIRED_SYNCH_MODE_ALWAYS,
+                                     io_freqs) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Create and sort a vector of supported MT/s (freq) - helper for testing purposes
+/// @param[in] MCS target for which to get the DIMM configs
+/// @param[in] vector of MVPD freqs
+/// @param[in] vector of max allowed freqs
+/// @param[in] bool whether or not we're forced into sync mode
+/// @param[in,out] reference to a std::vector<uint32_t> space to put the sorted vector
+/// @return FAPI2_RC_SUCCESS iff ok
+/// @note the attributes which drive this are read-only so they're hard to change when
+/// testing. So this helper allows us to use the attributes for the main path but
+/// have a path for testing (DFT I think the cool kids call it.)
+///
+fapi2::ReturnCode supported_freqs_helper(const fapi2::Target<TARGET_TYPE_MCS>& i_target,
+        const std::vector<uint32_t>& i_freqs,
+        const std::vector<uint32_t>& i_max_freqs,
+        const bool i_req_sync_mode,
+        std::vector<uint32_t>& io_freqs)
+{
+    // Indexes into the ATTR_MAX_ALLOWED_DIMM_FREQ arrary. e.g., [0][0] is 1R 1 drop
+    constexpr size_t l_indexes[MAX_DIMM_PER_PORT][MAX_PRIMARY_RANKS_PER_PORT] =
+    {
+        {0, 1, 0xFF, 2},
+        {3, 4, 0xFF, 0xFF}
+    };
+
+    // Holds the max freq allowed for this configuration of DIMMs. This is the minimum of maximum
+    // frequencies allowed by the DIMM. So, we start way off the charts so std::min can do the lifting for us.
+    uint32_t l_our_max_freq = ~(0);
+
+    io_freqs.clear();
+
+    // This magic number isn't the number of frequencies supported by the hardware, it's the number
+    // of frequencies in the attribute or VPD. They may be different (see *1 below)
+    if (i_freqs.size() != NUM_VPD_FREQS)
+    {
+        FAPI_ERR("incorrect number of frequencies for %s (%d)", mss::c_str(i_target), i_freqs.size());
+        fapi2::Assert(false);
+    }
+
+    FAPI_INF("unsorted supported freqs %d %d %d %d",
+             i_freqs[0], i_freqs[1], i_freqs[2], i_freqs[3]);
+
+    // (*1) This is the number of elelments in the max_allowed_dimm_freq attribute, not the frequencies of
+    // the system. Hence the magic number.
+    if (i_max_freqs.size() != NUM_MAX_FREQS)
+    {
+        FAPI_ERR("incorrect number of max frequencies for %s (%d)", mss::c_str(i_target), i_max_freqs.size());
+        fapi2::Assert(false);
+    }
+
+    FAPI_INF("max supported freqs %d %d %d %d %d",
+             i_max_freqs[0], i_max_freqs[1], i_max_freqs[2], i_max_freqs[3], i_max_freqs[4]);
+
+    // Given the max supported freqs, find the config based on our DIMMs. There's no great way to do this ...
+    for (const auto& p : mss::find_targets<TARGET_TYPE_MCA>(i_target))
+    {
+        const auto l_dimms = mss::find_targets<TARGET_TYPE_DIMM>(p);
+        uint64_t l_dimms_on_port = l_dimms.size();
+
+        // Just a quick check but we're in deep yogurt if this triggers
+        if (l_dimms_on_port > MAX_DIMM_PER_PORT)
+        {
+            FAPI_ERR("seeing %d DIMM on port %s", l_dimms_on_port, mss::c_str(p));
+            fapi2::Assert(false);
+        }
+
+        for (const auto& d : l_dimms)
+        {
+            uint8_t l_num_master_ranks = 0;
+            size_t l_index = 0xFF;
+
+            FAPI_TRY( mss::eff_num_master_ranks_per_dimm(d, l_num_master_ranks) );
+
+            // Just a quick check but we're in deep yogurt if this triggers
+            if (l_num_master_ranks > MAX_PRIMARY_RANKS_PER_PORT)
+            {
+                FAPI_ERR("seeing %d primary ranks on DIMM %s", l_num_master_ranks, mss::c_str(d));
+                fapi2::Assert(false);
+            }
+
+            FAPI_INF("%s rank config %d drop %d yields max freq attribute index of %d (%d)",
+                     mss::c_str(d), l_num_master_ranks, l_dimms_on_port,
+                     l_indexes[l_dimms_on_port - 1][l_num_master_ranks - 1],
+                     i_max_freqs[l_indexes[l_dimms_on_port - 1][l_num_master_ranks - 1]] );
+
+            l_index = l_indexes[l_dimms_on_port - 1][l_num_master_ranks - 1];
+
+            // Just a quick check but we're in deep yogurt if this triggers
+            if (l_index > NUM_MAX_FREQS)
+            {
+                FAPI_ERR("seeing %d index for %d DIMM and %d ranks on DIMM %s",
+                         l_index, l_dimms_on_port, l_num_master_ranks, mss::c_str(d));
+                fapi2::Assert(false);
+            }
+
+            l_our_max_freq = std::min(l_our_max_freq, i_max_freqs[l_index]);
+        }
+    }
+
+    FAPI_INF("after processing DIMM, max freq is %d", l_our_max_freq);
+
+    // We need to push things as the memcpy doesn't update the vector's count, etc. and we don't
+    // create the vector, we get it passed in. It's not a big deal as we want to touch all the elements
+    // to check for 0's anyway.
+    for (size_t i = 0; i < NUM_VPD_FREQS; ++i)
+    {
+        // Funky if-tree makes things clearer than a combinatorialy explosive conditional
+        if (i_freqs[i] == 0)
+        {
+            // Skip 0's
+            continue;
+        }
+
+        if (i_freqs[i] > l_our_max_freq)
+        {
+            // Skip freqs larger than our max
+            continue;
+        }
+
+        // Add this freq if we're not in sync mode, or, if we are add it if it matches a nest freq
+        if (!i_req_sync_mode || (i_req_sync_mode && (i_freqs[i] <= fapi2::ENUM_ATTR_MSS_FREQ_MT2400)))
+        {
+            io_freqs.push_back(i_freqs[i]);
+        }
+    }
+
+    // We now know io_freqs contains valid frequencies for this DIMM config, system contraints, and sync mode.
+    // Sort it so we know supported min is io_freq.begin and supported max is io_freq.end - 1
+    std::sort(io_freqs.begin(), io_freqs.end());
+
+    // If we have an empty set, we have a pro'lem
+    FAPI_ASSERT(io_freqs.size() != 0,
+                fapi2::MSS_VPD_FREQ_MAX_FREQ_EMPTY_SET()
+                .set_MSS_VPD_FREQ_0(i_freqs[0])
+                .set_MSS_VPD_FREQ_1(i_freqs[1])
+                .set_MSS_VPD_FREQ_2(i_freqs[2])
+                .set_MSS_VPD_FREQ_3(i_freqs[3])
+                .set_MSS_MAX_FREQ_0(i_max_freqs[0])
+                .set_MSS_MAX_FREQ_1(i_max_freqs[1])
+                .set_MSS_MAX_FREQ_2(i_max_freqs[2])
+                .set_MSS_MAX_FREQ_3(i_max_freqs[3])
+                .set_MSS_MAX_FREQ_4(i_max_freqs[4])
+                .set_REQUIRED_SYNC_MODE(i_req_sync_mode)
+                .set_MAX_FREQ_FROM_DIMM(l_our_max_freq)
+                .set_MCS_TARGET(i_target),
+                "%s didn't find a frequency which was in VPD and was allowable max", mss::c_str(i_target));
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Return whether a given freq is supported
+/// @param[in] a freq to check for
+/// @param[in] reference to a std::vector<uint32_t> of freqs
+/// @return bool, true iff input freq is supported
+///
+fapi2::ReturnCode is_freq_supported(const uint32_t i_freq, const std::vector<uint32_t>& i_freqs)
+{
+    return std::binary_search(i_freqs.begin(), i_freqs.end(), i_freq);
 }
 
 }// mss
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/freq/sync.H b/src/import/chips/p9/procedures/hwp/memory/lib/freq/sync.H
index 51a7fe83f..beae6c17a 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/freq/sync.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/freq/sync.H
@@ -49,12 +49,6 @@ enum class speed_equality : uint8_t
     EQUAL_DIMM_SPEEDS = 1,
 };
 
-enum class sync_mode : uint8_t
-{
-    MC_NOT_IN_SYNC =  0,
-    MC_IN_SYNC = 1,
-};
-
 ///
 /// @brief Retrieves a mapping of MSS frequency values per mcbist target
 /// @param[in] i_targets vector of controller targets
@@ -84,13 +78,54 @@ bool deconfigure(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target,
 /// @param[in] i_nest_freq nest frequency
 /// @param[in] i_required_sync_mode system policy to enforce synchronous mode
 /// @param[out] o_selected_sync_mode final synchronous mode
+/// @param[out] o_selected_freq final freq selected, only valid if final sync mode is in-sync
 /// @return FAPI2_RC_SUCCESS iff successful
 ///
 fapi2::ReturnCode select_sync_mode(const std::map< fapi2::Target<fapi2::TARGET_TYPE_MCBIST>, uint64_t >& i_freq_map,
                                    const speed_equality i_equal_dimm_speed,
                                    const uint32_t i_nest_freq,
                                    const uint8_t i_required_sync_mode,
-                                   sync_mode& o_selected_sync_mode);
+                                   uint8_t& o_selected_sync_mode,
+                                   uint64_t& o_selected_freq);
+
+///
+/// @brief Create and sort a vector of supported MT/s (freq) - helper for testing purposes
+/// @param[in] MCS target for which to get the DIMM configs
+/// @param[in] vector of MVPD freqs
+/// @param[in] vector of max allowed freqs
+/// @param[in] bool whether or not we're forced into sync mode
+/// @param[in,out] reference to a std::vector<uint32_t> space to put the sorted vector
+/// @return FAPI2_RC_SUCCESS iff ok
+/// @note Taken from ATTR_MSS_MRW_SUPPORTED_FREQ. The result is sorted so such that the min
+/// supported freq is std::vector<>.begin and the max is std::vector<>.end - 1. You can
+/// search the resulting vector for valid frequencies as it is sorted.
+///
+fapi2::ReturnCode supported_freqs_helper(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+        const std::vector<uint32_t>& i_freqs,
+        const std::vector<uint32_t>& i_max_freqs,
+        const bool i_req_sync_mode,
+        std::vector<uint32_t>& io_freqs);
+
+///
+/// @brief Create and sort a vector of supported MT/s (freq)
+/// @param[in] MCS target for which to get the DIMM configs
+/// @param[in,out] reference to a std::vector<uint32_t> space to put the sorted vector
+/// @return FAPI2_RC_SUCCESS iff ok
+/// @note Taken from ATTR_MSS_MRW_SUPPORTED_FREQ. The result is sorted so such that the min
+/// supported freq is std::vector<>.begin and the max is std::vector<>.end - 1. You can
+/// search the resulting vector for valid frequencies as it is sorted.
+///
+fapi2::ReturnCode supported_freqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+                                  std::vector<uint32_t>& io_freqs);
+
+///
+/// @brief Return whether a given freq is supported
+/// @param[in] a freq to check for
+/// @param[in] reference to a std::vector<uint32_t> of freqs
+/// @return bool, true iff input freq is supported
+///
+fapi2::ReturnCode is_freq_supported(const uint32_t i_freq, const std::vector<uint32_t>& i_freqs);
+
 
 }// mss
 
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
index f0e498b66..fbb0cf9b1 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
@@ -10596,31 +10596,6 @@ fapi_try_exit:
 }
 
 ///
-/// @brief ATTR_MSS_NEST_CAPABLE_FREQUENCIES getter
-/// @param[in] const ref to the TARGET_TYPE_MCBIST
-/// @param[out] uint64_t& reference to store the value
-/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  The NEST frequencies the memory chip can run at computed by the mss_freq. The
-/// possibilities are ORed together. The platform uses these value and the MRW to
-/// determine what frequency to boot the fabric (nest) if it can. There are two
-/// values: 8G and
-/// 9.6G
-///
-inline fapi2::ReturnCode nest_capable_frequencies(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target,
-        uint64_t& o_value)
-{
-
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_NEST_CAPABLE_FREQUENCIES, i_target, o_value) );
-    return fapi2::current_err;
-
-fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_NEST_CAPABLE_FREQUENCIES: 0x%lx (target: %s)",
-             uint64_t(fapi2::current_err), mss::c_str(i_target));
-    return fapi2::current_err;
-}
-
-///
 /// @brief ATTR_MSS_VOLT_OVERRIDE getter
 /// @param[in] const ref to the TARGET_TYPE_MCBIST
 /// @param[out] uint8_t& reference to store the value
@@ -19788,6 +19763,28 @@ fapi_try_exit:
     return fapi2::current_err;
 }
 
+///
+/// @brief ATTR_MSS_MRW_SUPPORTED_FREQ getter
+/// @param[out] uint32_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM A)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  List of memory frequencies supported by the current
+/// system.
+///
+inline fapi2::ReturnCode mrw_supported_freq(uint32_t* o_array)
+{
+    uint32_t l_value[4];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_SUPPORTED_FREQ, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_value) );
+    memcpy(o_array, &l_value, 16);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_MRW_SUPPORTED_FREQ: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
 
 ///
 /// @brief ATTR_MSS_VPD_MR_0_VERSION_LAYOUT getter
@@ -26221,6 +26218,1075 @@ fapi_try_exit:
 }
 
 
+///
+/// @brief ATTR_FREQ_PROC_REFCLOCK_KHZ getter
+/// @param[out] uint32_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  The frequency of the processor refclock in kHz. Provided by the Machine Readable
+/// Workbook. This can be overridden to adjust the refclock
+/// frequency.
+///
+inline fapi2::ReturnCode freq_proc_refclock_khz(uint32_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_FREQ_PROC_REFCLOCK_KHZ, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_FREQ_PROC_REFCLOCK_KHZ: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_FREQ_MEM_REFCLOCK getter
+/// @param[out] uint32_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  The frequency of the memory refclock in MHz. Provided by the Machine Readable
+/// Workbook. This is read by the set_ref_clock HWP to find out the desired
+/// frequency. This can be overridden to adjust the refclock
+/// frequency.
+///
+inline fapi2::ReturnCode freq_mem_refclock(uint32_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_FREQ_MEM_REFCLOCK, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_FREQ_MEM_REFCLOCK: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MAX_ALLOWED_DIMM_FREQ getter
+/// @param[out] uint32_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM A)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Maximum frequency (in MHz) that this system can run the DIMMs at. There are 5
+/// possible values determined by the dimm configuration. For configurations which
+/// have mixed rank configurations, the lowest frequency based on ranks of either
+/// DIMM is chosen. For example if there was a 1R and a 2R DIMM installed, and 1R
+/// dual drop was a lower max freq than 2R dual drop, then the 1R max freq would be
+/// the max allowed. [0]=One rank, single drop [1]=Two rank, single drop [2]=Four
+/// rank, single drop [3]=One rank, dual drop [4]=Two rank, dual drop A value of
+/// zero would indicate an unsupported configuration. Note: Do not use this
+/// attribute to limit configurations, it is not checked during plug rules. If you
+/// have an unsupported configuration, use the value 0 as the maximum
+/// freq.
+///
+inline fapi2::ReturnCode max_allowed_dimm_freq(uint32_t* o_array)
+{
+    uint32_t l_value[5];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MAX_ALLOWED_DIMM_FREQ, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_value) );
+    memcpy(o_array, &l_value, 20);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MAX_ALLOWED_DIMM_FREQ: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MEMVPD_POS getter
+/// @param[in] const ref to the TARGET_TYPE_MCS
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  The position of the MCS target's VPD selector data, relative to the EEPROM that
+/// contains its data. For systems with a single EEPROM for all chips, this should
+/// be equivalent to ATTR_FAPI_POS (the logical MCA position). For systems with an
+/// EEPROM per chip, this value should be equivalent to
+/// ATTR_CHIP_UNIT_POS.
+///
+inline fapi2::ReturnCode memvpd_pos(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEMVPD_POS, i_target, o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MEMVPD_POS: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_REQUIRED_SYNCH_MODE getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Specify the system policy to enforce synchronous mode between memory and nest.
+/// This drives the value of ATTR_MEM_IN_SYNCH_MODE. UNDETERMINED : Run
+/// synchronously if the dimm and nest freq matches ALWAYS : Require matching
+/// frequencies and deconfigure memory that does not match the nest NEVER : Do not
+/// run synchronously, even if the frequencies
+/// match
+///
+inline fapi2::ReturnCode required_synch_mode(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_REQUIRED_SYNCH_MODE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_REQUIRED_SYNCH_MODE: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+
+///
+/// @brief ATTR_IS_SIMULATION getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  env: 1 = Awan/HWSimulator. 0 =
+/// Simics/RealHW.
+///
+inline fapi2::ReturnCode is_simulation(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_IS_SIMULATION: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_EXECUTION_PLATFORM getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Which execution platform the HW Procedure is running on Some HWPs (e.g. special
+/// wakeup) use different registers for different platforms to avoid arbitration
+/// problems when multiple platforms do the same thing
+/// concurrently
+///
+inline fapi2::ReturnCode execution_platform(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EXECUTION_PLATFORM, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_EXECUTION_PLATFORM: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+
+///
+/// @brief ATTR_FREQ_PB_MHZ getter
+/// @param[out] uint32_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  The frequency of a processor's nest mesh clock, in MHz. This is the same for all
+/// chips in the system. Provided by the
+/// MRW.
+///
+inline fapi2::ReturnCode freq_pb_mhz(uint32_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_FREQ_PB_MHZ, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_FREQ_PB_MHZ: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_FREQ_A_MHZ getter
+/// @param[out] uint32_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  The frequency of a processor's A link clocks, in MHz. This is the same for all
+/// chips in the system. Provided by the
+/// MRW.
+///
+inline fapi2::ReturnCode freq_a_mhz(uint32_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_FREQ_A_MHZ, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_FREQ_A_MHZ: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_FREQ_X_MHZ getter
+/// @param[out] uint32_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  The frequency of a processor's X link clocks, in MHz. This is the same for all
+/// chips in the system. Provided by the
+/// MRW.
+///
+inline fapi2::ReturnCode freq_x_mhz(uint32_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_FREQ_X_MHZ, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_FREQ_X_MHZ: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_FREQ_CORE_FLOOR_MHZ getter
+/// @param[out] uint32_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  The lowest frequency that a core can be set to in MHz. This is the same for all
+/// cores in the system. Provided by the MVPD #V and is calculated as the max of the
+/// Power Save
+/// frequencies.
+///
+inline fapi2::ReturnCode freq_core_floor_mhz(uint32_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_FREQ_CORE_FLOOR_MHZ, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_FREQ_CORE_FLOOR_MHZ: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_FREQ_CORE_NOMINAL_MHZ getter
+/// @param[out] uint32_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  The nominal core frequency in MHz. This is the same for all cores in the system.
+/// Provided by the #V bucket of module
+/// VPD.
+///
+inline fapi2::ReturnCode freq_core_nominal_mhz(uint32_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_FREQ_CORE_NOMINAL_MHZ, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_FREQ_CORE_NOMINAL_MHZ: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_FREQ_CORE_CEILING_MHZ getter
+/// @param[out] uint32_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  The maximum core frequency in MHz. This is the same for all cores in the system.
+/// Provided by the #V bucket of module VPD and is calculated as the minimum of the
+/// turbo
+/// frequencies.
+///
+inline fapi2::ReturnCode freq_core_ceiling_mhz(uint32_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_FREQ_CORE_CEILING_MHZ, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_FREQ_CORE_CEILING_MHZ: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PM_SAFE_FREQUENCY_MHZ getter
+/// @param[out] uint32_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Frequency (in MHz) to move to if the Power Management function fails. This is
+/// the same for all cores in the system. Provided by the
+/// MRW.
+///
+inline fapi2::ReturnCode pm_safe_frequency_mhz(uint32_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PM_SAFE_FREQUENCY_MHZ, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PM_SAFE_FREQUENCY_MHZ: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_FREQ_PCIE_MHZ getter
+/// @param[out] uint32_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  The frequency of a processor's PCI-e bus in MHz. This is the same for all PCI-e
+/// busses in the system. Provided by the
+/// MRW.
+///
+inline fapi2::ReturnCode freq_pcie_mhz(uint32_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_FREQ_PCIE_MHZ, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_FREQ_PCIE_MHZ: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PROC_FABRIC_ASYNC_SAFE_MODE getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Set to force all fabric asynchronous boundary crossings into safe
+/// mode.
+///
+inline fapi2::ReturnCode proc_fabric_async_safe_mode(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_ASYNC_SAFE_MODE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PROC_FABRIC_ASYNC_SAFE_MODE: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PROC_FABRIC_A_BUS_WIDTH getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Processor SMP A bus width. Provided by the
+/// MRW.
+///
+inline fapi2::ReturnCode proc_fabric_a_bus_width(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_A_BUS_WIDTH, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PROC_FABRIC_A_BUS_WIDTH: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PROC_FABRIC_X_BUS_WIDTH getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Processor SMP X bus width. Provided by the
+/// MRW.
+///
+inline fapi2::ReturnCode proc_fabric_x_bus_width(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_X_BUS_WIDTH, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PROC_FABRIC_X_BUS_WIDTH: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PROC_FABRIC_CORE_FLOOR_RATIO getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Processor SMP core floor/nest frequency
+/// ratio
+///
+inline fapi2::ReturnCode proc_fabric_core_floor_ratio(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CORE_FLOOR_RATIO, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+                            o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PROC_FABRIC_CORE_FLOOR_RATIO: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PROC_FABRIC_CORE_CEILING_RATIO getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Processor SMP core celing/nest frequency
+/// ratio
+///
+inline fapi2::ReturnCode proc_fabric_core_ceiling_ratio(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CORE_CEILING_RATIO, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+                            o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PROC_FABRIC_CORE_CEILING_RATIO: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PROC_FABRIC_PUMP_MODE getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Processor SMP Fabric broadcast scope configuration. CHIP_IS_NODE = MODE1 =
+/// default CHIP_IS_GROUP = MODE2 Provided by the
+/// MRW.
+///
+inline fapi2::ReturnCode proc_fabric_pump_mode(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PROC_FABRIC_PUMP_MODE: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PROC_FABRIC_CCSM_MODE getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Processor SMP topology configuration. 0 = default = 1 or 2 hop topology (PHYP
+/// image spans system) 1 = 3 hop topology (PHYP image spans group). Provided by the
+/// MRW.
+///
+inline fapi2::ReturnCode proc_fabric_ccsm_mode(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CCSM_MODE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PROC_FABRIC_CCSM_MODE: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PROC_FABRIC_SMP_OPTICS_MODE getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Processor SMP optics mode. 0 = default = Optics_is_X_bus 1 = Optics_is_A_bus
+/// Provided by the
+/// MRW.
+///
+inline fapi2::ReturnCode proc_fabric_smp_optics_mode(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SMP_OPTICS_MODE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PROC_FABRIC_SMP_OPTICS_MODE: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PROC_FABRIC_CAPI_MODE getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Processor CAPI attachement protocol mode. 0 = default = no: SMPA CAPI
+/// attachement 1 = yes: SMPA CAPI attachement Provided by the
+/// MRW.
+///
+inline fapi2::ReturnCode proc_fabric_capi_mode(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CAPI_MODE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PROC_FABRIC_CAPI_MODE: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PROC_FABRIC_ADDR_BAR_MODE getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Processor memory map configuration. 0 = default = large system address map 1 =
+/// small system address map Provided by the
+/// MRW.
+///
+inline fapi2::ReturnCode proc_fabric_addr_bar_mode(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_ADDR_BAR_MODE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PROC_FABRIC_ADDR_BAR_MODE: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PROC_EPS_GB_PERCENTAGE getter
+/// @param[out] int8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Guardband percentage to apply to baseline epsilon calculations Set by
+/// p9_fbc_eff_config.
+///
+inline fapi2::ReturnCode proc_eps_gb_percentage(int8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_GB_PERCENTAGE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PROC_EPS_GB_PERCENTAGE: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PROC_EPS_TABLE_TYPE getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Processor epsilon table type. Used to calculate the processor nest epsilon
+/// register values. Provided by the
+/// MRW.
+///
+inline fapi2::ReturnCode proc_eps_table_type(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_TABLE_TYPE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PROC_EPS_TABLE_TYPE: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PROC_EPS_READ_CYCLES_T0 getter
+/// @param[out] uint32_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Calculated read tier0 epsilon protection
+/// count.
+///
+inline fapi2::ReturnCode proc_eps_read_cycles_t0(uint32_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T0, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PROC_EPS_READ_CYCLES_T0: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PROC_EPS_READ_CYCLES_T1 getter
+/// @param[out] uint32_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Calculated read tier1 epsilon protection
+/// count.
+///
+inline fapi2::ReturnCode proc_eps_read_cycles_t1(uint32_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T1, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PROC_EPS_READ_CYCLES_T1: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PROC_EPS_READ_CYCLES_T2 getter
+/// @param[out] uint32_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Calculated read tier2 epsilon protection
+/// count.
+///
+inline fapi2::ReturnCode proc_eps_read_cycles_t2(uint32_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T2, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PROC_EPS_READ_CYCLES_T2: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PROC_EPS_WRITE_CYCLES_T1 getter
+/// @param[out] uint32_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Calculated write tier1 epsilon protection
+/// count.
+///
+inline fapi2::ReturnCode proc_eps_write_cycles_t1(uint32_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PROC_EPS_WRITE_CYCLES_T1: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PROC_EPS_WRITE_CYCLES_T2 getter
+/// @param[out] uint32_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Calculated write tier2 epsilon protection
+/// count.
+///
+inline fapi2::ReturnCode proc_eps_write_cycles_t2(uint32_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T2, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PROC_EPS_WRITE_CYCLES_T2: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_DMI_REFCLOCK_SWIZZLE getter
+/// @param[in] const ref to the TARGET_TYPE_MCS
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Define DMI Ref clock/Swizzle for Centaur. Provided by the
+/// MRW
+///
+inline fapi2::ReturnCode dmi_refclock_swizzle(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_DMI_REFCLOCK_SWIZZLE, i_target, o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_DMI_REFCLOCK_SWIZZLE: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_SYSTEM_IPL_PHASE getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Define context for current phase of system
+/// IPL.
+///
+inline fapi2::ReturnCode system_ipl_phase(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_SYSTEM_IPL_PHASE: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_IS_MPIPL getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Indicates if current IPL is
+/// memory-preserving
+///
+inline fapi2::ReturnCode is_mpipl(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_MPIPL, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_IS_MPIPL: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET getter
+/// @param[out] uint64_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  XSCOM BAR base address offset creator: platform consumer: p9_sbe_scominit
+/// firmware notes: Defines 16GB range (size implied) mapped for XSCOM usage
+/// Attribute holds offset (relative to chip MMIO origin) to program into chip
+/// address range field of BAR -- RA bits 22:29 (excludes system/memory
+/// select/group/chip
+/// fields)
+///
+inline fapi2::ReturnCode proc_xscom_bar_base_addr_offset(uint64_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+                            o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET getter
+/// @param[out] uint64_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  LPC BAR base address offset creator: platform consumer: p9_sbe_scominit firmware
+/// notes: Defines 4GB range (size implied) mapped for LPC usage Attribute holds
+/// offset (relative to chip MMIO origin) to program into chip address range field
+/// of BAR -- RA bits 22:31 (excludes system/memory select/group/chip
+/// fields)
+///
+inline fapi2::ReturnCode proc_lpc_bar_base_addr_offset(uint64_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+                            o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MEM_MIRROR_PLACEMENT_POLICY getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Define placement policy/scheme for non-mirrored/mirrored memory layout NORMAL =
+/// non-mirrored start: 0, mirrored start: 1024TB FLIPPED = mirrored start: 0,
+/// non-mirrored start: 512TB Set by platform. Used by
+/// mss_eff_grouping.
+///
+inline fapi2::ReturnCode mem_mirror_placement_policy(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_MIRROR_PLACEMENT_POLICY, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MEM_MIRROR_PLACEMENT_POLICY: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_INTERLEAVE_ENABLE getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Used in the setting of groups. It is a bit vector. If the value BITWISE_AND 0x01
+/// = 0x01 then groups of 1 are enabled, if the value BITWISE_AND 0x02 = 0x02, then
+/// groups of 2 are possible, if the value BITWISE_AND 0x04 = 0x04, then group of 3
+/// are possible, if the value BITWISE_AND 0x08 = 0x08, then groups of 4 are
+/// possible, if the value BITWISE_AND 0x20 = 0x20, then groups of 6 are possible,
+/// if the value BITWISE_AND 0x80 = 0x80, then groups of 8 are possible. If no
+/// groups can formed according to this input, then an error will be thrown.
+/// Provided by the
+/// MRW
+///
+inline fapi2::ReturnCode mss_interleave_enable(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_INTERLEAVE_ENABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_INTERLEAVE_ENABLE: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MRW_HW_MIRRORING_ENABLE getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  TRUE : HW mirroring is enabled. FALSE : HW mirroring is disabled. Provided by
+/// the
+/// MRW.
+///
+inline fapi2::ReturnCode mrw_hw_mirroring_enable(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_HW_MIRRORING_ENABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MRW_HW_MIRRORING_ENABLE: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+
+///
+/// @brief ATTR_NEST_PLL_BUCKET getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Select Nest I2C and pll setting from one of the supported
+/// frequencies
+///
+inline fapi2::ReturnCode nest_pll_bucket(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_NEST_PLL_BUCKET, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_NEST_PLL_BUCKET: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_RISK_LEVEL getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  HWP/Init "risk level" enabled. Used by HB to pass to HB driven
+/// HWPs
+///
+inline fapi2::ReturnCode risk_level(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_RISK_LEVEL: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_DISABLE_HBBL_VECTORS getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  BootLoader HWP flag to not place 12K exception vectors. This flag is only
+/// applicable when security is
+/// disabled.
+///
+inline fapi2::ReturnCode disable_hbbl_vectors(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_DISABLE_HBBL_VECTORS, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_DISABLE_HBBL_VECTORS: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_BOOT_FLAGS getter
+/// @param[out] uint32_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Switch to using a flag to indicate SEEPROM side
+/// SBE
+///
+inline fapi2::ReturnCode boot_flags(uint32_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_BOOT_FLAGS, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_BOOT_FLAGS: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_SYS_FORCE_ALL_CORES getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Indicate that p9_sbe_select_ex should force selection to ALL good EX chiplets
+/// having good cores even if only a single EX chiplet mode is
+/// executed.
+///
+inline fapi2::ReturnCode sys_force_all_cores(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_SYS_FORCE_ALL_CORES, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_SYS_FORCE_ALL_CORES: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_SECURITY_ENABLE getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Holds the state of Security Access Bit
+/// (SAB)
+///
+inline fapi2::ReturnCode security_enable(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_SECURITY_ENABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_SECURITY_ENABLE: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_SECURITY_MODE getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  If SBE image has ATTR_SECURITY_MODE == 0b1, then leave SAB bit as is Else
+/// ATTR_SECURITY_MODE == 0b0, then clear the SAB
+/// bit
+///
+inline fapi2::ReturnCode security_mode(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_SECURITY_MODE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_SECURITY_MODE: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PIBMEM_REPAIR0 getter
+/// @param[out] uint64_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Pibmem repair attribute
+/// 0
+///
+inline fapi2::ReturnCode pibmem_repair0(uint64_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PIBMEM_REPAIR0, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PIBMEM_REPAIR0: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PIBMEM_REPAIR1 getter
+/// @param[out] uint64_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Pibmem repair attribute
+/// 1
+///
+inline fapi2::ReturnCode pibmem_repair1(uint64_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PIBMEM_REPAIR1, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PIBMEM_REPAIR1: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_PIBMEM_REPAIR2 getter
+/// @param[out] uint64_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Pibmem repair attribute
+/// 2
+///
+inline fapi2::ReturnCode pibmem_repair2(uint64_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PIBMEM_REPAIR2, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_PIBMEM_REPAIR2: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+
 }
 
 #endif
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C
index 03332ef27..fd04a1592 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C
@@ -379,6 +379,49 @@ fapi_try_exit:
 }
 
 ///
+/// @brief Determines & sets effective config for number of master ranks per dimm
+/// @param[in] i_target FAPI2 target
+/// @param[in] the SPD cache
+/// @return fapi2::FAPI2_RC_SUCCESS if okay
+/// @note This is done after the SPD cache is configured so that it can reflect the results of the
+/// factory and we don't need to worry about SPD versions. This is expressly different than the dram and dimm setters
+///
+static fapi2::ReturnCode master_ranks_per_dimm_setter(const fapi2::Target<TARGET_TYPE_DIMM>& i_target,
+        const std::shared_ptr<decoder>& i_pDecoder)
+{
+    const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
+    const auto l_mca = find_target<TARGET_TYPE_MCA>(i_target);
+
+    uint8_t l_decoder_val = 0;
+    fapi2::buffer<uint8_t> l_ranks_configed;
+    uint8_t l_attrs_master_ranks_per_dimm[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
+    uint8_t l_attrs_dimm_ranks_configed[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
+
+    // Get & update MCS attribute
+    FAPI_TRY( i_pDecoder->num_package_ranks_per_dimm(i_target, l_decoder_val) );
+    FAPI_TRY(eff_num_master_ranks_per_dimm(l_mcs, &l_attrs_master_ranks_per_dimm[0][0]));
+    FAPI_TRY(eff_dimm_ranks_configed(l_mcs, &l_attrs_dimm_ranks_configed[0][0]));
+
+    l_attrs_master_ranks_per_dimm[index(l_mca)][index(i_target)] = l_decoder_val;
+
+    // Set configed ranks. Set the bit representing the master rank configured (0 being left most.) So,
+    // a 4R DIMM would be 0b11110000 (0xF0). This is used by PRD.
+    FAPI_TRY( l_ranks_configed.setBit(0, l_decoder_val) );
+    l_attrs_dimm_ranks_configed[index(l_mca)][index(i_target)] = l_ranks_configed;
+
+    FAPI_INF( "%s Num Master Ranks %d, DIMM Ranks Configed 0x%x",
+              mss::c_str(i_target),
+              l_attrs_master_ranks_per_dimm[index(l_mca)][index(i_target)],
+              l_attrs_dimm_ranks_configed[index(l_mca)][index(i_target)] );
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, l_mcs, l_attrs_master_ranks_per_dimm) );
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_RANKS_CONFIGED, l_mcs, l_attrs_dimm_ranks_configed) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
 /// @brief       Object factory to select correct decoder
 /// @param[in]   i_target dimm target
 /// @param[in]   i_spd_data SPD data
@@ -534,13 +577,16 @@ fapi2::ReturnCode populate_decoder_caches( const fapi2::Target<TARGET_TYPE_MCS>&
             o_factory_caches.emplace( std::make_pair( pos(l_dimm), l_pDecoder ) );
         }
 
+        // Populate some of the DIMM attributes early. This allows the following code to make
+        // decisions based on DIMM information. Expressly done after the factory has decided on the SPD version
+        FAPI_TRY( master_ranks_per_dimm_setter(l_dimm, l_pDecoder) );
+
     }// end dimm
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
-
 ///
 /// @brief       Creates factory object & SPD data caches
 /// @param[in]   i_target the dimm target
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/index.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/index.H
index 35827be45..ea7569978 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/index.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/index.H
@@ -64,6 +64,12 @@ inline size_t index(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target)
     return mss::pos(i_target) % PORTS_PER_MCS;
 }
 
+template<>
+inline size_t index(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target)
+{
+    return mss::pos(i_target) % MCS_PER_MC;
+}
+
 ///
 /// @brief Return an attribute array index from a rank number
 /// @param[in] i_rank uint64_t a rank number DIMM0 {0, 1, 2, 3} DIMM1 {0, 1, 2, 3}
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
index af032751d..596c45b8d 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
@@ -65,28 +65,8 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS>
     // Caches
     FAPI_TRY( mss::spd::populate_decoder_caches(i_target, l_factory_caches) );
 
-    for( const auto& l_dimm : mss::find_targets<fapi2::TARGET_TYPE_DIMM>(i_target) )
-    {
-        const auto l_dimm_pos = mss::pos(l_dimm);
-
-        // TODO RTC:152390 Create function to do map checking on cached values
-        // Find decoder factory for this dimm position
-        auto l_it = l_factory_caches.find(l_dimm_pos);
-
-        FAPI_TRY( mss::check::spd::invalid_cache(l_dimm,
-                  l_it != l_factory_caches.end(),
-                  l_dimm_pos),
-                  "Failed to get valid cache (rank decoder)");
-
-        l_eff_config.iv_pDecoder = l_it->second;
-
-        // <sigh> This is a little hackery. We needed to decode the DIMM's master ranks, so we can decode the VPD
-        // for this entire MCS. Which means we need to re-do the cache find and check which stinks.
-        FAPI_TRY( l_eff_config.master_ranks_per_dimm(l_dimm) );
-    }
-
     // We need to decode the VPD. We don't do this in the ctor as we need
-    // the rank information and for that we need the SPD caches (which we get above.)
+    // the rank information and for that we need the SPD caches (which we get when we populate the cache.)
     // However, we need to do the VPD decode before the others so that they might
     // be able to use VPD information to make decisions about setting up eff attributes.
     FAPI_TRY( l_eff_config.decode_vpd(i_target),
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.C
index 562b797c2..953626b16 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.C
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.C
@@ -51,10 +51,14 @@
 #include <lib/utils/c_str.H>
 #include <lib/freq/cycle_time.H>
 #include <lib/utils/find.H>
+#include <lib/utils/count_dimm.H>
+#include <lib/utils/index.H>
+#include <lib/shared/mss_const.H>
 
 using fapi2::TARGET_TYPE_MCS;
 using fapi2::TARGET_TYPE_MCA;
 using fapi2::TARGET_TYPE_DIMM;
+using fapi2::TARGET_TYPE_MCBIST;
 using fapi2::FAPI2_RC_SUCCESS;
 
 extern "C"
@@ -67,77 +71,83 @@ extern "C"
     ///
     fapi2::ReturnCode p9_mss_freq( const fapi2::Target<TARGET_TYPE_MCS>& i_target )
     {
-        // Get cached decoder
-        std::map<uint32_t, std::shared_ptr<mss::spd::decoder> > l_factory_caches;
-        FAPI_TRY( mss::spd::populate_decoder_caches(i_target, l_factory_caches),
-                  "Failed to populate decoder cache");
+        // TODO RTC:161701 p9_mss_freq needs to be re-worked to work per-MC as it's hard
+        // (if not impossible) to know the appropriate freq if we don't have information
+        // for both MCS. Setting one to max freq doesn't work in the case of 0 DIMM as
+        // there is no check for other freq's and we end up setting the chosen freq to
+        // the default.
+        // So for now, iterate over all the MCBIST. This isn't great as we do this work
+        // twice for every MC. However, attribute access is cheap so this will suffice for
+        // the time being.
+
+        std::vector<uint64_t> l_min_dimm_freq(mss::MCS_PER_MC, 0);
+        std::vector<uint64_t> l_desired_cas_latency(mss::MCS_PER_MC, 0);
+
+        const auto& l_mcbist = mss::find_target<TARGET_TYPE_MCBIST>(i_target);
+
+        // If there are no DIMM, we can just get out.
+        if (mss::count_dimm(l_mcbist) == 0)
+        {
+            FAPI_INF("Seeing no DIMM on %s, no freq to set", mss::c_str(l_mcbist));
+            return FAPI2_RC_SUCCESS;
+        }
 
+        for (const auto& l_mcs : mss::find_targets<TARGET_TYPE_MCS>(l_mcbist))
         {
-            // instantiation of class that calculates CL algorithm
-            mss::cas_latency l_cas_latency(i_target, l_factory_caches);
-
-#if 0   // TK - encapsulated functionality left over from p8, how do we tackle this for p9?? -AAM
-            // left for reference
-
-            // TK - Need to add functionality for determining system setting based
-            // on system drop (e.g. single & dual drop) and configuration.
-            // How will we determine a system is single or dual drop?
-            // What will we do if there is dimm mixing?
-            // How does this affect tck timing ? - AAM
-
-            // TK - Need to incorporate code path for overrides
-            FAPI_TRY(mss::check_for_freq_override(l_target_mcbist,
-                                                  l_tCKmin),
-                     "Failed check for freq_override()");
-
-#endif
-            // We set this to a non-0 so we avoid divide-by-zero errors in the conversions which
-            // go from clocks to time (and vice versa.) We have other bugs if there was really
-            // no mt/s determined and there really is a DIMM installed, so this is ok.
-            // We pick the maximum frequency supported by the system as the default.
-            // TK remove this when we can ask the MRW for the fastest the system supports
-            uint64_t l_min_dimm_freq = fapi2::ENUM_ATTR_MSS_FREQ_MT2666;
-            uint64_t l_desired_cas_latency = 0;
-
-            if(l_cas_latency.iv_dimm_list_empty)
-            {
-                // Cannot fail out for an empty DIMM configuration
-                // So default values are set
-                FAPI_INF("DIMM list is empty! Setting default values for CAS latency and DIMM speed.");
-            }
-            else
+            const auto l_index = mss::index(l_mcs);
+
+            // Get cached decoder
+            std::map<uint32_t, std::shared_ptr<mss::spd::decoder> > l_factory_caches;
+            FAPI_TRY( mss::spd::populate_decoder_caches(l_mcs, l_factory_caches),
+                      "Failed to populate decoder cache");
+
             {
-                uint64_t l_tCKmin = 0;
+                // instantiation of class that calculates CL algorithm
+                mss::cas_latency l_cas_latency(l_mcs, l_factory_caches);
+
+                if(l_cas_latency.iv_dimm_list_empty)
+                {
+                    // Cannot fail out for an empty DIMM configuration, so default values are set
+                    FAPI_INF("DIMM list is empty! Setting default values for CAS latency and DIMM speed.");
+                }
+                else
+                {
+                    // We set this to a non-0 so we avoid divide-by-zero errors in the conversions which
+                    // go from clocks to time (and vice versa.) We have other bugs if there was really
+                    // no mt/s determined and there really is a DIMM installed, so this is ok.
+                    // We pick the maximum frequency supported by the system as the default.
+                    l_min_dimm_freq[l_index] = fapi2::ENUM_ATTR_MSS_FREQ_MT2666;
 
-                // Find CAS latency using JEDEC algorithm
-                l_cas_latency.find_CL(i_target,
-                                      l_desired_cas_latency,
-                                      l_tCKmin);
+                    uint64_t l_tCKmin = 0;
 
-                // Find dimm transfer speed from selected tCK
-                FAPI_TRY( mss::ps_to_freq(l_tCKmin, l_min_dimm_freq),
-                          "Failed ps_to_freq()");
+                    // Find CAS latency using JEDEC algorithm
+                    l_cas_latency.find_CL(l_mcs,
+                                          l_desired_cas_latency[l_index],
+                                          l_tCKmin);
 
-                FAPI_INF("DIMM speed from selected tCK: %d", l_min_dimm_freq);
+                    // Find dimm transfer speed from selected tCK
+                    FAPI_TRY( mss::ps_to_freq(l_tCKmin, l_min_dimm_freq[l_index]),
+                              "Failed ps_to_freq()");
 
-                FAPI_TRY(mss::select_supported_freq(l_min_dimm_freq),
-                         "Failed select_supported_freq()");
+                    FAPI_INF("DIMM speed from selected tCK: %d (%s)", l_min_dimm_freq[l_index], mss::c_str(l_mcs));
 
-                FAPI_INF("Selected DIMM speed from supported speeds: %d", l_min_dimm_freq);
+                    FAPI_TRY(mss::select_supported_freq(l_mcs, l_min_dimm_freq[l_index]),
+                             "Failed select_supported_freq() %s", mss::c_str(l_mcs));
 
-            }// end else
+                    FAPI_INF("Selected DIMM speed from supported speeds: %d", l_min_dimm_freq[l_index]);
 
-            // Set attributes
-            FAPI_TRY(mss::set_freq_attrs(i_target, l_min_dimm_freq),
-                     "Failed set_freq_attrs()");
+                }// end else
 
-            FAPI_TRY(mss::set_CL_attr(i_target, l_desired_cas_latency ),
+            } // close scope
+
+            FAPI_TRY(mss::set_CL_attr(l_mcs, l_desired_cas_latency[l_index] ),
                      "Failed set_CL_attr()");
 
-            FAPI_INF( "Final Chosen Frequency: %d",  l_min_dimm_freq);
-            FAPI_INF( "Final Chosen CL: %d",  l_desired_cas_latency);
+            FAPI_INF( "Final Chosen CL: %d (%s)",  l_desired_cas_latency[l_index], mss::c_str(l_mcs));
+        } // close for each mcs
 
-        }
+        FAPI_TRY(mss::set_freq_attrs(l_mcbist, l_min_dimm_freq),
+                 "Failed set_freq_attrs()");
 
     fapi_try_exit:
         return fapi2::current_err;
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.H
index 7e1862bd2..4050b06c2 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.H
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.H
@@ -98,26 +98,30 @@ fapi_try_exit:
 ///
 /// @brief      Sets frequency attributes
 /// @param[in]  i_target the controller target
-/// @param[in]  i_dimm_freq final selected dimm freq in MT/s
+/// @param[in]  i_dimm_freq vector of freqs selected dimm freq in MT/s
 /// @return     FAPI2_RC_SUCCESS iff ok
-/// @note       P9 Nimbus will support DMI speeds 16GB and 9.6GB
 ///
-inline fapi2::ReturnCode set_freq_attrs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
-                                        uint64_t i_dimm_freq)
+inline fapi2::ReturnCode set_freq_attrs(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target,
+                                        const std::vector<uint64_t>& i_dimm_freq)
 {
-    // TK - RIT, needsto be corrected
-    uint64_t l_nest_freq = 2;
-    const auto l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target);
+    // Find the minimum (but non-0) freq in the vector. If we see all 0's we'll write a 0. However,
+    // we shouldn't as the caller should have been dealing with no DIMM before we got here.
+    uint64_t l_final_freq = UINT64_MAX;
 
-    FAPI_INF("Setting freq attrs for %s", mss::c_str(i_target));
+    for (const auto l_freq : i_dimm_freq)
+    {
+        if (l_freq != 0)
+        {
+            l_final_freq = std::min(l_final_freq, l_freq);
+        }
+    }
+
+    // If we saw all 0's, write a 0.
+    l_final_freq = l_final_freq == UINT64_MAX ? 0 : l_final_freq;
 
-    // TK
-    //Update for P9, what do we do w/setting nest freq? - AAM
-    // how do we select nest freq if we even have to??
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_NEST_CAPABLE_FREQUENCIES, l_mcbist, l_nest_freq),
-              "Failed to set nest capable frequencies attribute" );
+    FAPI_INF( "Final Chosen Frequency: %d (%s)", l_final_freq, mss::c_str(i_target) );
 
-    FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_MSS_FREQ, l_mcbist, i_dimm_freq),
+    FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_MSS_FREQ, i_target, l_final_freq),
              "Failed to set mss freq attribute");
 
 fapi_try_exit:
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq_system.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq_system.C
index 428d73a5a..713dff705 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq_system.C
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq_system.C
@@ -43,6 +43,7 @@
 #include <lib/utils/count_dimm.H>
 #include <lib/freq/sync.H>
 
+
 using fapi2::TARGET_TYPE_SYSTEM;
 using fapi2::TARGET_TYPE_PROC_CHIP;
 using fapi2::TARGET_TYPE_MCBIST;
@@ -79,9 +80,17 @@ extern "C"
         std::map< fapi2::Target<TARGET_TYPE_MCBIST>, uint64_t > l_freq_map;
         uint32_t l_nest_freq = 0;
         uint8_t l_required_sync_mode = 0;
-        mss::sync_mode l_mc_in_sync;
+        uint8_t l_mc_in_sync = 0;
+        uint64_t l_selected_nest_freq = 0;
         mss::speed_equality l_equal_dimm_speed;
 
+        // Get nest freq && F/W attr that tells me if sync mode is required
+        // or if I have to figure that out
+        FAPI_TRY( mss::required_synch_mode(l_required_sync_mode) );
+        FAPI_TRY( mss::freq_pb_mhz(l_nest_freq) );
+
+        FAPI_INF("Retrieved req'd sync mode: %d and nest freq %d", l_required_sync_mode, l_nest_freq);
+
         // Populate dimm speed map
         FAPI_TRY( mss::dimm_speed_map(i_targets, l_freq_map, l_equal_dimm_speed),
                   "Failed to get dimm speed mapping" );
@@ -89,37 +98,34 @@ extern "C"
         FAPI_INF("Dimm speed for all MCBISTs are the same : %s",
                  uint8_t(l_equal_dimm_speed) ? "true" : "false");
 
-        // Get nest freq && F/W attr that tells me if sync mode is required
-        // or if I have to figure that out
-        FAPI_TRY( FAPI_ATTR_GET( fapi2::ATTR_REQUIRED_SYNCH_MODE,
-                                 fapi2::Target<TARGET_TYPE_SYSTEM>(),
-                                 l_required_sync_mode ) );
-
-        FAPI_TRY( FAPI_ATTR_GET( fapi2::ATTR_FREQ_PB_MHZ,
-                                 fapi2::Target<TARGET_TYPE_SYSTEM>(),
-                                 l_nest_freq) );
-
-        FAPI_INF("Retrieved req'd sync mode: %d and nest freq %d", l_required_sync_mode, l_nest_freq);
-
         // Select SYNCH mode
         FAPI_TRY( mss::select_sync_mode(l_freq_map,
                                         l_equal_dimm_speed,
                                         l_nest_freq,
                                         l_required_sync_mode,
-                                        l_mc_in_sync) );
+                                        l_mc_in_sync,
+                                        l_selected_nest_freq) );
 
-        FAPI_INF("Selected SYNC mode : %s", uint8_t(l_mc_in_sync) ? "MC in sync" : "MC NOT in sync");
+        FAPI_INF("Selected SYNC mode : %s",
+                 (l_mc_in_sync == fapi2::ENUM_ATTR_MC_SYNC_MODE_IN_SYNC) ? "MC in sync" : "MC NOT in sync");
 
-        // Set attribute
+        // Set attributes.
+        // set ATTR_FREQ_PB_MHZ based on sync logic
+        // set ATTR_MC_SYNC_MODE to 0 (not in sync) or 1 (in sync)
         for(const auto& l_mcbist : i_targets)
         {
+            // Convert from uint64_t to uint32_t for attribute macros
+            uint32_t l_pb_freq_value = l_selected_nest_freq;
             const auto& l_proc_chip = mss::find_target<TARGET_TYPE_PROC_CHIP>(l_mcbist);
 
-            // Cast converts enum class to uint8_t& expected for ATTR_SET
-            FAPI_TRY( FAPI_ATTR_SET( fapi2::ATTR_MC_SYNC_MODE,
-                                     l_proc_chip,
-                                     reinterpret_cast<uint8_t(&)>(l_mc_in_sync) ),
-                      "Failed to set ATTR_MC_SYNC_MODE");
+            FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MC_SYNC_MODE, l_proc_chip, l_mc_in_sync),
+                      "Failed to set ATTR_MC_SYNC_MODE" );
+
+            if (l_mc_in_sync == fapi2::ENUM_ATTR_MC_SYNC_MODE_IN_SYNC)
+            {
+                FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_FREQ_PB_MHZ, fapi2::Target<TARGET_TYPE_SYSTEM>(), l_pb_freq_value),
+                          "Failed to set ATTR_FREQ_PB_MHZ" );
+            }
         }
 
     fapi_try_exit:
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/freq_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/freq_attributes.xml
index 9d4a6e4f1..6d78a9b1b 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/freq_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/freq_attributes.xml
@@ -55,15 +55,22 @@
     <targetType>TARGET_TYPE_SYSTEM</targetType>
     <description>
       Maximum frequency (in MHz) that this system can run the DIMMs at.
-      There are 4 possible values determined by the dimm configuration.
+      There are 5 possible values determined by the dimm configuration.
+      For configurations which have mixed rank configurations, the lowest
+      frequency based on ranks of either DIMM is chosen. For example if
+      there was a 1R and a 2R DIMM installed, and 1R dual drop was a lower
+      max freq than 2R dual drop, then the 1R max freq would be the max allowed.
         [0]=One rank, single drop
         [1]=Two rank, single drop
-        [2]=One rank, dual drop
-        [3]=Two rank, dual drop
-      A value of zero would indicate an unsupported configuration.
+        [2]=Four rank, single drop
+        [3]=One rank, dual drop
+        [4]=Two rank, dual drop
+      A value of zero would indicate an unsupported configuration. Note: Do not
+      use this attribute to limit configurations, it is not checked during plug rules.
+      If you have an unsupported configuration, use the value 0 as the maximum freq.
     </description>
     <valueType>uint32</valueType>
-    <array>4</array>
+    <array>5</array>
     <platInit/>
   </attribute>
   <!-- ********************************************************************* -->
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
index 2b69e4374..14c667738 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
@@ -2119,22 +2119,6 @@
     </attribute>
 
     <attribute>
-        <id>ATTR_MSS_NEST_CAPABLE_FREQUENCIES</id>
-        <targetType>TARGET_TYPE_MCBIST</targetType>
-        <description>
-            The NEST frequencies the memory chip can run at computed by the mss_freq.
-            The possibilities are ORed together.  The platform uses these value and
-            the MRW to determine what frequency to boot the fabric (nest) if it can.
-            There are two values: 8G and 9.6G
-        </description>
-        <initToZero></initToZero>
-        <valueType>uint64</valueType>
-        <enum>8_0G = 1, 9_6G = 2</enum>
-        <writeable/>
-        <mssAccessorName>nest_capable_frequencies</mssAccessorName>
-    </attribute>
-
-    <attribute>
         <id>ATTR_MSS_VOLT_OVERRIDE</id>
         <targetType>TARGET_TYPE_MCBIST</targetType>
         <description>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml
index da2a6f4d4..63c8b4a04 100755
--- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml
@@ -442,4 +442,24 @@
     <mssAccessorName>mrw_dram_2n_mode</mssAccessorName>
   </attribute>
 
+  <attribute>
+    <id>ATTR_MSS_MRW_SUPPORTED_FREQ</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+      List of memory frequencies supported by the current system.
+    </description>
+    <valueType>uint32</valueType>
+    <array>4</array>
+    <platInit/>
+    <!-- Note, mirrors ATTR_MSS_FREQ -->
+    <enum>
+      MT1866 = 1866,
+      MT2133 = 2133,
+      MT2400 = 2400,
+      MT2666 = 2666
+    </enum>
+    <default> 1866, 2133, 2400, 2666 </default>
+    <mssAccessorName>mrw_supported_freq</mssAccessorName>
+  </attribute>
+
 </attributes>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
index 5e197d4ee..22182288a 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
@@ -293,6 +293,8 @@
   <valueType>uint8</valueType>
   <persistRuntime/>
   <writeable/>
+  <initToZero/>
+  <enum>IN_SYNC = 1, NOT_IN_SYNC = 0</enum>
 </attribute>
 
 <attribute>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_freq.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_freq.xml
index 2ccb46b50..7fd0c2d47 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_freq.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_freq.xml
@@ -99,10 +99,22 @@
       <priority>HIGH</priority>
     </callout>
     <deconfigure>
-      <target>MCS_TARGET</target>
+      <childTargets>
+        <parent>MCS_TARGET</parent>
+        <childType>TARGET_TYPE_DIMM</childType>
+      </childTargets>
     </deconfigure>
   </hwpError>
 
+  <!-- Cronus only error when we can't match DIMM speeds to sync mode -->
+  <hwpError>
+    <rc>RC_MSS_FAILED_SYNC_MODE</rc>
+    <description>
+      DIMM speeds are different and sync mode is required
+    </description>
+    <ffdc>NEST_FREQ</ffdc>
+  </hwpError>
+
   <!-- TK - Should this be FFDC or just return FAPI2_RC_FALSE? - AAM -->
   <hwpError>
     <rc>RC_MSS_UNSUPPORTED_FREQ_CALCULATED</rc>
@@ -124,5 +136,31 @@
     </deconfigure>
   </hwpError>
 
+  <hwpError>
+    <rc>RC_MSS_VPD_FREQ_MAX_FREQ_EMPTY_SET</rc>
+    <description>
+      When considering the frequencies in the VPD and the max supported
+      frequencies based on DIMM config, there are no applicable frequencies
+      remaining
+    </description>
+    <ffdc>MSS_VPD_FREQ_0</ffdc>
+    <ffdc>MSS_VPD_FREQ_1</ffdc>
+    <ffdc>MSS_VPD_FREQ_2</ffdc>
+    <ffdc>MSS_VPD_FREQ_3</ffdc>
+    <ffdc>MSS_MAX_FREQ_0</ffdc>
+    <ffdc>MSS_MAX_FREQ_1</ffdc>
+    <ffdc>MSS_MAX_FREQ_2</ffdc>
+    <ffdc>MSS_MAX_FREQ_3</ffdc>
+    <ffdc>MSS_MAX_FREQ_4</ffdc>
+    <ffdc>REQUIRED_SYNC_MODE</ffdc>
+    <ffdc>MAX_FREQ_FROM_DIMM</ffdc>
+    <callout>
+      <target>MCS_TARGET</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>MCS_TARGET</target>
+    </deconfigure>
+  </hwpError>
 
 </hwpErrors>
diff --git a/src/import/hwpf/fapi2/xml/attribute_info/system_attributes.xml b/src/import/hwpf/fapi2/xml/attribute_info/system_attributes.xml
index 62319993f..c4bea25df 100644
--- a/src/import/hwpf/fapi2/xml/attribute_info/system_attributes.xml
+++ b/src/import/hwpf/fapi2/xml/attribute_info/system_attributes.xml
@@ -46,15 +46,4 @@
     <platInit/>
   </attribute>
   <!-- ********************************************************************* -->
-  <attribute>
-    <id>ATTR_MEMVPD_FREQS_MHZ</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
-    <description>
-      List of memory frequencies supported by the current system.
-    </description>
-    <valueType>uint32</valueType>
-    <array>4</array>
-    <platInit/>
-  </attribute>
-  <!-- ********************************************************************* -->
 </attributes>
diff --git a/src/usr/targeting/common/genHwsvMrwXml.pl b/src/usr/targeting/common/genHwsvMrwXml.pl
index 983a2a143..589447457 100755
--- a/src/usr/targeting/common/genHwsvMrwXml.pl
+++ b/src/usr/targeting/common/genHwsvMrwXml.pl
@@ -2771,7 +2771,7 @@ sub generate_sys
 
     #TODO CQ:SW352246 Replace hardcoded defaults with MRW values
     print "    <attribute>
-      <id>MEMVPD_FREQS_MHZ</id>
+      <id>MSS_MRW_SUPPORTED_FREQ</id>
       <default>
         2133,
         2400,
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 913fe168e..cef38c4f6 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -10668,7 +10668,7 @@ firmware notes: Used as override attribute for pstate procedure
 
 <!--TOOD RTC: 151938 Make sure that these are set up by parseMRW script-->
 <attribute>
-    <id>MEMVPD_FREQS_MHZ</id>
+    <id>MSS_MRW_SUPPORTED_FREQ</id>
     <description>
     List of memory frequencies supported by the current system.
     </description>
@@ -10681,7 +10681,7 @@ firmware notes: Used as override attribute for pstate procedure
     <persistency>non-volatile</persistency>
     <readable/>
     <hwpfToHbAttrMap>
-        <id>ATTR_MEMVPD_FREQS_MHZ</id>
+        <id>ATTR_MSS_MRW_SUPPORTED_FREQ</id>
         <macro>DIRECT</macro>
     </hwpfToHbAttrMap>
 </attribute>
@@ -19124,17 +19124,23 @@ Measured in GB</description>
     <id>MAX_ALLOWED_DIMM_FREQ</id>
     <description>
       Maximum frequency (in MHz) that this system can run the DIMMs at.
-      There are 4 possible values determined by the dimm configuration.
+      There are 5 possible values determined by the dimm configuration.
+      For configurations which have mixed rank configurations, the lowest
+      frequency based on ranks of either DIMM is chosen. For example if
+      there was a 1R and a 2R DIMM installed, and 1R dual drop was a lower
+      max freq than 2R dual drop, then the 1R max freq would be the max allowed.
       [0]=One rank, single drop
       [1]=Two rank, single drop
-      [2]=One rank, dual drop
-      [3]=Two rank, dual drop
+      [2]=Four rank, single drop
+      [3]=One rank, dual drop
+      [4]=Two rank, dual drop
       A value of zero would indicate an unsupported configuration.
     </description>
     <simpleType>
         <uint32_t>
+            <default>2400,2400,2400,2400,2400</default>
         </uint32_t>
-        <array>4</array>
+        <array>5</array>
     </simpleType>
     <hwpfToHbAttrMap>
         <id>ATTR_MAX_ALLOWED_DIMM_FREQ</id>
diff --git a/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml b/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml
index 221547a8e..56f0ed6ea 100644
--- a/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml
@@ -101,6 +101,10 @@
         <id>FREQ_PB_MHZ</id>
         <default>0x7D0</default>
     </attribute>
+    <attribute>
+        <id>REQUIRED_SYNCH_MODE</id>
+        <default>2</default><!-- NEVER -->
+    </attribute>
      <attribute>
         <id>PAYLOAD_BASE</id>
         <!-- Value of 0x0 for standalone systems, no payload to start -->
@@ -127,7 +131,7 @@
         <default>EPS_TYPE_LE</default>
     </attribute>
     <attribute>
-      <id>MEMVPD_FREQS_MHZ</id>
+      <id>MSS_MRW_SUPPORTED_FREQ</id>
       <default>
         2133,
         2400,
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 1ac64aa7a..83e2b4c4e 100755
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -576,7 +576,7 @@
     </attribute>
     <attribute><id>HB_HRMOR_NODAL_BASE</id></attribute>
     <attribute><id>TPM_REQUIRED</id></attribute>
-    <attribute><id>MEMVPD_FREQS_MHZ</id></attribute>
+    <attribute><id>MSS_MRW_SUPPORTED_FREQ</id></attribute>
     <!-- Max/min config attributes -->
     <attribute><id>MAX_PROC_CHIPS_PER_NODE</id></attribute>
     <attribute><id>MAX_EXS_PER_PROC_CHIP</id></attribute>
diff --git a/src/usr/targeting/common/xmltohb/vbu_NIMBUS.system.xml b/src/usr/targeting/common/xmltohb/vbu_NIMBUS.system.xml
index ba76e51b5..41d4a6c54 100644
--- a/src/usr/targeting/common/xmltohb/vbu_NIMBUS.system.xml
+++ b/src/usr/targeting/common/xmltohb/vbu_NIMBUS.system.xml
@@ -131,7 +131,7 @@
         <default>EPS_TYPE_LE</default>
     </attribute>
     <attribute>
-      <id>MEMVPD_FREQS_MHZ</id>
+      <id>MSS_MRW_SUPPORTED_FREQ</id>
       <default>
         1866,
         2133,