Add RTC to remind us to allow sending readSeeprom op to slave SBE

There was some issues sending readSeeprom commands to the slave
SBE while hostboot was running out of master core's cache and the
LPC bars that were used for initial IPL have been reset. This
commit adds a TODO in the code so we will come back and allow this
once we alter the design to allow this

Change-Id: Icd592d43d14706c0f198bc5ad5a50bc5abaccfb7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49601
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 8 insertions, 0 deletions

diff --git a/src/usr/sbe/sbe_update.C b/src/usr/sbe/sbe_update.C
index 02cade5ac..bb23872d7 100644
--- a/src/usr/sbe/sbe_update.C
+++ b/src/usr/sbe/sbe_update.C
@@ -1887,6 +1887,8 @@ namespace SBE
 
             // If the current seeprom is side 0 and is on master proc,
             // then attempt read via chipOp
+            // TODO RTC: 182266 Remove is_master conditional once we figure out
+            //      how we can write to master cache from slave SBE
             if (l_sideZeroIsActive && io_sbeState.target_is_master)
             {
                 err = getSeepromSideVersionViaChipOp(io_sbeState.target,
@@ -1923,6 +1925,8 @@ namespace SBE
 
             //If side 0 is not active, or this is a slave proc, or there was
             //an error trying to read the primary via chipOp, then try reading via I2C
+            // TODO RTC: 182266 Remove is_master conditional once we figure out
+            //      how we can write to master cache from slave SBE
             if(!l_sideZeroIsActive || !l_sbeSupportedSeepromReadOp ||
                 l_errFoundDuringChipOp|| !io_sbeState.target_is_master)
             {
@@ -1955,6 +1959,8 @@ namespace SBE
             //If side 1 is active and this is master, then attempt read via chipOp
             //Note that there is no reason to attempt chipOp on backup if it failed
             //on the primary.
+            // TODO RTC: 182266 Remove is_master conditional once we figure out
+            //      how we can write to master cache from slave SBE
             if (!l_sideZeroIsActive && l_sbeSupportedSeepromReadOp &&
                 !l_errFoundDuringChipOp && io_sbeState.target_is_master)
             {
@@ -1992,6 +1998,8 @@ namespace SBE
 
             //If side 1 is not active, or this is a slave proc,  or there was
             //an error trying to read the primary via chipOp, then try reading via I2C
+            // TODO RTC: 182266 Remove is_master conditional once we figure out
+            //      how we can write to master cache from slave SBE
             if(l_sideZeroIsActive || !l_sbeSupportedSeepromReadOp ||
                 l_errFoundDuringChipOp || !io_sbeState.target_is_master)
             {