Story 180760 - Use self restore API to disable ATTN in HID ...

during istep 15/16 of HCODE build/execution

Change-Id: I63f54cdc35b3ff7e68120a07c142b6a557257854
RTC: 180760
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49070
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>

4 files changed, 35 insertions, 0 deletions

diff --git a/src/include/arch/ppc.H b/src/include/arch/ppc.H
index 2e338ce36..a4c3afbed 100644
--- a/src/include/arch/ppc.H
+++ b/src/include/arch/ppc.H
@@ -356,6 +356,14 @@ inline uint64_t getPSSCR()
 }
 
 ALWAYS_INLINE
+inline uint64_t getHID()
+{
+    register uint64_t hid = 0;
+    asm volatile("mfspr %0, 1008" : "=r" (hid));
+    return hid;
+}
+
+ALWAYS_INLINE
 inline size_t getCacheLineBytes()
 {
     return 128;
diff --git a/src/include/sys/misc.h b/src/include/sys/misc.h
index cf8b6a93b..8255aa3b5 100644
--- a/src/include/sys/misc.h
+++ b/src/include/sys/misc.h
@@ -190,6 +190,7 @@ enum CpuSprNames
     CPU_SPR_MSR,
     CPU_SPR_LPCR,
     CPU_SPR_HRMOR,
+    CPU_SPR_HID,
 };
 
 /** @fn cpu_spr_value
diff --git a/src/kernel/syscall.C b/src/kernel/syscall.C
index 580b30d84..5245705d4 100644
--- a/src/kernel/syscall.C
+++ b/src/kernel/syscall.C
@@ -735,6 +735,10 @@ namespace Systemcalls
                 TASK_SETRTN(t, getHRMOR());
                 break;
 
+            case CPU_SPR_HID:
+                TASK_SETRTN(t, getHID());
+                break;
+
             default:
                 TASK_SETRTN(t, -1);
                 break;
diff --git a/src/usr/isteps/istep15/host_build_stop_image.C b/src/usr/isteps/istep15/host_build_stop_image.C
index 958e8fbfe..630517611 100644
--- a/src/usr/isteps/istep15/host_build_stop_image.C
+++ b/src/usr/isteps/istep15/host_build_stop_image.C
@@ -30,6 +30,7 @@
 #include    <sys/mm.h>
 #include    <usr/vmmconst.h>
 #include    <arch/pirformat.H>
+#include    <arch/ppc.H>
 #include    <isteps/pm/pm_common_ext.H>
 #include    <config.h>
 
@@ -62,6 +63,7 @@
 #include    <p9_infrastruct_help.H>
 #include    <p9_hcode_image_defines.H>
 #include    <p9_xip_section_append.H>
+#include    <p9n2_quad_scom_addresses_fld.H>
 
 using   namespace   ERRORLOG;
 using   namespace   ISTEP;
@@ -183,6 +185,9 @@ errlHndl_t  applyHcodeGenCpuRegs(  TARGETING::Target *i_procChipTarg,
     //look up the HRMOR value from the HRMOR CPU special purpose register(SPR)
     uint64_t    l_hrmorVal  =   cpu_spr_value(CPU_SPR_HRMOR);
 
+    // create a mask to represent the ATTN enable bit in the HID register
+    uint64_t  l_enblAttnMask = 0x8000000000000000ull >> P9N2_C_HID_EN_ATTN;
+
     //iterate through the cores while copying information from SPRs
     for (const auto & l_core: l_coreIds)
     {
@@ -256,6 +261,23 @@ errlHndl_t  applyHcodeGenCpuRegs(  TARGETING::Target *i_procChipTarg,
                 l_failAddr = P9_STOP_SPR_HRMOR;
                 break;
             }
+
+            //Call p9_stop_save_cpureg to store the HID SPR value
+            //  (minus ATTN enable bit)
+            uint64_t l_curHidVal =  cpu_spr_value( CPU_SPR_HID );
+            uint64_t l_hidVal = l_curHidVal & (~(l_enblAttnMask));
+            l_rc = p9_stop_save_cpureg( io_image,
+                                        P9_STOP_SPR_HID,
+                                        l_hidVal,
+                                        l_pirVal | l_fuseAdj);
+
+            if ( l_rc ){
+                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                           "ERROR: HID: core=0x%x,thread=0x%x,l_rc=0x%x",
+                           l_coreId, l_threadId, l_rc );
+                l_failAddr = P9_STOP_SPR_HID;
+                break;
+            }
         }
 
         //  fill in lpcr for each thread