talos-hostboot/src/usr/sbe, branch 07-25-2019

Automatically include config.h

2019-12-06T16:28:47+00:00

Rather than having to remember to include config.h anywhere we reference a CONFIG variable (and usually forgetting), this adds it to the default compiler flags so that it gets included in every source file we build. Change-Id: I53622ab4d46c55d942e98cae6ec03049fd5b3d08 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/87475 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Zachary Clark Reviewed-by: Roland Veloz Reviewed-by: Christian R Geddes Reviewed-by: Nicholas E Bofferding

Corrected bad logic, in an if statement, that was creating a bad trace

2019-05-07T14:01:37+00:00

Corrected bad logic that was NOT guarding a check for when the procIOMask did not match the coreMask: Old logic: if ( (NULL == err) && (procIOMask == coreMask)) { ... } else if ( procIOMask != coreMask ) <-- bad logic { ... } <--- produced bad/confusing trace else { ... } New logic: if (nullptr == err ) { if (procIOMask == coreMask) { ... } else <-- good logic to guard (procIOMask != coreMask) with if (nullptr == err ) { ... } <--- trace is no longer confusing } else { ... } Change-Id: Ic852e1e4c670b021b48354efbdc51bd1a009115c CQ:SW464063 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76840 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Nicholas E. Bofferding Reviewed-by: Ilya Smirnov Reviewed-by: Daniel M. Crowell

Modify PNOR load order in SBE update to avoid OOM condition

2019-02-26T15:52:45+00:00

Changed the order and lifetime of the various PNOR section loads that happen inside the SBE update flow to reduce the overlap as much as possible. SBE_IPL and HBBL will be loaded, consumed, then unloaded. Then after that HCODE will get loaded, consumed, and unloaded. Change-Id: Icf30d0313cf326e3e7b3f1f5a6614c76d1e75e91 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72453 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Matt Derksen Reviewed-by: Daniel M. Crowell Reviewed-by: Michael Baiocchi Reviewed-by: William G. Hoffa

Add new path in EEPROM device op to allow reading from new EECACHE

2019-02-16T15:10:13+00:00

Recently a new EECACHE section was introduced to Hostboot. This section gets populated with a copy of every PRIMARY_VPD eeprom (someday could contain other eeprom roles also) during host_discover_targets. This commit add support to allow users to select where they want to perform their EEPROM device operation. If they pass CACHE to the deviceOp macro then a read will come from the pnor cache, writes will write to pnor cache and then also write to the eeprom HW. If HARDWARE is passed in then reads and writes will be directly done on the eeprom hardware. If AUTOSELECT is passed the code will check our cache to see if we have a copy of the eeprom in question, if we have a copy we will go the CACHE path, if no copy exists we will go the HARDWARE path. Along with this change some reorganization was done w/ the eeprom related files. RTC: 196805 Change-Id: If2c4e5d3e338a1a10780740c1a019eb4af003b73 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70822 Reviewed-by: Matt Derksen Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Roland Veloz Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell

Create error log and fail if Proc's EC is found to be 0x0

2018-11-27T19:10:41+00:00

While looking up the SBE version we will look at the processor's EC level to determine how to lookup the version. If we find that the EC level is 0 then something went wrong. In HW the register describing the procs EC will always be fused to some non-zero so we shouldnt see this in HW , in simics if this happens it is likely because simics has not implemented this register yet. Change-Id: I24bc0caaf3d2c9a574943ca07069bd6fb99cf1a6 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68804 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Matt Derksen Reviewed-by: William G. Hoffa Reviewed-by: Ilya Smirnov Reviewed-by: Daniel M. Crowell

Only allow key transition in istep 10.2

2018-11-15T19:58:29+00:00

In certain cases, if a key transition driver was booted and the nest frequency had to be updated, the key transition flow would erroneously activate in istep 7.3 (call_mss_freq). This change confines key transitioning to istep 10.2 Change-Id: I450703e21bf68644298f77fcdfca62eae5c667e4 CQ: SW451376 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68685 Tested-by: Jenkins Server Reviewed-by: Michael Baiocchi Reviewed-by: Daniel M. Crowell

Serialize all attribute synchronization calls

2018-10-17T13:18:29+00:00

Forces all FSP attribute synchronizations down to FSP to serialize in the attribute resource provider attribute synchronization daemon thread to avoid concurrenty problems. Change-Id: Ifb355ba6f42872465ea3d6f0d9009cfd6f768d7a CQ: SW448280 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67450 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell

Revert "P10 prep: Infrastructure (IS) ring Id metadata and API changes"

2018-10-15T13:48:17+00:00

This reverts commit 52b76be222254e59959db984606c09dae854270b. Accidental merge before ekb was complete. Change-Id: I59412ecad661596322aaba5cb5cf83190727d64f Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67455 Reviewed-by: Daniel M. Crowell Tested-by: Daniel M. Crowell

P10 prep: Infrastructure (IS) ring Id metadata and API changes

2018-10-14T18:05:32+00:00

Gerrit intent: - Applicable for P9 merge (co-req NOT required) - Co-req not req'd for any tests Includes the following changes: - Accommodates initCompiler's needs for additional ring Id APIs to retrieve IS's key ring identifiers, ringId and ringClass, and to align with our enumerated chipId - Elimination of redundancy in and reorg of IS's ring Id lists: RingProperties, GenRingIdList (gone) and ChipletData. - GenRingIdList has been removed. - Expand RingProperties to also include scanScomAddr and ringClass. - Member of ring and chiplet properties structs have been renamed in consistent camel style (no longer using "iv_" anywhere). - Note that with "infrastructure (IS)" we here mean the core infrastructure codes that directly interact with and affect the image. Key_Cronus_Test=XIP_REGRESS Change-Id: I7e92af04edd10c0994718e476f6e7b77c5d124d6 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/59087 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell

Account for mixed procs in compatibility mode

2018-08-21T19:29:46+00:00

Current code enforces the same EC level for all processors in the system. However, this breaks compatibility mode for P9C 1.2/1.3 and P9N 2.2/2.3. Added code to allow these to pass the EC check when mixing parts Change-Id: Ie013d94dfdee3627911f4afbec5f65d5ce984227 CQ:SW442691 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64823 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell