talos-hostboot/src/usr/lpc, branch master

Add support for LPC error detection and recovery

2017-09-18T19:50:35+00:00

Change-Id: Iea9bd4425aeb798acd85484402c627fb623cae94 Also-By: Matt Ploetz RTC: 133649 RTC: 134582 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45397 Reviewed-by: Christian R. Geddes Reviewed-by: Prachi Gupta Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell

Fix off-by-one error in LPC driver for pnor mbox windows

2017-08-17T15:32:59+00:00

Found a bug where we fail if we use a window all the way up to the edge of the allocated window. Change-Id: I1e663089a3ba6b2e4d9a7dbc67ae98db0fd2524e CQ: SW398471 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44703 Reviewed-by: Prachi Gupta Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell

Bringup memory remapping Fix LPC and XSCOM BAR asserts

2017-07-26T04:10:10+00:00

The LPC and XSCOM BAR values are checked and an assert coded in the failure leg. The condition for these asserts is being fixed. Also the LPC BAR check is being fixed to subtract out the start offset. Change-Id: I09f9989a51f6581c5b12a4a5057a4fcfa3412566 RTC:149250 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43286 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Matt Derksen Reviewed-by: Christian R. Geddes Reviewed-by: Daniel M. Crowell

Update LPC DD to set it's bar based upon what SBE tell us LPC bar is

2017-06-06T02:24:07+00:00

Previously the value of the BARS was hard coded. We want to be able to handle swapped memory. We will always just use what the SBE tells us to use as LPC bar from now on. Change-Id: I104463926c19763bd0bde8a0fd68ef3060157fe2 RTC: 173521 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41202 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Tested-by: Jenkins OP Build CI Reviewed-by: Martin Gloff Reviewed-by: Corey V. Swenson Reviewed-by: Daniel M. Crowell

Map BAR attributes based on data from Bootloader

2017-06-02T13:23:59+00:00

If the master processor has no memory behind it the entire memory map must be modified. Each processor has its own statically defined map that covers both memory and MMIOs. If the master has no memory, its memory map is swapped with another processor. Each processor gets a new effective fabric id that is then used to compute all of the BAR values for those processors. The SBE boots with a certain memory map programmed into the master processor. That value is then passed up through the bootloader into Hostboot. This value is compared to the BAR values that Hostboot assumes it is using. Based on that comparison, various attributes are computed to match the effective fabric positions. Change-Id: I2b0d1959c303df8c9c28c8f0a5b5be1e77aa154f RTC: 173528 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40359 Tested-by: Daniel M. Crowell Reviewed-by: Martin Gloff Reviewed-by: Christian R. Geddes Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: William G. Hoffa

Clean up of devdesc in hostboot code

2017-05-22T19:32:12+00:00

Change-Id: I252b9bffe2ff66d700c82f090b2d3bb21c1e570f RTC:118001 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40558 Reviewed-by: William G. Hoffa Tested-by: Jenkins Server Reviewed-by: Prachi Gupta Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Matthew A. Ploetz

lpc: Add support for large read/write ops

2017-05-02T14:34:38+00:00

On P9 the LPC is memory mapped. The LPC FW space used to map the flash is generally acccessed to read or write rather large amounts of data. Its inefficient to go through the whole dispatch and locking for every single 4 bytes read or written. This adds the ability to request reads or writes of larger quantities for FW space. The implementation uses memcpy whose current implementation in HostBoot will perform well for 8 bytes aligned accesses, but will downgrate to bytes accesses otherwise. Change-Id: I9770f22da99d1e1b917f4ba2101d459483f1dee1 Signed-off-by: Benjamin Herrenschmidt Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39386 Tested-by: Jenkins Server Reviewed-by: Dean Sanner Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Christian R. Geddes Reviewed-by: Daniel M. Crowell

XSCOM/LPC Workaround for Nimbus DD1

2017-02-16T19:31:39+00:00

There is a shared resource between the XSCOM and LPC logic that leads to errors at the XSCOM level causing errors to be detected during LPC operations. This commit adds an external interface to access block LPC operations while an XSCOM operation is in flight. Change-Id: I571094dfb666aa9198fabec5280a0f45c62c90ba RTC: 167291 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36399 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Thi N. Tran Reviewed-by: Dean Sanner Reviewed-by: Daniel M. Crowell

Pnor DD Changes for AST2500

2016-10-31T19:49:47+00:00

- Created Common sfc_ast2X000 class for common functions - Modified sfc_ast2400 class to use common class - Added sfc_ast2500 class Change-Id: I27c7674b58e006801ae03aabd60fdcfa21f49e9c RTC: 161664 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30919 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell Reviewed-by: Elizabeth K. Liner Reviewed-by: Matthew A. Ploetz

FFS Support for Bootloader

2016-03-03T21:17:52+00:00

This commit moves functionality out of pnor_common.C and puts it in a new file pnor_utils.C this file will be shared with bootloader and hostboot code. Quite a few files were pulled apart in order to make includes easier across modules. These are lpc_const.H and pnor_const.H. bl_pnorAccess leverages the new pnor_utils.C file that will help the bootloader parse pnor TOC Change-Id: I740f6f8a707760756a261535e62e2d0a849324f8 RTC:134064 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/696 Tested-by: Jenkins Server Reviewed-by: Martin Gloff Reviewed-by: Daniel M. Crowell Reviewed-by: William G. Hoffa