talos-hostboot/src/usr/intr, branch master

FFDC enhancements for core activate fails

2018-05-19T21:56:42+00:00

Adding some more traces to the error log we grab for core activation failures. Change-Id: I30c6985060fcffcb3382b775a52e59c08d2b51b7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57907 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Matt Derksen Reviewed-by: Daniel M. Crowell

Implement Interrupt Resource Provider Init for MPIPL Multi-Node Systems

2018-05-07T20:18:19+00:00

- In MPIPL the HW interrupt config could be such that interrupts will cross node boundaries. HB handles interrupts independently on each node - so initialize INTRP in a way to handle this transition. - Modify the MPIPL flow with the following changes: a) Set the Interrupt LSI State Machine to disabled b) Enable LSI Mode via the Interrupt Control Register c) Force all nodes to sync after steps a + b - Enable INTRP Multi-Node MPIPL Sync Code developed in P8 - Each node will now initialize its own internode_info data area during an initial IPL - Coalescing of the Host will modify this data to define all the nodes in the system - During the MPIPL each node can view each others area to determine when all nodes have reached the common sync point - Remove Legacy P8 MPIPL INTRP Code that is not used Change-Id: Idb742eafc7389f328ea7f506c4c4541c989e52b6 RTC: 182712 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57993 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Reviewed-by: Prachi Gupta Tested-by: Jenkins OP HW Reviewed-by: Christian R. Geddes Reviewed-by: Richard J. Knight Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell

Use the effective chip and group ids to calc mmio addr

2018-05-07T13:52:34+00:00

-A testcase was executed which garded out all the MBA's in the system, the expectation was that hostboot would attempt to configure enough hardware in the system to successfully ipl. However instead of IPLing multiple checkstops and various error logs were observed. -The testcase to gard all the mba's and then ipl the system resulted in there being no useable memory available for the master proc (proc0). In this case there is code which will swap the memory map around such that the sytem can still IPL. One of the requirements to enable the ability to swap the memory map around is to use the effective chip and group ids for calculating the memory ranges. -When setting the inband scom address for the DMI targets the existing calulation is using the default fabric chip group ids, this commit will change the calulation to use the "effective" chip and group ids when calculating the inband scom mmio range. Change-Id: Iaa0bed0b6ee02c02cf9319c2708f9366a97eefeb CQ:SW422379 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58220 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: William G. Hoffa Reviewed-by: Daniel M. Crowell

Properly handle INTRP unmask error handling

2018-02-14T16:28:12+00:00

Change-Id: Ic81b3b2bb73e714b0609fa14b5b308db399b88b6 CQ: SW416916 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53945 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Prachi Gupta Reviewed-by: Elizabeth K. Liner Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell

Re-order INTR/IPC shutdown message handling

2018-02-14T15:00:32+00:00

- The mbox msg_handler already subscribes to the INITSERVICE shutdown message so perform the IPC shutdown logic during that Change-Id: I2402e6ac17212051029de3474e24b8e91dce9544 CQ: SW417278 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53984 Reviewed-by: Richard J. Knight Reviewed-by: Prachi Gupta Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Dean Sanner

Updates to make multinode IPC work

2018-02-13T11:38:43+00:00

-Fixed node/group id calculations -Reduced dbell printk to prevent printk overflow -Fixed architectual hole in how internode IPC works Workitems won't work, instead just always check for IPC on any doorbells to master thread -Changed PIR tracing to print out in hex Change-Id: I25eb7f87fd812a90f98a7724b1ac1100f764fe7b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53187 Tested-by: Jenkins Server Reviewed-by: Prachi Gupta Reviewed-by: William G. Hoffa Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Dean Sanner

Multi-Drawer (IPC) Interrupt/Messaging Support

2018-01-25T22:44:20+00:00

- Use doorbells instead of IPIs (no IPI support using LSI interupts in the XIVE intr architecture) - New message type from kernel to userspace so the kernel can notify the HB userspace Interrupt Resource Provider (INTRP) that an IPC message was sent to the particular HB instance (in P8 this happened automatically as that was part of the IPI architecture). - Re-enable testcase that validates that an IPC message can be successfully sent. Change-Id: Ic846f8dca45217205ed61d8381a573e995cb16f2 RTC: 150861 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52004 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Christian R. Geddes Tested-by: FSP CI Jenkins Reviewed-by: Prachi Gupta Reviewed-by: Daniel M. Crowell

Interrupt Handling Flow Change to Prevent Deadlock

2018-01-16T02:31:09+00:00

- Previously the End of Interrupt (EOI) message was sent after the registered interrupt handler completed handling of the defect. Instead of this, now the INTRP will immediately mask the current interrupt source and issue the HW EOI to allow other interrupt sources to present. - Later when the registered interrupt handler sends INTRP its EOI message the INTRP will unmask the source and issue the necessary HW EOI to fully clear the interrupt Change-Id: I01c99ca9fdd0cedcf3d313127a8d56f5cda66bc7 CQ: SW413511 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51691 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell Tested-by: FSP CI Jenkins Reviewed-by: Christian R. Geddes

Set hostboot_mode bit on P3PC interrupt scom reg during intrrp init

2017-12-08T16:44:24+00:00

The interrupt resource provider is expecting hostboot to set this bit in the P3PC register to notify the interrupt logic that we are running hostboot. Setting this allows the interrupt code to allow thread contexts to be enabled w/o NVT data structures, also complex store operations to thread context are considered invalid and are dropped. This bit gets cleared in the shutdown path when we reset the interrupt logic. Change-Id: I41430c836633796d6841a965ef634f26939c6eb5 CQ: SW410032 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50598 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: Martin Gloff Reviewed-by: Matt Derksen Tested-by: Jenkins OP Build CI Reviewed-by: William G. Hoffa

Secure Boot: Blacklist: Init PSI bridge BAR and FSP BAR properly for security

2017-11-30T16:48:03+00:00

Change-Id: I96639c0e61a101170802ba9a96cd785d0388e985 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50057 Reviewed-by: Stephen M. Cprek Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Michael Baiocchi Reviewed-by: William G. Hoffa Reviewed-by: Marshall J. Wilks Reviewed-by: Daniel M. Crowell