talos-hostboot/src/usr/i2c, branch 07-25-2019

Move definition of TRACE_ERR_FMT and TRACE_ERR_ARGS

2020-02-03T15:22:01+00:00

Originally TRACE_ERR_FMT and TRACE_ERR_ARGS were defined in centaurScomCache.H for the P9 'master' branch. This commit puts them into the more proper errlentry.H file like they are for P10's 'master-p10' branch. Change-Id: Icb7af6ae721a15036804b7d35f49911888eb5eaf Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/90705 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Zachary Clark Reviewed-by: Nicholas E Bofferding Reviewed-by: William G Hoffa

Make RT_TARG id generation code common between IPL time and runtime

2020-01-22T15:45:00+00:00

For axone we are writing the OMI mmio bars into hdat so the hypervisor know how to talk to the devices. IPL code needs to be able to lookup the hbrt-style ids so we can use them to make hdat entries that the hypervisor will be able to associate targets with. This commit also move rt_targeting.H to the correct include directory and updates everywhere that it is included. Change-Id: I31deaa1a9c5a7523622a8b3b12ad459e2b2feed3 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80419 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M Crowell

NVDIMM: Use block write for nvdimm update

2020-01-20T16:23:06+00:00

In an effort to speed up the nvdimm update, full 32-byte blocks can now be sent via I2C SMBUS with no initial byte count byte. Since a block write seems more prone to random system interrupt, this code should be restricted to run on v3.A or beyond which has the timeout increased to mitigate these interrupts. Test results have shown about a 5 minute improvement per NVDIMM. Change-Id: I040a5f2cc5afb76a73129ef9f6ac965cf36775f4 CQ: SW471053 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79678 Reviewed-by: Corey V Swenson Tested-by: Jenkins Server Reviewed-by: TSUNG K YEUNG Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M Crowell

Automatically include config.h

2019-12-06T16:28:47+00:00

Rather than having to remember to include config.h anywhere we reference a CONFIG variable (and usually forgetting), this adds it to the default compiler flags so that it gets included in every source file we build. Change-Id: I53622ab4d46c55d942e98cae6ec03049fd5b3d08 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/87475 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Zachary Clark Reviewed-by: Roland Veloz Reviewed-by: Christian R Geddes Reviewed-by: Nicholas E Bofferding

Fixes to PMIC presence detection

2019-11-08T05:34:48+00:00

While performing presence detection on the PMIC targets we need to first read the parent OCMB's SPD to see what device address the PMIC is on. There was a bug where we were attempting to read the parent OCMB's spd without first checking if the OCMB is present itself. This commit adds a check to ensure we dont attempt i2c reads on devices that are not present. Also this commit adds a check to make sure we do not attempt presence detection on GEMINI ocmbs Change-Id: I999189b3b97210bb37b7ba1fdb2d86658d770e36 CQ: SW480414 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/86564 Reviewed-by: Ilya Smirnov Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M Crowell

Avoid commiting errors inside fapi2_i2c device driver

2019-11-08T05:17:54+00:00

There are instances where we expect NACK errors returned from i2c requests, for example when waiting for the ocmbs to declare themselves "ready". In these cases we do not want to flood the error log with expected I2C nack errors. To avoid this, instead of committing retriable errors inside of the fapi2_i2c device driver when the MAX RETRY ATTEMPTS is reached we will instead just add traces to the err that gets returned to the caller that explain previous retryable errs occured. In the case where we hit retryable errors and eventually hit and non-retryable error the retryable error is committed in the driver and the non-retryable error is returned to the caller. Also this commit adds some timings to the error log so we can tell how long our attempts took. Change-Id: I9a5ee0bfe088444aa7fecd974f61514c40b320a6 CQ: SW480155 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/86419 Tested-by: Jenkins Server Reviewed-by: Matt Derksen Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Daniel M Crowell

Allow dynmic i2c device addresses and set up PMIC targets to do this

2019-11-01T20:41:41+00:00

Depending on which vendor made a given OCMB the i2c device address of the PMIC targets on the OCMB will be different. To account for this we have added a new DYNAMIC_DEVICE_ADDRESS attribute. This attribute is filled out on the PMIC target by looking at the SPD on parent OCMB chip. This means that we must do presence detection on the OCMB prior to the the PMIC targets. While doing i2c operations if a given target has the DYNAMIC_DEVICE_ADDRESS we will use that over the devAddr in the any complex i2c attribute for that target. Change-Id: I22a185a65c064a1514751dd5828547c57af98df1 RTC: 209714 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/85394 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M Crowell Reviewed-by: Roland Veloz Reviewed-by: William G Hoffa

Fix calling eepromddtest.H

2019-08-16T15:33:33+00:00

Makefile change overwrote TESTS and lost adding of eepromddtest.H Change-Id: I01adcc3958ce181909589b159a86a54bceb65257 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82293 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Christian R Geddes

OR mux select with the "enable" bit 0b1000 when making selection

2019-08-01T21:50:52+00:00

During simics bringup we figured out that the mux selects needed to be between 8-15. We learned during bringup this is because the real 0-7 select needs to be OR'ed with the enable bit for the model of mux. This commit does the ORing correctly and subtracts 8 from all of the muxSelects used in the simics xml so we match what the MRW is doing. Change-Id: I45faab455afdfc63ac05fc2637890f9d0137a444 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81397 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Reviewed-by: Matt Derksen Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Roland Veloz Reviewed-by: Daniel M Crowell

Always update EECACHE header when we find a new eeprom entry

2019-08-01T21:50:12+00:00

The plan of this caching algorithm is to make a cache entry for every OCMB/DIMM, Proc, and Node eeprom that we detect in the XML. We will only copy the contents of the EEPROM if the target is found to be present, but we still must make header entries in for targets that are not present. Change-Id: I46328b84f7095eec9df7abb2f40b0d11ed0c4324 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81192 Tested-by: Jenkins Server Reviewed-by: Matt Derksen Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Glenn Miles Reviewed-by: Daniel M Crowell