talos-hostboot/src/include/usr, branch 05-21-2018

FFDC enhancements for core activate fails

2018-05-19T21:56:42+00:00

Adding some more traces to the error log we grab for core activation failures. Change-Id: I30c6985060fcffcb3382b775a52e59c08d2b51b7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57907 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Matt Derksen Reviewed-by: Daniel M. Crowell

Get SN from BMC and update into PVPD EEPROM

2018-05-19T21:09:16+00:00

Resolves #135 Change-Id: I46b5c2208ed28822c6001a955f4056d976e79339 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58010 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell

Add option to masterProcChipTargetHandle() to return functional chip

2018-05-18T14:05:18+00:00

This commit adds an option to the two masterProcChipTargetHandle() functions to only look for and return a functional master proc chip as necessary with the issue in Defect SW424528. The default behavior of these functions - where the functionality is not checked - remains the same. Once use of these functions has also been updated to use this new option. Change-Id: I37049d2cb9299a9404b57d85031a364bdb257c82 CQ:SW424528 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58920 Reviewed-by: Nicholas E. Bofferding Reviewed-by: Marshall J. Wilks Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Sachin Gupta Reviewed-by: Daniel M. Crowell

Verify frequency attributes across nodes to match with that of master node

2018-05-16T16:51:54+00:00

-Existing code ensures consistency of frequency data across all modules in istep6.12. -In a multi-drawer config this data needs to be consistent across all drawers. -Master drawer sends the frequency data to all the other via IPC mechanism. -This data is compared and error is returned if there is a mismatch. Change-Id: Ia1daf1f0eeb90fbafb68417b979488b040efe535 RTC:158036 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57542 Reviewed-by: Prachi Gupta Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Roland Veloz Reviewed-by: Daniel M. Crowell

Improve resource recovery path to handle memory plugging rules

2018-05-15T22:08:42+00:00

Resource recovery is a RAS feature wherein we do not apply certain gard records if those records would result in a boot fail due to a lack of hardware. Change the logic from applying speculative deconfiguration one by one to applying all predictive gard records and then removing those records if minimal hardware is not available. Also add BLOCK_SPEC_DECONFIG attribute to flag when speculative deconfiguration is not allowed. This flag is set if minimum hardware is not available and is cleared after a hardware change. Change-Id: Ia065de3a44ab29fbf33ad4ce98bc42ea5144463f RTC: 191414 CQ: SW424137 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58041 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Christian R. Geddes Reviewed-by: Daniel M. Crowell

Force hb dump on VFS crashes

2018-05-11T20:21:22+00:00

Added flag to force a HB dump for most VFS crashes. Also added a few constants in the ErrlEntry constructor to make the bool args more obvious. Change-Id: I4f90ee694cece10f567df787f851dca78a895ad7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57272 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Martin Gloff Reviewed-by: Christian R. Geddes Reviewed-by: Daniel M. Crowell

Secure Boot: Inform FSP of key transition progress

2018-05-11T02:37:38+00:00

The existing key transition flow updates all SBE SEEPROMs within the system in the same boot, thereby quiescing all SBEs. This compromises the ability of FSP to detect a key transition TI at the end of the update process because the SBE is not alive to service FSP's incoming SBE FIFO request to read the memory holding the attention information. This change adds new support to log the key transition progress in a node target attribute introduced in an earlier commit and send that status to FSP via a new mailbox message. Change-Id: I828184ae8be89ac87137d7510a3c375cef2e05d7 CQ: SW418697 CMVC-Prereq: 1053806 CMVC-Prereq: 1053552 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56677 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Michael Baiocchi Reviewed-by: Marshall J. Wilks Reviewed-by: Daniel M. Crowell

New API to Retrieve Random Number from the TPM

2018-05-11T01:49:40+00:00

A new programming interface allows us to obtain random numbers from the TPM more easily (i.e. in a more high-level way). Change-Id: Ibd3d3b320411bea146d6eab4d1a59ca760bc726c RTC:191000 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57802 Reviewed-by: ILYA SMIRNOV Tested-by: Jenkins Server Reviewed-by: Michael Baiocchi Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Nicholas E. Bofferding Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell

Get Final HDAT Size from PAYLOAD's SPIRA section

2018-05-08T18:37:04+00:00

This commit retrieves the amount of space the PAYLOAD has reserved for the HDAT content in its SPIRA section. It then uses this size when copying the HDAT from the temporary location (where the FSP put it with DMAs-via-TCEs) to its final location. Change-Id: I430a78a1655db85f448b3f5c30e6a83f5be4b1f6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58261 Reviewed-by: ILYA SMIRNOV Reviewed-by: Nicholas E. Bofferding Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell

Secure Boot: Implement Centaur SCOM cache

2018-05-08T13:44:28+00:00

This change implements a Centaur SCOM cache for sensitive SCOM registers. The cache is initialized and enabled before the first Centaur SCOM, and disabled just prior to locking down the Centaur configuration. Once the Centaur has been locked down, the real register values are compared to the cache entries, and the Centaur is deconfigured (not garded) on any mismatch in assumptions. RTC: 187288 Change-Id: I7b13bfd7eb6b427aba115d6944958bf55e171008 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57532 Reviewed-by: ILYA SMIRNOV Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Michael Baiocchi Reviewed-by: Daniel M. Crowell