talos-hostboot/src/include/usr/util, branch master

Update utilDeallocateTces and other TCE Cleanup

2018-02-13T22:09:41+00:00

This commit removes the size parameter from utilDeallocateTces() as we should be able to use the token parameter to get back the saved size of the region. This commit also cleans up some other minor TCE issues and even fixes one I2C trace. Change-Id: I9ed5695d5ea13d89a22ace9593b5d9dc31a16736 RTC:168745 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53908 Reviewed-by: Nicholas E. Bofferding Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Reviewed-by: Marshall J. Wilks Reviewed-by: ILYA SMIRNOV Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell

Verify ComponentID and Extend PAYLOAD

2018-02-01T22:59:52+00:00

While verifying the PAYLOAD in memory before moving it to its final location, this commit parses the PAYLOAD's header and verifies that it has the correct componentId. It also extends the PAYLOAD information to the TPM. Change-Id: Ie333d1ba5919b36919b207f25ad60806359ed710 RTC:168745 Backport: release-fips910 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52837 Reviewed-by: Nicholas E. Bofferding Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Stephen M. Cprek Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell

On MPIPLs open up TCE windows for FSP to extract dump information

2018-02-01T22:58:10+00:00

When the system is rebooting in a MPIPL, in istep 14.8 host_mpipl_service, if TCEs are enabled, a Read-Only TCE window will be opened for the FSP to read information about the dump. Change-Id: I1a32c9d4fe0027e795c14c50dfbd8782609b17e9 Backport: release-fips910 CQ:SW415585 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53204 Reviewed-by: Nicholas E. Bofferding Tested-by: Jenkins Server Reviewed-by: Stephen M. Cprek Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell

Collect better FFDC on ROM verification errors

2018-01-31T16:09:11+00:00

Collect both the UTIL and RUNTIME component traces on a ROM verify failure Added a new Errlog User Details sections "Verify Info" containing the component name, ID(s), measured, and expected hashes Change-Id: I0d0408128e05807bb906be5ee365d56d1416693f CQ:SW413889 Backport:release-fips910 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52593 Reviewed-by: Michael Baiocchi Reviewed-by: Nicholas E. Bofferding Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Marshall J. Wilks Reviewed-by: Daniel M. Crowell

Concurrent code update of HBRT - Update Structure

2018-01-08T18:23:52+00:00

Update Hostboot targeting data in the new targeting structure from the current targeting data. It will have the logic to save and restore values as appropriate. Change-Id: I7ae4a0c2e58548f6f1a6229f40b9fda833670e86 RTC: 180908 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48504 Reviewed-by: Roland Veloz Reviewed-by: Matt Derksen Reviewed-by: Brian E. Bakke Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell

Handles FSP reset-reload in HBRT messages

2017-12-21T05:12:25+00:00

For every instance where a firmware_request is made, it is possible to get an error if the FSP is doing a reset/reload. Now, if an error returned from the firmware_request call indicates that the FSP is doing a reset/reload, the firmware_request call will be made again. Also refactored the code. Consolidated the calls to firmware_request to another file to facilitate the adding/updating of messages. Change-Id: I5be440927ab255c55b40a0a0ed26f786d31a9317 RTC:182606 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50505 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Reviewed-by: Daniel M. Crowell

Fix Initializing HW To Point At An Invalid TCE Table in Istep 10.6

2017-12-20T22:00:02+00:00

This fixes a bug where the HW was not initialized properly to point at an invalid TCE Table in istep 10.6. This is required such that the FSP cannot DMA into memory without Hostboot control. Change-Id: I41ad102a4c05bfede5062f6082cbfa9041c0f1cf RTC:168745 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50652 Tested-by: Jenkins Server Reviewed-by: Nicholas E. Bofferding Reviewed-by: Stephen M. Cprek Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell

Convert asserts to error logs where it makes sense

2017-12-20T18:54:35+00:00

Change-Id: Idd15e39cc6be44c0865f13503bfa4482d77fcf0d RTC:181899 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51042 Tested-by: Jenkins Server Reviewed-by: Michael Baiocchi Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Martin Gloff Reviewed-by: Nicholas E. Bofferding Reviewed-by: Daniel M. Crowell

Add hbHypCommArea struct to end of Hostboot Data reserved mem section

2017-12-15T21:06:35+00:00

The Hypervisor needs a way to send down an address to the host so that the host can account for the HRMOR moving and still be able to boot on an MPIPL. To do this we are adding another subsection to the existing reserved memory section which already was holding VPD and attribute info. This subsection will serve as the HB-HYP communication region. For now PHYP is the only hypervisor using this space and they are only using it to store the HRMOR if they decide to move it. In order for the hypervisor to easily find where to write the HRMOR we added an address pointer to HDAT that hostboot will fill in to tell PHYP where to write the HRMOR. This is all setting up for us to be able to read the HRMOR after an MPIPL so that we can load the hypervisor in at the correct address. Change-Id: I5d3687a207296bd87d2a7120dd17505e0022b748 RTC: 180959 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48651 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Reviewed-by: Matt Derksen Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Martin Gloff Reviewed-by: William G. Hoffa

Modify how POWERVM is processed in the MCL manager

2017-12-12T22:50:35+00:00

POWERVM is verified and loaded to its final location before the MCL processing occurs. Therefore we only need to get the lid sizes and create HDAT entries Additionally it was found that sorting the CompInfoMap resulted to direct key lookup to not work for the POWERVM component, so removed it. Change-Id: I5008a1eaa01e0910743fdb11fa73b73a26eccd63 RTC: 181900 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50644 Reviewed-by: Nicholas E. Bofferding Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Marshall J. Wilks Reviewed-by: Michael Baiocchi Reviewed-by: Daniel M. Crowell