talos-hostboot/src/include/usr/sbe, branch master

Secure Boot: Inform FSP of key transition progress

2018-05-11T02:37:38+00:00

The existing key transition flow updates all SBE SEEPROMs within the system in the same boot, thereby quiescing all SBEs. This compromises the ability of FSP to detect a key transition TI at the end of the update process because the SBE is not alive to service FSP's incoming SBE FIFO request to read the memory holding the attention information. This change adds new support to log the key transition progress in a node target attribute introduced in an earlier commit and send that status to FSP via a new mailbox message. Change-Id: I828184ae8be89ac87137d7510a3c375cef2e05d7 CQ: SW418697 CMVC-Prereq: 1053806 CMVC-Prereq: 1053552 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56677 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Michael Baiocchi Reviewed-by: Marshall J. Wilks Reviewed-by: Daniel M. Crowell

Created individual update flags for both SEEPROM 0 and SEEPROM 1

2018-03-12T18:22:13+00:00

I created individual update flags for both SEEPROM 0 and SEEPROM 1 to better target which seeprom to update. Now SEEPROM 0 or SEEPROM 1 or both can be singled out for update(s). Change-Id: I91f1b66f6a1f2e42d37173fb9e21f87e440d3a21 RTC: 189218 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55173 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Martin Gloff CI-Ready: Daniel M. Crowell Reviewed-by: Christian R. Geddes Reviewed-by: William G. Hoffa

Force an SBE update upon boot failure as well as break out common data

2018-02-28T18:46:06+00:00

This commit takes care of two stories since they are related to each other. First, moved all common data (structs, enums, constant literals) from file sbe_update.H into sbe_common.H. This will allow content to be shared between FSP and HB with out having to have simultaneous updates. Secondly, an update will be forced if bit 3 of the SB keyword flags dictates it, regardless of whether an update is recommended or not by other logic. Change-Id: I3bd3c5cdd648309637bdf657db8f0935670c7d12 RTC:181140 RTC:181141 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54408 Reviewed-by: Martin Gloff Reviewed-by: Brian E. Bakke Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell

Story 179465 - Smarter HBBL id handling ...

2017-11-19T18:15:50+00:00

to avoid constant SBE updates Change-Id: Id02c7eb95a8e83274968477514130512ee553968 RTC: 179465 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49748 Reviewed-by: Martin Gloff Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Christian R. Geddes Reviewed-by: Daniel M. Crowell

Use readSeeprom PSU chipop to get SBE seeprom image version

2017-11-18T02:05:53+00:00

During an SBE update we were getting I2C collisions when trying to access pnor on the "running" or "active" side of the seeprom. This commit adds support for a PSU chipOp called "readSeeprom" which allows the host to make a request to the SBE to copy a specified chunk of pnor out to a buffer in memory which the host can access. This commit also uses this chipOp in place of the I2C read during the SBE update of the active seeprom side. Change-Id: I4b639ebe6090dcc0bdbb42f13fcb12c23260a8b4 RTC: 180959 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48408 Tested-by: Jenkins Server Reviewed-by: Matt Derksen Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell

SBE update plan for OpenPOWER

2017-08-09T17:34:40+00:00

We need to have a new way to handle the SBE update flow for OpenPOWER. Update the SBE code one side at a time to avoid a scenario where a bad code load bricks the system. Start by loading side 0 (primary), then re-IPL, and finally load side 1 (backup). A new config flag is used, SBE_UPDATE_CONSECUTIVE. Change-Id: Icf18ebec173c2f42fe200fb9cd547b9ebc580acc RTC: 176755 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43893 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Christian R. Geddes Reviewed-by: Corey V. Swenson Reviewed-by: Michael Baiocchi Reviewed-by: Daniel M. Crowell

Remove SBEC pnor partition from p9 code

2017-07-24T20:13:26+00:00

Change-Id: I13e79a6542353e42ac809cc60295947dfb1acb96 RTC: 163810 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43048 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Martin Gloff Reviewed-by: Nicholas E. Bofferding Reviewed-by: Daniel M. Crowell

Block SBE updates during mpipl

2017-07-18T22:17:09+00:00

Change-Id: Ie59495404ec27d6be865063fc930e895340d9be2 RTC: 169683 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42853 Reviewed-by: Matt Derksen Tested-by: Jenkins Server Reviewed-by: Martin Gloff Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell

Log build level for SBE and HCODE customization

2017-07-17T15:07:38+00:00

Extract build information from the XIP header for the SBE and HCODE images. Trace the information. Also use it as FFDC for related error logs. Save the SBE build information in the SB keyword of MVPD. Change-Id: I600a71ae6cbf342643261da14f6b3b2e6bf3cbf1 RTC: 168827 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42951 Reviewed-by: Matt Derksen Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Christian R. Geddes Reviewed-by: Daniel M. Crowell

xip_customize: GPTR/overlays stage 1 support

2017-07-14T12:28:11+00:00

Updated to poll Nimbus DD level and whether there's support for overlays in the XIP interface. Further, updated to add three extra args in xip_customize API, two of which are to support a third ring work buffer for the overlays handling. This has necessitated making changes to hcode_image_build (HIB) API as well. Note that the calling codes of xip_customize and HIB need to be updated to supply the additional args in their APIs. Note that this code stage 1 will work for Nimbus DD2 with Gptr rings in Mvpd, and no Gptr rings in the HW image. It will, however, not work if there's content in .overlays or if there's Gptr rings already in the .rings section. Thus, the stage 1 code here will work with a DD2 image (i.e., that does NOT have Gptr rings in .rings in HW image) as long as noone has put any real Gptr initfiles in for processing (which would result in ring content in .overlays). We must ensure that the stage 2 code of xip_customize gets merged on the HB side to enable processing of .overlays content before we actually add any Gptr initfiles for the .overlays section into EKB. Change-Id: I3d6ab8a9add239c92819613dcae21ef5faf0a1c5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40591 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Sumit Kumar Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40898 Reviewed-by: Dean Sanner Tested-by: Dean Sanner