talos-hostboot/src/include/usr/devicefw, branch 07-25-2019

NVDIMM: Use block write for nvdimm update

2020-01-20T16:23:06+00:00

In an effort to speed up the nvdimm update, full 32-byte blocks can now be sent via I2C SMBUS with no initial byte count byte. Since a block write seems more prone to random system interrupt, this code should be restricted to run on v3.A or beyond which has the timeout increased to mitigate these interrupts. Test results have shown about a 5 minute improvement per NVDIMM. Change-Id: I040a5f2cc5afb76a73129ef9f6ac965cf36775f4 CQ: SW471053 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79678 Reviewed-by: Corey V Swenson Tested-by: Jenkins Server Reviewed-by: TSUNG K YEUNG Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M Crowell

NVDIMM: Fix issue where a deviceRead of a register is returning bad data

2019-08-09T16:18:40+00:00

The reason the deviceRead is returning bad data, from an NVDIMM register, is because the register data is segmented across several pages. One must first set the page correctly before attempting to do a read of a register. This fix will set the page up correctly before doing a read/write to an NVDIMM register. Change-Id: Ic63c8671c0083f1ca243f255a29d1ef4606b7ce5 CQ: SW465917 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81542 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: Matthew Raybuck Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Matt Derksen Reviewed-by: Daniel M Crowell

Use i2c word write for NVDIMM update

2019-06-12T14:45:34+00:00

Trying to reduce the update time and this reduced teh time to about 12.3 minutes. Change-Id: I97cd29a8bcda58902089480f2cc0849381e7d2cf CQ:SW466226 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78422 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell

HB Improvements: Fix compiler warnings on modern compilers

2019-04-05T21:52:10+00:00

Resolve warnings when compiling with gcc 4.8. Compiled with GCC 7.3, no more compile errors/warnings; build ends with caught exception from linker. This commit compiles with GCC 8.2, no more error/warnings; except for a linking warning. Change-Id: Ib5d7c2b5bd350edc76ee2c7de96896154cd44420 RTC: 202716 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72271 Reviewed-by: Nicholas E. Bofferding Reviewed-by: Ilya Smirnov Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell

UCD Flash Update: Support I2C SMBUS operations for UCD flash update

2019-03-08T16:12:18+00:00

- Adds I2C SMBUS operations for UCD flash update - Creates UCD component ID + trace name - Creates stub for UCD flash update entry point Change-Id: Id75cdd137b5a4924998c04bdbdce9218610a4906 RTC: 201992 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72229 Reviewed-by: Ilya Smirnov Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Matthew Raybuck Reviewed-by: Daniel M. Crowell

Add new path in EEPROM device op to allow reading from new EECACHE

2019-02-16T15:10:13+00:00

Recently a new EECACHE section was introduced to Hostboot. This section gets populated with a copy of every PRIMARY_VPD eeprom (someday could contain other eeprom roles also) during host_discover_targets. This commit add support to allow users to select where they want to perform their EEPROM device operation. If they pass CACHE to the deviceOp macro then a read will come from the pnor cache, writes will write to pnor cache and then also write to the eeprom HW. If HARDWARE is passed in then reads and writes will be directly done on the eeprom hardware. If AUTOSELECT is passed the code will check our cache to see if we have a copy of the eeprom in question, if we have a copy we will go the CACHE path, if no copy exists we will go the HARDWARE path. Along with this change some reorganization was done w/ the eeprom related files. RTC: 196805 Change-Id: If2c4e5d3e338a1a10780740c1a019eb4af003b73 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70822 Reviewed-by: Matt Derksen Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Roland Veloz Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell

Add EEPROM caching device op

2019-02-13T20:41:48+00:00

This commit introduces a new EEPROM_CACHE deviceOp and registers the OCMB_CHIP, PROC, and DIMM targets to it. This is part of the larger effort to transition for a "VPD" cache to an "EEPROM" cache in pnor. The deviceOp is currently called in hwasPlat's platPresenceDetect if the target in question has a ATTR_EEPROM_VPD_PRIMARY_INFO associated with it. The layout for the new EECACHE section in pnor is defined in eepromCache_const.H. Essentially it is a header that contains an array of record headers that tell where in the EECACHE pnor section a given cached EEPROM can be found. All EEPROM targets will be allocated space in the EECACHE section but only present targets will have their cache filled in. RTC: 196805 Change-Id: I49c341c9784be04ddf0259bd444f06c9baf8c6f1 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70520 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Matt Derksen Reviewed-by: Roland Veloz Reviewed-by: Daniel M. Crowell

Hack to force OCMB presence detection

2018-12-14T00:18:52+00:00

Temporary code that assumes the OCMB is present if the target is in the model. Also adds a check to throw an error instead of crashing if VPD_REC_NUM isn't set. Change-Id: Iba87d13093f0044bdf28a10621561e02d10faaf6 RTC: 196805 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68488 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Christian R. Geddes Reviewed-by: Nicholas E. Bofferding

Driver changes to support i2c mux

2018-12-07T01:18:15+00:00

- Updated data structures gpioAddr_t, eeprom_addr_t, misc_args_t, nvdimm_addr_t and tpm_info_t with I2C MUX data members. Also added constructors to these structures to default there data members with the correct default info. - Updated macros DEVICE_I2C_PARMS, DEVICE_I2C_ADDRESS and DEVICE_I2C_ADDRESS_OFFSET to take the I2C MUX bus selector parameter and the I2C MUX entity path. - Added method i2cAccessMux to file i2c.H/.C that will setup the call for the I2C MUX. Method i2cCommonOP calls i2cAccessMux which then calls i2cCommonOp with appropriate parameters for the I2C MUX: i2cCommonOP -> i2cAccessMux -> i2cCommonOP. - Updated i2ctest.H with new I2C MUX params to get it to pass. RTC:191352 Change-Id: I6a70860eb2286bbd23d6157d72351b8adfa21aac Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66651 Reviewed-by: Ilya Smirnov Tested-by: Jenkins Server Reviewed-by: Nicholas E. Bofferding Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell

Route scom operations on OCMB chips to exp_i2c_scom interface

2018-11-15T18:18:39+00:00

Before we get OMI targets trained we must use i2c to access scom registers on the OCMB chip. This commit does all of the plumbing so when HWP calls getScom() on a OCMB target, the hostboot platform recognizes this as a special scom and routes it to a new i2scom DD. This device driver will truncate the scom address to 32 bits and run the exp_i2c_putscom/exp_i2c_getscom interfaces to perform the operation. Eventually we need to also support MMIO scoms to the OCMB chip, the MMIO scoms will be used after the OMI training is complete. Change-Id: I0018cc8d25f74d1253b72c3112d3e344a4248416 RTC: 196806 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67976 Reviewed-by: Matt Derksen Tested-by: Jenkins Server Reviewed-by: Ilya Smirnov Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell