talos-hostboot/src/include/arch, branch master

Force 25G Nvlink speed on P9N DD2.1

2018-03-09T02:25:27+00:00

Normally the OBUS PLL frequency is controlled via the MRW, however P9NDD2.1 has a bug that forces the OBus freq to 25G. Desire is to allow the MRW to set to a higher freq, but MRW doesn't have entries for per chip EC, so this commit just handles down leveling P9N DD2.1 (as a chip restriction) Change-Id: I542f7810a69facb919cc3889ae3ed5ca0a233445 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55195 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: William G. Hoffa CI-Ready: Dean Sanner CI-Ready: Corey V. Swenson Tested-by: FSP CI Jenkins Reviewed-by: ERICH J. HAUPTLI Reviewed-by: Daniel M. Crowell

Enable ATTN prior to OPAL handoff

2017-11-30T14:33:28+00:00

Change-Id: Iadfded90c09b149948348ee462ab34f9c2431982 RTC: 182134 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49865 Reviewed-by: Matt Derksen Tested-by: Jenkins Server Reviewed-by: Christian R. Geddes Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell

Story 180760 - Use self restore API to disable ATTN in HID ...

2017-11-07T15:47:40+00:00

during istep 15/16 of HCODE build/execution Change-Id: I63f54cdc35b3ff7e68120a07c142b6a557257854 RTC: 180760 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49070 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Christian R. Geddes Reviewed-by: Matt Derksen Reviewed-by: William G. Hoffa

Log traces to error logs in HBRT

2017-10-20T02:17:55+00:00

This enables buffer tracing at hostboot runtime. Will add these traces to runtime errors for better debug Change-Id: I795bb7deafdd02adea4588ebf8dfb11cbce116a0 RTC:172770 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48084 Tested-by: Jenkins Server Reviewed-by: Christian R. Geddes Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Martin Gloff Reviewed-by: Daniel M. Crowell

Setup INTP bars correctly when memory is swapped on master proc

2017-06-02T16:12:11+00:00

In the event that no memory is detected behind proc0. We will attempt to use the memory behind a slave proc instead. When this occurs we must adjust the interrupt bars to account for this swap Change-Id: Ib37a190b7a7a2c655440ffd2bad56c351b4d4fa2 RTC: 173527 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40820 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Martin Gloff Reviewed-by: Daniel M. Crowell Reviewed-by: William G. Hoffa

Map BAR attributes based on data from Bootloader

2017-06-02T13:23:59+00:00

If the master processor has no memory behind it the entire memory map must be modified. Each processor has its own statically defined map that covers both memory and MMIOs. If the master has no memory, its memory map is swapped with another processor. Each processor gets a new effective fabric id that is then used to compute all of the BAR values for those processors. The SBE boots with a certain memory map programmed into the master processor. That value is then passed up through the bootloader into Hostboot. This value is compared to the BAR values that Hostboot assumes it is using. Based on that comparison, various attributes are computed to match the effective fabric positions. Change-Id: I2b0d1959c303df8c9c28c8f0a5b5be1e77aa154f RTC: 173528 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40359 Tested-by: Daniel M. Crowell Reviewed-by: Martin Gloff Reviewed-by: Christian R. Geddes Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: William G. Hoffa

Cleanup for SMT4/SMT8 read fuse bits and activate threads

2017-05-15T16:44:15+00:00

Change-Id: I9de1c4b08aceee76eed962413345c5e6d1444f23 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39947 Tested-by: Jenkins Server Reviewed-by: Martin Gloff Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell

Fix PVR check for Nimbus DD1

2017-05-12T03:39:31+00:00

Added check for bit 18 to distinguish between Nimbus DD1.0 and Cumulus DD1.0 Consolidated Nimbus DD1 checking to a common function Added printk output that shows which CPU we're running on Modified some existing printk output to use fewer characters Change-Id: I1c42df0051fc2d9cc5fa54d95f68c3bd26b86462 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39876 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Tested-by: Jenkins OP Build CI Reviewed-by: Corey V. Swenson Reviewed-by: Martin Gloff Reviewed-by: Christian R. Geddes Reviewed-by: Daniel M. Crowell

Handle SMT4/SMT8 fuse bits

2017-04-28T18:14:12+00:00

Change-Id: I8fc108877714ff76103510b7801af72a94e5aae3 RTC:160720 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39778 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Martin Gloff Reviewed-by: Daniel M. Crowell

More istep debug output

2017-04-17T13:19:12+00:00

Write current istep out to mbox scratch reg 5 Print istep out to simics console Change-Id: I14d8a9afba12b627a0b1880e0818b5b16f317d7c RTC: 171748 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39292 Tested-by: Jenkins Server Reviewed-by: Christian R. Geddes Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Thi N. Tran Reviewed-by: Dean Sanner Reviewed-by: William G. Hoffa