talos-hostboot/src/include/arch, branch 07-25-2019

Force a Hostboot dump on any TI in Simics

2020-01-07T19:14:40+00:00

Execute a magic instruction in the TI path to force a hostboot dump to be collected on any TI while running in Simics. Change-Id: I8aeffb2b646bbe8480568e8af33a658400fa01a5 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/88831 Reviewed-by: Nicholas E Bofferding Reviewed-by: Matt Derksen Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: William G Hoffa

Handle processor swap between slots to 1-socket system

2019-08-05T20:33:09+00:00

If a processor was booted in the second slot, it will be programmed to use the memory for that slot. When it is installed in the first slot it will then get reprogrammed to use the data for slot0. However, if the new system only contains data for that 1 slot, we won't be able to find a match to do the initial part of the boot. This change will force some values into good enough shape to get the boot far enough to do the SBE update to reprogram the memory map. Change-Id: I9b88d4181272104a8c680e9b5e84c4d204fdea05 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80680 Reviewed-by: Matt Derksen Reviewed-by: Christian R Geddes Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M Crowell

Assembly for DARN instruction inconsistent

2019-06-22T00:13:49+00:00

Sometimes generating incorrect L value for the darn instruction. Removed the L variable and hard-coded into the instruction. Change-Id: I5b478d2c220858942320f6fea3cb09d0ba6aee42 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79278 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Roland Veloz Reviewed-by: Daniel M. Crowell

NVDIMM encryption HW function support

2019-06-03T15:26:25+00:00

Update random number generation, IPL and runtime. Write encryption regs to enable nvdimm encryption, crypto-erase, disable encryption. Read config-status reg to verify encryption state. Change-Id: I25625b53f90eeb542767fa729ebb47f8f8455a4b RTC:201474 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77321 Reviewed-by: Nicholas E. Bofferding Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Matthew Raybuck Reviewed-by: Daniel M. Crowell

Developer Improvement: Get code coverage tool working with Hostboot

2019-05-13T14:10:45+00:00

This commit fixes GCOV code coverage for P9 with GCC 4.9.2 Change-Id: Ie1e7c35f67414531dbd6e7a771ac1529a9ebd59d RTC: 208351 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76812 Tested-by: Jenkins Server Reviewed-by: Nicholas E. Bofferding Reviewed-by: Ilya Smirnov Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell

General Improvement: Get HB standalone + op-build working with GCC8

2019-05-02T15:52:37+00:00

Fix issue where when compiling with GCC 8, illegal instruction of value 0x0 is placed instead of the expected "blr" instrusction. Change-Id: I2ff28d5549689d541ea24d102230cbfc22cbbbff RTC: 163075 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76650 Tested-by: Jenkins Server Reviewed-by: Nicholas E. Bofferding Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Zachary Clark Reviewed-by: Daniel M. Crowell

Validate OMI INBAND BAR offset attributes against calculated values

2019-04-18T15:38:28+00:00

While setting up the virtual memory mapped IO to the OCMB chips we make some assumptions that the OCMB MMIO spaces will be contiguous. The p9a_omi_setup_bars HWP uses OMI_INBAND_BAR_BASE_ADDR_OFFSET to set the scom registers that determine the physical offset mapped to the IO. When setting up the Virtual addresses hostboot uses to represent the physical mmio address, we must validate that the attribute matches with what we calculated. While doing this we found that the virtual address attribute was being calculated incorrectly. It was not localizing the OCMB position relative to the MC which is required when calculating the offset into the MC bar. Change-Id: I0ebbcd38e19a238e2cc16791bb0595536788bb7f RTC: 201493 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75631 Reviewed-by: Matthew Raybuck Reviewed-by: Michael Baiocchi Reviewed-by: Roland Veloz Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell

Add simics exit_cache_contained mode call

2019-04-08T17:46:42+00:00

In istep14, need to call magic instruction 8021 in order to exit cache contained mode when running simics. Change-Id: I277f07420111c0383a7d9b61bf4d1750e39126f2 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75473 Reviewed-by: Christian R. Geddes Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Corey V. Swenson Reviewed-by: William G. Hoffa

Add msgsync to doorbell wakeup logic to avoid weak consistency bug

2019-01-21T14:54:51+00:00

POWER9 added a new sync mode called 'msgsync' that is required to avoid weak consistency issues when you are using doorbell (msgsnd) functions. See POWER ISA Section 5.9.2 for details, excerpt here: The ordering done by sync (and ptesync) provides the appearance of "causality" across a sequence of msgsnd instructions, as in the following example. "msgsnd->T1" means "msgsnd instruction target- ting thread T1". "" means "occurrence of Directed Hypervisor Doorbell interrupt caused by msgsnd executed on T0". On T0, register r1 is assumed to contain the value 1. T0 T1 T2 std r1,X sync msgsnd->T2 msgsync msgsnd->T1 ld r1,X In this example, T2's load from X must return 1. The change here adds the msgsync call to the code that executes any time we handle a doorbell interrupt. In addition there is a POWER9 DD2 errata that indicates we also require a lwsync to ensure consistency. Change-Id: Ib0f3571926d71efcbffa205093278e2a1d58df85 CQ: SW454611 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70648 Reviewed-by: Nicholas E. Bofferding Reviewed-by: Dean Sanner Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: William G. Hoffa

Elevate log levels for simics during PSU ops

2018-10-18T17:42:10+00:00

This commit introduces some new magic instructions one which will temporarily elevate the log levels for given components and another which will start and stop collection of these simics logs. This was added so we can temporarily increase log levels during PSU operations in hopes of catching a timeout we have been seeing in simics and getting more info for the simics teams. Change-Id: I990a4b5413f7ff14796dee36e39199f785aef458 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67359 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Matt Derksen Reviewed-by: Ilya Smirnov Reviewed-by: Hieu C. Nguyen Reviewed-by: William G. Hoffa