talos-hostboot/src/import/chips/common, branch 07-25-2019

Add Gemini to chipids list

2019-04-23T14:43:37+00:00

Add the newly defined chipid for Gemini Also added some SPD values for the DMB id Change-Id: I19ff1cbb14d0f2ae1b1dfaf29e42658effd2248a Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76121 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Reviewed-by: Matthew Raybuck Tested-by: Hostboot CI Reviewed-by: Louis Stermole Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76128 Reviewed-by: Jenkins Server Reviewed-by: Christian R. Geddes Tested-by: Christian R. Geddes

Add header file to keep track of Chip IDs

2018-11-27T19:31:14+00:00

New header file includes 32-bit and 16-bit versions of the standard chip id (cfam id, idec). Also added the OpenCAPI device id for Explorer. Change-Id: I3ae122ed447b86c269a4b9cbc5ea7b8aefa4c702 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66931 Tested-by: Jenkins Server Reviewed-by: Joseph J. McGill Reviewed-by: Benjamin Gass Reviewed-by: Brent Wieman Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69099 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell

Revert "P10 prep: Infrastructure (IS) ring Id metadata and API changes"

2018-10-15T13:48:17+00:00

This reverts commit 52b76be222254e59959db984606c09dae854270b. Accidental merge before ekb was complete. Change-Id: I59412ecad661596322aaba5cb5cf83190727d64f Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67455 Reviewed-by: Daniel M. Crowell Tested-by: Daniel M. Crowell

P10 prep: Infrastructure (IS) ring Id metadata and API changes

2018-10-14T18:05:32+00:00

Gerrit intent: - Applicable for P9 merge (co-req NOT required) - Co-req not req'd for any tests Includes the following changes: - Accommodates initCompiler's needs for additional ring Id APIs to retrieve IS's key ring identifiers, ringId and ringClass, and to align with our enumerated chipId - Elimination of redundancy in and reorg of IS's ring Id lists: RingProperties, GenRingIdList (gone) and ChipletData. - GenRingIdList has been removed. - Expand RingProperties to also include scanScomAddr and ringClass. - Member of ring and chiplet properties structs have been renamed in consistent camel style (no longer using "iv_" anywhere). - Note that with "infrastructure (IS)" we here mean the core infrastructure codes that directly interact with and affect the image. Key_Cronus_Test=XIP_REGRESS Change-Id: I7e92af04edd10c0994718e476f6e7b77c5d124d6 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/59087 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell

TOR API code restruct: Fixing missing symbols in common_ringId API.

2018-06-28T17:54:03+00:00

Change-Id: Iaf622a739c1d9d9bd4102647170000ff6f3eb686 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50496 Reviewed-by: Thi N. Tran Reviewed-by: Kahn C. Evans Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Dev-Ready: Kahn C. Evans Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61519 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Christian R. Geddes

Update to p9_xip_tool to handle stand-alone DDCO ring files.

2018-05-17T22:05:24+00:00

In this update, we're adding support to p9_xip_tool to be able to dissect and extract stand-alone DDCO ring files, i.e. files that are DD packaged through using the dd_container API and which is the DD packaging that XIP "understands". Right now, dissect and extract (of a specific DD level) can only be achieved if the DDCO binary is attached to the XIP image as one of the rings sections, .rings, .overlays or .overrides. Key_Cronus_Test=XIP_REGRESS Change-Id: I8be00742f05b4df61652a1de6d0230bb5d203f97 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54704 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: Hostboot CI Tested-by: Cronus HW CI Tested-by: PPE CI Reviewed-by: Sumit Kumar Reviewed-by: Richard J. Knight Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56110 Tested-by: Jenkins OP Build CI Reviewed-by: Daniel M. Crowell

Risk level 3/4/5 support: Step 1 - backward compatibility and v6 image

2018-04-25T16:10:36+00:00

- Introducing RV_RL3/4/5 ring variant (RV) support for EC/EQ chiplets. - Dropping RV support for all chiplet's instance rings which saves 456 Quad bytes and 58 Nest bytes in Seeprom's TOR slots (compared to master). - Each additional risk level adds 144 bytes in Seeprom TOR slots. - Various changes to data names associated with ring variants to clarify that the notion of ring variants is now specific only to Common rings while Instance rings only have the BASE variant. - Also, removed backwards compatibility to TOR v5, i.e. from before we introduced RL2 in february. Assumption is that all images/drivers used in fips910/920 and OP920 are TOR v6. - This commit produces a TOR v6 image to ensure EKB FSP CI success. Key_Cronus_Test=XIP_REGRESS Change-Id: Icfcb1e68fd74a10ffc48ee7a5da528a8042ef3b1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56973 Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Cronus HW CI Tested-by: Hostboot CI Tested-by: FSP CI Jenkins Reviewed-by: Kahn C. Evans Reviewed-by: James N. Klazynski Reviewed-by: Joseph J. McGill Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56983 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell

Code restruct: ring_apply

2018-04-05T13:31:43+00:00

- Consolidating the three _image_ring_generation functions into a single shared, and renamed, ring_section_generation function, - Moving several data centric functions into common_ringId API, - Use of sizeof() instead of hardcoded assumptions about structure or data type sizes, - Renaming of variables which makes sense in the context of the scope of this commit, such as: - ringBuffer renamed to ringSection - ringBufSize renamed to ringSectionSize and type changed to uint32_t - Removes the backward compatibility to TORV3/V4 and now only works with latest TOR version, i.e. 6 at this point. About the Hw_ImageBuild_Prereq: - 51511 must have fully propagated into all repos and drivers used in FSP CI tests before this commit (43175) can be merged. 43175 removes the TORV3/V4 backwards compatibility to support TOR ring sections that have TOR level DD coordination. Key_Cronus_Test=XIP_REGRESS Change-Id: I0af25fa623c1c523eb0297e475066497787f3d15 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43175 Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Hostboot CI Tested-by: Cronus HW CI Tested-by: FSP CI Jenkins Reviewed-by: Prachi Gupta Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52211 Reviewed-by: Daniel M. Crowell Tested-by: Daniel M. Crowell

Additional risk level support - (step 2) Updating the image w/RL2

2018-02-22T19:22:28+00:00

This commit changes the images' .rings section by adding the TOR RL2 variant slot to the runtime Quad chiplets, EQ and EC. Specifically, we have changed the definition of the ATTR_RISK_LEVEL attribute to now have three risk levels, RL0 (prev FALSE), RL1 (prev TRUE) and RL2 (new). To accomodate RL2, a new "override" txt file has been created, ./attribute_ovd/runtime_risk2.txt and changes to many other files using the ATTR_RISK_LEVEL attrib have been updated as well. Lastly, and to allow for the inclusion of RL2 rings in the HW image, the TOR_VERSION has been updated to version 6 which will allow for RL2 support in the ring ID metadata files. p9_setup_sbe_config is updated to write the RISK_LEVEL value into scratch 3 bits 28:31, and deprecate the existing mailbox. RISK_LEVEL processing has been removed from p9_sbe_attr_setup. It's only function is to seed mailboxes which are empty via the attribute state present in the SEEPROM. Since RISK_LEVEL is zero at image build time, and explicitly cleared as a result of every customization, there's logically no need to process the RISK_LEVEL here. PPE changes to accomodate the new RISK_LEVEL mailbox location need to be implemented in the PLAT code: src/hwpf/target.C Key_Cronus_Test=XIP_REGRESS HW-ImageBuild-Preqeq=52659 - 52659 must be fully merged in Cronus and HB before this commit (53292) can be merged. This is to avoid a Coreq situation. CQ: SW416424 cmvc-prereq: 1046058 cmvc-prereq: 1043606 cmvc-prereq: 1045920 Change-Id: Ia0471219916602cc0041a2c55a1070013f66a7d9 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53292 Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Cronus HW CI Tested-by: FSP CI Jenkins Tested-by: Hostboot CI Reviewed-by: Richard J. Knight Reviewed-by: Sachin Gupta Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53321 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Christian R. Geddes

Additional risk level support - (step 1) Backward compatibility

2018-02-11T19:00:50+00:00

The purpose of this commit is to avoid a coreq situation by ensuring this commit is fully propagated through our repos and test drivers before introducing the change to the new HW image with two RLs. The commit enables simultaneous support for producing a HW image and retrieving rings from an image that has either one or two risk level (RL) rings in the .rings section. The commit however does NOT actually, yet, make any changes to the image which is the aim of the (step 2) commit 53292. Nor does this commit generate any raw ring files or process any RL2 level rings yet. Again this will happen in 53292. The commit also includes, - various related cleanups in data naming and ring file processing, - some data and invironment specific parts in ring_apply.C have been moved to common_ringId.C. Key_Cronus_Test=XIP_REGRESS HW-Image-Prereq=53292 - This commit (52659) must be fully merged before merging 53292. Change-Id: I402d53c4a3ca6a084c958321069cc6f60e04ad24 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53019 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Christian R. Geddes