talos-hostboot/src/build/configs, branch 07-25-2019

Support for ATTR_TMP and GUARD in standalone simics

2020-01-10T21:18:32+00:00

If a file called ATTR_TMP or GUARD exists in the simics search path, they will be automatically loaded into pnor when simics starts. The offset is computed when the pnor is built by way of a generated python file that we then load into simics. Change-Id: I4d68215a589dcbdaefb2a67e65d1f6928ce639fa Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/88398 Tested-by: Jenkins Server Reviewed-by: Luis P Fernandez Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Matt Derksen Reviewed-by: Nicholas E Bofferding

Automatically set VPD cache flags based on EEPROM cache setting

2019-10-17T16:29:29+00:00

Added more logic to the vpd/HBconfig file to force the correct (use hardware) values for the VPD code if the EECACHE flag (SUPPORT_EEPROM_CACHING) is set. This allows the system config files to not include the unused VPD flags anymore. Change-Id: I87f7c5f3e51e3121c081b3007164dbf21cbafba8 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/84757 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Christian R Geddes Reviewed-by: Corey V Swenson Reviewed-by: William G Hoffa

Force sbe update loop if a change in OMI freq is detected

2019-07-17T19:55:07+00:00

After we parse the SPD to determine correct frequency settings we need to check if the optimal settings found differ from the original settings we booted with. This commit adds a check for OMI frequency changes in addition to the existing nest frequency and mc sync mode checks. Change-Id: Icaf64eda225df3aab82a033866663e3103cef55f RTC: 207596 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78739 Reviewed-by: Daniel M Crowell Tested-by: Daniel M Crowell

Add planar vpd support to Axone simics

2019-06-24T15:34:29+00:00

Simics support was added so now we can read directly from hardware. Change-Id: I161a847377c7271d14bf94b2e1fa7c3c63c2530c RTC:209309 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78305 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Christian R. Geddes Reviewed-by: Roland Veloz Reviewed-by: Daniel M. Crowell

Unset CONSOLE_OUTPUT_ERRORDISPLAY in axone config

2019-06-12T14:44:03+00:00

We recently enabled the CONSOLE config flap to test the lpc console in simics. This caused a lot of slowdown during the test cases when we force a bunch of errors. This commit disables diplaying errors to the console in axone simics. Change-Id: I80f7868d80e4186d8034a0326d09a290d599ed07 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78777 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Christian R. Geddes

Enable the UART console in Axone Simics config

2019-06-03T20:37:19+00:00

Enable the code to support the console output and force Simics to display it. Change-Id: Ie7aaad150ce9191cf53387af8d147f293d98126a Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78196 Reviewed-by: Ilya Smirnov Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Christian R. Geddes Reviewed-by: Daniel M. Crowell

Force Axone simics to read all VPD from HW with config flags

2019-05-14T19:54:03+00:00

This commit will set the config flags to always read from HW rather than the old VPD cache in PNOR. Until this point in Axone we were still using an old copy of MVPD that we write into PNOR during the startup simics scripts. From this commit onward we will use the actual VPD simics provides. To handle this, some updates we needed to the PG rules for Axone. Change-Id: Ie06cefe1aec37edfc4c379ee1173bc51fc6bbe1f Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76519 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Matt Derksen Reviewed-by: Daniel M. Crowell

Enable IPLTIME_CHECKSTOP_ANALYSIS in axone

2019-04-25T17:43:48+00:00

Simics now supports the enablement so we now pass istep 6.11 (host_start_occ_xstop_handler) Change-Id: Ibc57795d645e98d7585eb45a122e3d127f16bbf1 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75563 Reviewed-by: Daniel M. Crowell Tested-by: Daniel M. Crowell

Run Axone simics all the way to completion by default

2019-04-19T15:16:13+00:00

Prior to this commit we ended the IPL at istep 14.7 and ran the CXX test suite before shutting down. This commit will allow us to run through istep 21 like a standard IPL. Change-Id: Ifb567dc30e7ecbb31ed59889ff900411633844bf Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76098 Reviewed-by: Matthew Raybuck Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Reviewed-by: Matt Derksen Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell

Compile Explorer MSS libs in our istepsmss lib

2019-04-03T20:15:04+00:00

We added P9A awhile back but forgot to add in the explorer libs. Some of the MSS hwps are requiring these so we need to add them. When we pulled this in it caused the HBI image for the Nimbus and Cumulus standalone layouts to be too large. To get around this we will not compile any Axone/Explorer HWP code in non-axone system configurations. Change-Id: I041f5f160a6e530995bbb1b350a1b2362704fbc8 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75224 Reviewed-by: Matt Derksen Reviewed-by: Corey V. Swenson Reviewed-by: Christian R. Geddes Tested-by: Christian R. Geddes