talos-hostboot/src/build/citest, branch 07-25-2019

Remove workaround setting EFUSE3 power-on value

2020-01-14T20:40:01+00:00

We can remove this workaround as it is now correct in the simics copy of the power on values. Change-Id: I7a37e17595b8932406dbc98342107a0a04d66c3d RTC: 244050 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/89264 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Matt Derksen Reviewed-by: Roland Veloz Reviewed-by: Daniel M Crowell

Update simics level to f0c3530f4fefad5236391e61ae29b1a2582636ca

2019-11-14T16:48:49+00:00

Fixes for - 2 proc axone model - BOOT_CONFIG responses for Explorer Change-Id: I30273f3b64ec5cfc28331916883c1dfdce744d0e Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/86870 Reviewed-by: Christian R Geddes Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M Crowell

HCBI-239 Enable static analysis

2019-10-09T14:51:08+00:00

Change-Id: Id07e25aeb7337060baab8eaa2bbf4e3e8df238cd Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/84660 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Luis P Fernandez Reviewed-by: Camvan T Nguyen Reviewed-by: Nicholas E Bofferding Reviewed-by: William G Hoffa

Update dimmspd used by explorers in axone simics

2019-10-07T18:56:35+00:00

We want the explorer's SPD to contain valid i2c addresses for the PMIC for simics. Currently simics has these as 0x90 and 0xC0. Normally we ould just update simics directly and then update the simics relase but there has been issues in the last few weeks getting onto a newer simics release and we need these changes to test functionality that is being added to aid with hardware bringup. Change-Id: I1e29205cef59da986092bc8b609ebe27a89c5611 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/84682 Tested-by: Jenkins Server Reviewed-by: Daniel M Crowell

Add call to fapi wrapper of exp_getidec into hwasPlat code

2019-10-03T19:15:15+00:00

The file hwasPlat.C contains the code we use to lookup and compare the IDEC information of a given OCMB when read from the card's SPD versus what is read from the card's defined registers. Recently the code that looks up the IDEC from the card's registers was made into a HWP so it could be leveraged by multiple platforms. A new wrapper has been created on the hostboot side in src/usr/fapiwrap/ that provides an interface for the hostboot platform to call in order to leverage the new EKB hwp. Change-Id: I9155767b199c9b197c010521f33cc0d418901628 RTC: 214627 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/83109 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Ilya Smirnov Reviewed-by: Daniel M Crowell Reviewed-by: William G Hoffa

Increase hostboot standalone timeout to be 75 minutes

2019-10-01T20:46:29+00:00

We were seeing normal CIs take 56 minutes which was exceeding the existing 50 minute timeout. This increase is due the adding a 2nd proc to the axone simics xml and the addition of axone related tests. Change-Id: I0fa1f2ce93efab47e4ccb7d81a13cf293b3ed5b0 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/84549 Reviewed-by: DANIEL J LARSON Reviewed-by: Matt Derksen Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M Crowell

Implement Static Analysis with cppcheck

2019-09-11T15:53:06+00:00

Cppcheck static analysis tool can now be run when compiling by running: make cppcheck And it will always run when committing without stopping the commit if an error is found. This commit suppresses some false positives found in the code. A false positive can be suppressed inline by placing “// cppcheck-suppress syntaxError” in a line before the false positive., e.g.: char arr[5]; // cppcheck-suppress arrayIndexOutOfBounds arr[10] = 0; Change-Id: I9e833a153d6b04df2f8a72cd994e43922c61c2fe RTC: 201451 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79629 Reviewed-by: Zachary Clark Reviewed-by: Nicholas E Bofferding Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M Crowell

Account for Explorer's DMB_REVISION format in its SPD

2019-09-11T15:52:05+00:00

We have been told that the field we are reading to figure out the EC level of the OCMB via its SPD (offset 0x200) is going to say 0xA0 for the first version of the card, at IBM we would call this EC 0x10. The Explorer manufacture has stated that they will increment the 1st nibble when they do match card revisions, and the 2nd nibble on minor revisions. This commit adds the logic to convert the manufacture's revision format into IBM's EC level format. It also updates the prebuilt cache we use in simics for axone to have the expected 0xA0 value for the explorer SPD stored in the prebuilt cache Change-Id: I10e9523a8fbea847e3124c256fab7bee850cb29d RTC: 214627 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82873 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Matt Derksen Reviewed-by: Daniel M Crowell

Axone 2-Proc Standalone Sim Enablement

2019-08-30T18:15:28+00:00

- XML Additions for all targets on 2nd proc Change-Id: Ib8a860e4679e08253076abbbade98f4ba172e81d RTC: 208448 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82685 Reviewed-by: Christian R Geddes Reviewed-by: Michael Baiocchi Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Nicholas E Bofferding

Update Sim level to 08_23_19_f5e686_simics.tar.gz

2019-08-26T14:55:58+00:00

Change-Id: I5f912de4fd98914e6b9f4fd9ff2cbbb2134575ad Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82772 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Ilya Smirnov Reviewed-by: Michael Baiocchi Reviewed-by: William G Hoffa